JPS59168542A - Information memory - Google Patents

Abstract

PURPOSE:To perform the logical processings including the inversion, double writing, etc. of information by attaining a logical operation both the data fed from a host (a computer, a word processor, etc.) and the memory data of an information memory. CONSTITUTION:A host 200 is equal to a word processor, a computer, etc. and performs the input, processing, storage, etc. of picture information to deliver the information to an information memory 100. A page memory 20 converts the character code given from the host 200 into the character pattern data to write it to a designated region and transfers it to a plotter 300 synchronously with the speed of the plotter 300. In this case, a logical operation is possible between the data given from the host 200 and the memory data of the memory 20 with an indication given from the host 200. The logical operation includes the writing of the host data with priority, the writing of the host data with inversion, the writing of the memory data with inversion, the memory erasion, etc.

Description

Detailed Description of the Invention ■Technical Field The present invention creates page data with bit information distribution in response to instructions from an information processing device (hereinafter simply referred to as host) such as a computer, word processor, input board 2 drawing device, etc. The present invention relates to an information storage device that outputs to an output device such as a plotter, a C'RT display, etc., and particularly relates to an information processing device, also called an intelligent interface, that also performs data processing.

■Prior Art Conventionally, the host itself creates bit information and supplies it to the output device, or the output device is equipped with a character generator and a buffer memory, and the output device creates the bit information and prints out, displays, etc. I am doing it.

Therefore, the processing standards of the host itself and the processing standards of the output device are strictly determined, and the combinations of host and output device that can be connected to each other are extremely limited, which causes various inconveniences. For example, even if the user wants to change the operating mode, it is impossible because the commands between the host and the output device are limited and fixed, and the degree of freedom of operation for the user is low.

Users can superimpose characters and bit images or halftone images, or invert one of them and superimpose it.
There are also cases where it is desired to record an inverted image. Therefore, without making any particular changes to the functions of the host or output device,
The emergence of an information storage device, that is, an intelligent interface, that connects these devices and changes or expands many processing modes and functions is desired.

■Objective The first object of the present invention is to provide an information storage device that enables various host-output device combinations and processing modes without particularly changing the functions of the post and output devices. - A second object is to provide an information storage device that enables logical processing such as inversion 1 overwriting of one or two types of information, overwriting 2 in which one is inverted, etc. in various combinations of output devices, Text (text mode), halftone images (halftone mode), and bit images (Picture 1 to Image mode) can be selectively drawn on the entire page or a specified area of the page, or simply as needed. The third object is to provide an information storage device that creates bit information by performing processing or composite processing, and the writing area processing for each of text characters, halftone images, and bit images is relatively easy. A fourth object is to provide an information storage device that is consistent with the above.

■Configuration The present invention will be explained below based on the embodiments shown in the drawings.

FIG. 1 shows a schematic configuration of one embodiment of the present invention.

In FIG. 1, an information storage device 100 is an embodiment of the present invention, which receives information from a host 200, writes bit information to a page memory of the device 100, and writes bit information of the page memory to a plotter 300. give.

The host 200 includes a word processor, a plotting and tabulating device,
Character data and coordinate data from computers, scanners, keyboards, data storage devices, etc.

It inputs, processes, and stores image information such as bit information and a-degree gradation data.

Plotter 300 is a recording device capable of dot recording. In addition to the plotter, the output device may be a CR'r display, or may be an information processing device such as a computer, word processor, or data storage device.

The information storage device +00 consists of a microprocessor (hereinafter abbreviated as CPU) board 10° page memory 2
0. Pattern memory 30. interface port 40
and a common bus 50. During initialization immediately after the power is turned on, the ROM II control program is written into the work memory RAM 12.

FIG. 2 shows the configuration of electrical elements of the CPU board 10.

The CPU board 10 is a ROM that stores a control program.
l1. RAM12 as work memory. Microprocessor (CPU) 13° Clock pulse generator 14. Control signal decoding circuit 15. Address latch circuit 16. Data Noves Driver 17. Data buffer 18. (Retei check circuit 19. Address multiplexer 11a
, memory refresh control circuit 12a, novel timing pulse generator 13a, address novel (sofa 14)
a, data bus buffer 15a, read/write controller 1-
It includes a roll 16a2 interrupt control circuit 17a, a timer 18a, and a common bus 50.

FIG. 3 shows the configuration of the page memory 20. The page memory 20 consists of 144 64 KB D-RAMs.
．． 024 KByte memory array 1-21, address multiplexer 22. Input/output/<
Sofa23. It consists of a refresh control circuit 24 and a unit selection circuit 25).

FIG. 4 shows the configuration of the pattern memory 30. The turn memory 30' stores the bit information of the character pattern (1 character 48 vertical lines = 48 dots, 3 horizontal bytes = 24 dots) and the bit information of the density gradation number (turn (1) (turn 8 x 8 dots)). A memo 1 array 31 is provided for storing information.Characters (turns include 1 Japanese 8 letters, alphabets, numbers, and other necessary characters and symbols, density gradation, A turn number, contrast, a lightness, etc.) Contains 4 groups with different tones, each group 64 patterns (64 gradations), totaling 4 x 64 patterns.Pattern memory 30
In addition to the memory array 31, the memory array 31kl
nノ (Write turn information, from memory array 31) (
Memory address selector 32 for reading turn information. Memory bank selector 33. A timing pulse generator 34 and a buffer 35 are provided.

J2 indicates a connection terminal portion.

FIG. 5 shows the configuration of the interface port 40. Interface port 40 is Centronics interface 4 which is an interface with host 1-200.
1. A plotter interface 42 is an interface with the plotter 300, and a serial interface 4 is a serial interface for exchanging data with other external devices.
4゜DMA (Direct; Memory Acc
ess) controller 43, bus interface 45
It consists of a two-person output buffer memory 46, an R5232C (parallel interface) 47, and a +1542248.

The sensor 1 to the rotary interface 41 are parallel interfaces, and accept data from the host 200. Plotter interface 42 is an output interface and outputs page data to blocks. The serial interface 44 is a bidirectional interface, and sends and receives data. The buffer memory 46 can be used for wavelengths as a work memory or part of a p1 memory (page memory).

Next, the functions of each element will be explained in more detail.

Memory Unit 1-21 The memory unit 21 is divided into four subpages based on address classification, and each subpage is further divided into four banks. This situation is shown in FIG.

The numerical representation of the address in FIG. 6 is a hexadecimal notation (usually expressed as 1).

When performing DMA transfer, since the DMA controller 43 has the CPU No.
Transfer data is stored in the I10 area corresponding to CPU13.
AGENO IjRITIE L, DMA:1nl-0
- control the controller 43;

When erasing the memory of the memory unit 21, PAGE
NO is optional, and WRITE t, MSB bit ON data is written in the I10 area, 4 pieces of data are written in 64 KB of 8000+4-8FFFFH. All memories can be written simultaneously in 64-byte units. Data (“O” when deleting
”), 64Flyt
, etli are simultaneously written with the same data. Therefore, memory erasing time is extremely short.

The plotter interface 42 is synchronized with the tarock from the plotter 300 and transfers data in memory units 1 to 30 according to the operation of the DMA controller 43.

1) The MA controller/13 performs block transfer in units of 300 Bytes; each time the transfer of 300 r3 yee is completed, the common bus 50 is transferred to the CPU], without returning to 3. Plotter 3
To command 1 to 00, the status from the plotter is C
PU]3.

The Centronics interface 41 controls data transfer between the CPU 13 or DMA controller 43 and the host h2Qo. When the CPU 13 directly reads data, an interrupt is generated by the strobe signal from the post 200, and an acknowledge signal is generated by reading the data from the CPU 200. In data transfer between the DMA controller 1 and the roller 43, a DMA request is issued to the DMA controller 43 every time a slave signal is received. Generates an acknowledge signal when data is stored in memory.

The serial interface 44 controls serial transmission and reception of data by the DMA controller 1-roller 43 or the CPU 13. , DMA controller 43, the serial interface 44 requests DMA when the transmit buffer is empty or when the receive buffer is filled with data. When the CPU I3 directly handles transmission/reception data, one interrupt is generated and a service request is made to the CPU 13.

The buffer memory 46 has addresses FCOOO to FDF.
It is a FF memory and can be accessed by the CPU 13 and the DJ controller 43. By turning off the dip switch, the memory 4G is disabled.

Next, the sending procedure of the DMA controller 43 will be explained. First, specify the command register, specify the bank NO, specify the DMA transfer address, and transfer the DMA transfer yt, e.
Specify the number, specify the mode register, and reset the mask register. This starts DMA. DM
When A is completed, the mask register is set to 1-.

The plotter interface 42 reads the status of the plotter 300, sets the DMA controller 43 if recording is possible, and specifies and sets a command. When the command shell is specified, data transfer by interruption is started, and when the data transfer for all lines has been completed for the set number of sheets, the DMA mask register is set.

The Centronics interface 41 sets the DMA controller 43 at the time of DMA transfer, then transfers data by interrupt, and when the transfer is completed, sets the DMA mask I register to 1.

During DMA transfer, the serial interface 44
Set the DMA controller 43, change the serial mode to Sera 1, and set the serial command. This starts data transfer by interruption. Upon completion of data transfer, l) set the MA mask register;

The page memory bit map, data transfer, command format, etc. are as follows.

(1) Basic form a, page memory focus map size 3296 bits vertically 1 - (line) x 2400 bits horizontally 4] 2 Bytes, e
X 300 Bytes, eb, Bitmap writing method Full horizontal sequential scanning (by external clock synchronization) C. Bitmap reading method Full horizontal sequential scanning (by external clock synchronization) d. Data transfer mode (receiving) B) Text ) Modero) Halftone mode C) Bit image mode e, 4 types of halftone expression (4 groups) each group has 64 density gradations One density pattern is 8 x 8 dot square matrix f, bitmap compatible Print area 279 mm long x 203 mm wide (2) Page memory bit map a, horizontally divided into 4 (divided into 4 subpages) l subpage 824 lines (pitch l-) x 2400 bits. Each subpage consists of 4 banks.

b. Specify the starting position 1 of the addressing method as a relative address (the starting position is an absolute address). The coordinate origin is at the top left.

The starting address is common to each motoy (9 ports) and (c) in the x (horizontal: horizontal) direction in Byte (8 Bj te) units.

The y (vertical: vertical) direction is also Byte (8Bite: 8
1ine) unit.

b, Address unit horizontal direction Byte unit (from left to right) vertical direction 1i
ne unit (from top to bottom) C0 end address 1 address designation The end address is a relative address with respect to the start position, and corresponds to the number of columns of data.

b) Text mode is unspecified. It is determined by the character size, character pitch, LF amount (line feed amount), and number of lines.

In halftone mode (mouth), the horizontal direction is the number of blocks (IByt,
(e unit), vertical direction is also the number of sections (81ine: IByt
;e).

In the Pi1-image mode of c), the horizontal direction Byt,
e unit, vertical direction is 1ine (bit) unit.

d. Range that can be written in the valid data bit map memory (3296 dots vertically x 2400 dots horizontally). Data (bits) that exceed this range (writable area) are invalid.

In the case of B) Text 1-mode, the range does not exceed the maximum number of existing addresses.

(3) Data transfer a, character data (character code data) alphabets, numbers, and kana conform to JTS C-6220. Based on 8 unit code. For Kanji mode, JTS C-6226
Compliant.

b, Halftone density data I Byje/ward; Binary (0-6
3) Ward = pattern = 8 x 8 bits There are 32 functional character codes from 0 to 31, which occupy binary codes from 0 to 31, and letters, numbers, and symbols are assigned to 32 to 120. Therefore, to prevent confusion with these, the density gradation is set to 0.
The data specifying 63 is a value obtained by adding 128 to the value indicating the real value, and when decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

C, bit image data 1 bit/pel; nyte unit MSB...
L (leftmost pixel) LSB...R (rightmost pixel) d,
Numerical data B-inary; Byte unit e unit - data transfer order from MSD to LSD (from L to R: transfer the right Byte sequentially from the left end 113yje).

f, control code JIS C-6220, 8, extended control code using a functional character code and ESC code using the @ sign. Commands using ESC codes are completed with SP.

SP = 5 pace.

Note that there are 32 functional character codes from 0 to 31, and [3ynary coats 0 to 31 are occupied, and 32 to 120 are assigned alphabetical characters, numbers, and symbols, so these In order to prevent confusion, the data specifying the density gradation 0 to 63 should be the value indicating the real value plus 128, and when decoding it, 128 should be subtracted from the content of the gradation data to determine the actual gradation. Find the indicated value.

(4) Control command The contents of the control command are as follows.

a, Command format % expression % b, Area specification command format ESC+ (letter) + xl x2 y+ y2 +c1
c2 C3c4 +5pXjX7: Horizontal start address (
Absolute address) y+y2: Vertical start address (absolute address) CIC2: Horizontal end address (relative address) c
3c6: Vertical end address (relative address) Relative address is a value from 1 to 1 from the start address. Each address data is 2 bytes. Alphabetic characters indicate mode specification or command type.

C, Defold The mode is text mode, and the start address is the coordinate origin.

d.Mode specification Text mode ESC+A+x I
Since text mode and other modes always have a mode specification, there is no end address specification in text mode.

Halftone mode ESC 10G 10n + 5P n=0-/l: n=0 ends halftone mode, n=
1 to 4 designate each of the four groups of gradation types.

Pi1-image mode ESC+13+Xl x2 y1y2 +c1c2 C
3C4+spe0M included format % formula % n=o or 1; n=o is memory clear & write.

n=1 is overwriting (OR of memory data and transfer data)
. The data is "1" for recording, and "0" for non-recording. n=
2 is exclusive OR (exe, OR) writing.

f, Entire page memory erase ESC+E + SP g, Partial page memory erase ESC+D+x1 x2 yl y2 +cI C2C
The 304+SP address is in 81ine units.

h1 Character size specification ESC + S + n + SP n = 0 to 5; n = 0 is the same size (reset), n = 1 is 1 times the width and 1/2 times the height, n = 2 is j times the width and 2 times the height, n = 3
is 2 times the width and 1 time the height 2n=4 is 2 times the width and 1/2 times the height, n=
5 indicates double width and double height.

n=o instructs to reset the character size, and is set to the same size by reset (default).

i0 character space ESC+H+n+SP n = O~32, and spaces are shown in dots.

j0 line spacing ESC+V+n+SP n is a number with 81jne as a unit of -. n to default 1
=0°k, print & memory clear ESC+P 10n 15P n=0 to 99, representing the number of printouts (number of page memory transfers). If n=0, it is assumed that n=1.

1. Print and non-clear ESC+N +n+5P n=0 to 99 represents the number of printouts (number of page memory transfers). If n=0, it is assumed that n=1.

m, Definition of carriage return (CR) ESC 1R+n+5P n=o is only CR, n=L is only line feed LF without CR, n=2 is CR and line feed 1. Both F.

Definition of n, line feed (LF) ESC + F + n + 5P n=o and F only, n=l is CR only, n=2 is both CR and F.

Note that there are dip switches for setting the definitions of CR and LF, and when the definitions of m, . . . , n are not commanded, the definitions set by the dip switches are followed.

0, return CR p, line feed LF With the above configuration and the control program stored in the ROMII, the information storage device 100 has the following characteristics in outline.

(1) The memory unit 21 has a memory (page memory) that is equal to or more than the number of pixels (dot number = bit number) for processing one page of the plotter 300, and (a) converts character codes from the host 200 into character pattern data (bit (pattern: pixels) and written in the area specified by the host 200 of the memory unit 21;
Converting the data into a halftone pseudo-halftone pattern (reading the bit information of the halftone pattern corresponding to the halftone data) and writing it into the area specified by the host h290 of the memory unit 21; c) the host l-200 Pi1-data (pixels) from
A page memory is created in bits (pixels) in three modes: 1) writing the data directly as a bit image into an area specified by hosts 1 to 200 of the memory unit 21; It is possible to switch between three modes within one page.

(2) Writing to the memory unit 21 is performed by setting the writing start position of each mode to the nth power of 2 in pixels (n =
3). It is preferable that n≦5.

(3) In (2) above, in the bit image mode (c), the end position that defines the end of the specified area is specified as a relative value from the start position in the same address unit as the start position.

(4) In (2) above, if there is no particular designation from the host 200, the writing start position is immediately after the device 100 is started (when data is received after power is turned on), and the writing start position is from beep 1 to information. Write from the coordinate origin of the memory unit 21, in other cases, the start position specified immediately before is the return position, and if the previous end mode is the bit image of c), from the return line feed position, or from the return line feed position of b). In the case of a halftone pattern (such as a character pattern or a mouth), the specified address is the address following the address that ended immediately before.

(5) The host 200 can specify the number of times one page worth of memory data is output from the memory unit 21, and the host 200 can also specify whether to retain or erase the data in the memory unit 21 after that number of data outputs. be.

(6) Data from host 200 and memory unit 21
It is possible to perform logical operations on the memory data specified by the host 200, and update the result of the operation to the area specified by the host 200. Logical operations include logical sum (OR), exclusive OR (Exc, OR), priority writing of host data, and inverted writing of host data.

These are inversion writing of memory data and memory erasing.

(7) Memory data 1 to 21 are transferred to the plotter 300 in synchronization with the speed of the plotter 300.

(8) It has a standard command table for interpreting commands from the host h200 to the device 100, and when a person receives a load from the host l-200, he or she rewrites the command table and uses it to interpret the command, and the post 200 It is now possible to change the command table from

(9) In (8) above, the command format is functional character code, character code, rose, meter (numeric code)
The number of each used is variable length (not limited).

(10) In (8) and (9) of J1, the command table is a variable-length matrix, and the lengths of its rows and columns are variable (not limited).

(]1) In (8) to (10) above, each command is assigned to each column, and each column has a line for the number of characters used in the command, a line indicating the end of the character code, and a line for parameters. This is the number of lines corresponding to the line indicating the size and the line indicating the processing routine.The line indicating the end of the character code in each column is set to 0, and the end of the used column string (command string) is the first line. The row of the column (function character code string) is determined as "0".

(12) It is possible to store character patterns in the same size memory, reduced memory, and enlarged memory, and store character pattern data (focus) in these modes according to the character size specification from the host 200. to memory.

(13) In (12) above, the vertical size and horizontal size can be selected separately, and character pattern data (bits) are set in vertical and horizontal sizes according to instructions from the host 200.
is stored in the memory unit 21.

(14) The driver-flix configuration (bit data distribution) of the original character pattern is an integral multiple (1 or more) of the address unit when specifying the writing position, and the inter-character space is the address unit. It is an integral multiple (including 0) and can be specified from the host 1-200.

(15) In (14) above, the top 1 of the character pattern
~The matrix structure is such that the vertical direction is an integral multiple of twice the address coronation, and the space between character lines is an integral multiple of the address unit (
(including 0) and can be specified arbitrarily from the host 1-200.

(16) There are four types (four groups) of halftone patterns, and each group has 64 pieces (64 gradations). In (1) above, tone data (density data) from the host 1-200 is stored in the area of the memory unit 21 specified by the host 200 from among the halftone pattern groups specified by the host 1-200. Identify the halftone pattern specified by and write that pattern.

(17) In (16) above, when the host 200 notifies (declares) a halftone prior to the transfer of tone data, the tone data is stored in at least IBit; The IByte including data indicating that there is a certain thing is interpreted as gradation data.

(18) In the above (17), the IByte gradation data includes multiple bits of attribute data (data indicating the group) specifying the gradation group.

(19) In (16) above, the host 200 writes the gradation storage write area (closed area: start end address and end address)
Transfer the specified data. When specifying a writing area in this way, the host 200 also transfers attribute data specifying a tone group.

(20) The host 200 can define the functional character codes CR (plotter return) and LF (block line feed) using commands.

(21) When there is no definition of CR and LF from the host 200 - (default) follows the definition according to the state of the designated switch that defines these definitions.

(22) Equipped with a DMA controller 43,
Image data (pixels) is transferred from the memory unit 21 to the plotter 300 by DMA controller 1-roller 4.
3 to the 8-bit buffer and plotter 30
It converts into serial data synchronized with the recording operation of 0 and outputs it to the plotter 300.

(23) The DMA controller 43 can also be applied to data input/output with the host 1-200, and data transfer with the host 200 can be performed in a CPU mode in which data is first taken into the accumulator of the CPU 13 and then sent out, and a DMA controller The data can be transferred in DMA mode using 43.

Table 1 below shows the contents of the standard command table.

A comparison between each column 1-16 of Table 1 and the contents of the command is shown in Table 2 below.

Table 2 **Memory data inversion specifies that the data in the page memory is inverted and updated. The command is ESC+I+n+SP, where n=O is positive (
(no memory inversion) instruction, n=1 is inversion (negative image)
Instruct rewriting.

*** Rewriting the command table instructs to add and change the contents of the table shown in Table 1.

The command is ESC+X+7. I z2 Z37. L
ZCZ8 +SP is present, Zl is data indicating a numerical value specifying column M, z2 to Z6 are rows N = l to 4, respectively.
This is information data to be written to.

Next, the operation of the CPU 13 based on the control program stored in the ROMII will be explained.

First, reference is made to FIG. 7 which shows an overview. When the power is turned on, the CPU 13 undergoes initialization, declares variables, defines subroutines, and proceeds to the main program. In variable declaration, define all variables used in the control program. In subroutine definitions, subroutines that are called from the main program and other subroutines are defined. Each processing part that makes up the program is made into subroutines as much as possible, and data processing is executed by calling these subroutines. The main subroutines are shown in Figure 7. Subroutines include elemental subroutines that perform only one process, and compound subroutines that call them to perform a group of processes. .

The main program calls element subroutines or composite subroutines in the order of processing steps and repeats them so that a series of data processing is executed.

In the initial setting of the main program, a subroutine (force) is called to set a read/write area (coordinate origin immediately after power is turned on) in the write area setting table. Next, subroutine (d) is called to write standard commands as shown in Table 1 into the command table.

Furthermore, subroutine (a) is called to set initial values (defaults). Then, subroutine (a) is called to erase the entire page memory (31). and the command (
command).

When a command arrives, data processing begins. In data processing, first a subroutine (N) is called to interpret an instruction (command), and then a subroutine (N) is called to process and set parameters in the command. Next, a subroutine (N) is called to select the processing operation specified by the command. When a processing operation is selected, processing such as memory reading is performed according to a subroutine that executes the processing operation.

When the processing is completed, the process returns to the instruction waiting state before data processing.

Next, each of the subroutines will be explained with reference to FIGS. 8 to 39.

(A) Initial settings (Figure 8) Start address input registers 5AX (x coordinate) and SA
Clears Y (y coordinate), clears start atone storage registers XADR (x coordinate) and '/ADH (y coordinate), and clears virtual bitmap space coordinate registers X, V. Next, character pattern and halftone pattern 1
Set the 4ft (x) of the area (section) to 3 bytes (24 dots), set the height to 6 bytes I- (48 dots = 48 lines), set the space between characters to 1 byte (8 dots), and set the space between lines to 3 bytes (24 dots). Set the flag S- to 0, which instructs to convert lowercase letters to uppercase letters (since the command consists of uppercase letters, this conversion is performed even if the input is in lowercase letters for the purpose of reading). , set it to off (no conversion), refer to the pattern table (text character memory & density gradation pattern memory), set it to text mode (text character specification), return operation CR only to return CR equivalent to n = O. and change action LF
Set only the line feed LF equivalent to n = 0, and set the font size to n
= Set to the same size as O, set without overwriting (OR writing), set without rewriting, and the number of prints (
The number of times page memory data is transferred to the printer 300 is set to 1 (this is the default setting). The writing area is
Set it to an area outside the actual writing area (that is, no writing).

(a) Erasing the entire memory (Figure 9) Set simultaneous writing to all areas, write 0 (non-recorded data) to the start address (in bytes) of the write area, and sequentially transfer it to the next address.

After performing this transfer 65,535 times (number of bytes equivalent to 9 l buffs), erasing of the entire memory is completed. That is, data in all 16 banks are erased simultaneously.

(1) DMA output (Figure io) When the plotter 300 is ready, it clears the subpage counter (register) and sets the read line to 1.
reset the hardware between the device 100 and the printer 300, set the read bank to 7, set the DNA permission and specify the DMA operating mode for the port and interface, set the address to 0, and set the transfer byte counter to 304, disables interrupts, sets the subpage to 0, and starts DMA transfer to the plotter 300. When the contents of the transfer byte counter become 0, the address is set to O again, the transfer byte counter is set to 304 again, and DMA is activated.

Thereafter, each time the number of transferred bytes reaches 304 (transfer bytes (each time the content of the - counter becomes 0), the read line is moved to the next line, and when the read of one bank is completed, the read of the next bank is started. - When reading of a subpage is finished, reading proceeds to the next subpage.

When the number of read lines reaches 3296, DMA is prohibited, interrupts are enabled, and this subroutine ends.

(1) Printer 1- (Figure 11) When the plotter 300 is ready, the above-mentioned (1) DMA
Execute the output, and when it is finished, subtract 1 from the print setting number and if the residual is 0, if the memory erase after printing is set, (a) Execute the entire memory erase subroutine and (A) ) Execute the initial setting subroutine and then return to the main routine. If the memory erase after printing is not set, proceed to the (a) initial value setting subroutine without executing the entire memory erase. This print subroutine can be repeated until the number of remaining prints becomes 0.

(E) Writing area/address setting (Figure 12) If the current writing line is 3296 (this does not exist in the effective address), writing for the entire page has been completed, so the corresponding The value obtained by subtracting 3296 from the number of written lines (0)
Change the writing line to (this returns you to the beginning of writing). If the write line is 3295 or less, continuous writing is possible, so check whether it is necessary to switch banks and subpages, and if necessary, switch banks or subpages. When switching is not necessary, the number of 304 bytes for one line is added to the write absolute address to advance the write position to the next line. Then, the contents of the write line counter (register) are incremented by 1 and this subflow is ended.

(Power): P) Included area setting table (bank and subpage settings) (Figure 13) Bank number and subpage number assigned to the number of lines, using the number of lines (contents of the line counter) as an argument
There is a table in which the bank number and subpage number are determined by referring to this table, and the bank and subpage to be allocated as the write area are set. FIG. 13 shows the bank and subpage allocation obtained by referring to the table.

(g) Half-width characters (standard) (Fig. 14) Character pattern memory (character memory) is 3 by 1 horizontally.
-2 vertical 48 lines, all these bins 1-24
It is stored in the character memory in the form of 4B arranged in a row. This data is stored in the same half-width character buffer as 1
Stored in a sequence of columns.

First clear the line number counter C, calculate the primary absolute address ■y, and subtract 304 (by I-, 304 is the number of pi 1 to 1 line for one line) from the absolute address Y'/ to make the absolute address. . This subtraction is done by adding 304 to the absolute address in the third step of the above-mentioned (e) writing area/address setting, which is an element subroutine of this subroutine, and advancing the writing area by ] lines. It is. Subtraction in 304 in other subroutines described below has the same meaning.

If you set the absolute address Y'/ as above, (O)
Proceed to write area/address setting, and when exiting from there, the half-width character buffer data is memorized in the set bank. In this memory operation, the half-width character buffer contains 3 bytes 1- (241<soto) in the first column (0th line) of the character pattern as 3 bytes in the first block, and the second column (1st The 3 bytes of the line) are the 3 bytes of the second block.
As a part-time worker,... and finally the 48th column (4th
7 lines) are stored as the final 48th block, set every 3 consecutive bytes (1-) from the position (0, 3, 6, 9...) that is the number of lines to write C multiplied by 3. memory in the specified bank. That is, the pattern data bits arranged in one column are converted into 3 horizontal bytes x 4 B lines and written into the page memory.

(ri) Half-width half-length characters (Figure 15) In this case, from the character buffer that stores pattern data of 3 horizontal bytes l-X/1g lines in one column, write the number of lines C multiplied by 6 (0 ,6,12,18,...
・Read every 3 bytes after ) and store it in the set bank. That is, the data with the data of even numbered lines of characters discarded is converted into 3 horizontal bytes x 24 vertical lines and written into the page memory.

(g) Half-width double-length characters (Fig. 16) In this case, a repeat writing counter cc is used. Set by reading every 3 bytes after the position (0, 3, 6, 9,...) where the number of writing lines C is multiplied by 3 from a character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column. Then, the write line is changed and the same 3 bytes are written to the next line. That is, when the first write is completed, the counter CC is incremented by 1, the same 3 bytes are written to the write line again, the counter CC is further incremented, and the value becomes 2 from 1, and then the counter CC is incremented by 1. is cleared.

That is, the data written twice across two lines of data for each line of characters is converted into 3 horizontal bytes xw96 lines and written into the page memory.

(J) Full-width characters (Figure 17) In this case, each bit of a letter-sound line is written twice in succession into a full-width character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column, and then A string of bit information in which two consecutive bits of the same bit information are stored is stored in the character buffer. Therefore, the full-width character buffer has twice the number of bits of one character pattern. From the full-width character buffer, every 6 bytes are read from the position where the number of write lines C is multiplied by 6 (0, 6° 12.1g, . . . ) and stored in the set bank. That is, six consecutive bytes (information is the content of one line) are written to the page memory as one line. Therefore, one column of data is converted into 6 bytes (48 bytes) x 18 lines (vertical) and written into the page memory.

(S) Full-width half-length characters (Figure 18) In this case, as well, in the (C) full-width character preprocessing that precedes this routine, each bit of each character line is stored in the full-width character buffer in the same way as for the (C) full-width characters described above. Write it twice in a row,
Contains two consecutive bits of the same bit information in a full-width character buffer.
One column of Pi1-information stored in is stored. but,
Since reading from the buffer is performed every 6 consecutive bytes starting from the position of line number be done.

(C) Full-width double-length characters (Figure 19) In this case, as well, in the (C) double-width character preprocessing that precedes this routine, each focus of each character line is continued in the double-width character buffer in the same way as for the (C) double-width characters described above. and write it twice, and the same p1-information is written twice in a row in the full-width character buffer.
One column of Pi1-information stored in is stored. Also,(
(e) As with half-width double-length characters, write twice counter C.
C is used and the same line data (full-width) is written in two consecutive lines, so character data is stored in the page memory in 6 horizontal bytes l-X and $196 lines.

(S) Halftone pattern (Figure 20) There are four types (groups) of halftones, and 64 gradations are assigned to each group, and each gradation is 1 horizontal byte (8 bits) x M8 lines (8 bits). )=represented by an 8-byte pattern.

In FIG. 20, patterns 1 to 4 indicate types (groups) of halftones. The halftone data indicates the type of halftone and the density gradation. The data indicating the type of halftone is saved as is.

First, to explain from the beginning of the flow, 1 from the halftone data.
Subtract 28. As explained earlier, this is defined by the JIS c-a22o, sBt place code standard (ASCII code) in which the functional character code, alphabetic characters, and symbols of the command are numbered from O to 120. For example, this standard assigns numbers to functional character codes, letters, and symbols. Therefore, if the gradations from 0 to 63 are expressed as they are in binary, confusion in identification is expected, so the number obtained by adding 128 to the gradation numbers θ to 63 is given as gradation data from the host h200 to the system [100]. I have to. Therefore, 128 is subtracted from the gradation data in subphase a of this halftone pattern to reproduce data representing 1 gradation 0 to 63 itself. Then, 1 minimum pattern is 8
Since it is a byte, the data representing the gradation is multiplied by 8 and stored in the gradation pattern read address register F.

Next, identify the readout pattern group using the saved halftone type data, and sequentially read out the Fth to 8pi1 (1 minimum pattern 64pi1-) of the group and transfer them to the half-width character buffer. Start address'/AD
Multiply R (byte) by 8 and store it in line register Y,
Store star door 1-less XADR in X register X,
Clear write line register C and set absolute address 'l'
Calculate 1=304X(V NOD 208)+X.

That is, since x and ■ addresses are consecutive in the memory, divide ■ by 208, take the remainder, multiply it by 304, and add X to obtain the absolute address ■■. Next ■v
Let the value obtained by subtracting 304 from Y'/. Next, it is checked whether or not reverse writing is set. If it is not set, the process proceeds to normal writing shown in FIG. 21, and if it is set, the process proceeds to reverse writing shown in FIG. 22.

To explain normal writing with reference to FIG. 21, first, execute the above-mentioned (e) write area/address setting to set the write area of the page memory, and then write to the set area. Write each byte of the half-width character buffer in association with the line number. Each time one byte is written to one line, the line number counter C is incremented by one line, and when the count value reaches 8, writing is completed. As a result, 1 horizontal byte of 1 minimum pattern, ML8 lines>', has been written.

Inversion writing will be explained with reference to FIG. 22. The inversion write is also performed using the same procedure as the above-mentioned normal write, but the difference is that each pin of each byte is inverted from rlJ to rOJ and "0" to [lJ, and then written to the page memory.

(C) Full-width character preprocessing For (C) Full-width characters, (S) Full-width half-length characters, and (C) Full-width double-length characters, one bit of the character pattern (character) data is horizontally transferred to the full-width character buffer. It is necessary to store two consecutive bits. This storage is performed by this full-width character preprocessing.

In this case, first clear the character read line number counter C, clear the full-width character buffer, and then read the character data (3 bytes of each line are sequentially arranged in one horizontal column; total of 3 x 48 bytes). For each 3 bytes, each pinto is written to the full-width character buffer in consecutive 2 bits 1-, and when this is finished, the counter C is incremented by 1 count, and then the next 3 bytes 1 of the character data is written in the same manner as 6 bytes 1-. and then store it in the full-width character register. and increments counter C by 1. The same applies below.

When the contents of counter C reach 144, all the processing of one character's character data has been completed, so when the character specification is referred to and a full-width character is specified, the subroutine for full-width characters (C) described above is executed. When specified (su)
Proceeds to the subroutine for full-width half-length characters, or (b) if full-width double-length characters are specified, then proceeds to the subroutine for full-width double-length characters.

(n) Pattern processing (Figure 24a and Figure 2/lb)
Patterns (fonts) include character patterns and halftone patterns. The character code follows the ASCII code of JIS C-6220, and according to this regulation, 0 to 31
Function character codes are assigned to , symbols, numbers, and letters are assigned to 32 to 120, and ]21 to 151 are undefined.

Katakana characters are assigned to 1.52 to 210, and 21
1 to 230 are undefined. Therefore, symbols, numbers, alphabetic characters, and katakana are assigned codes sequentially starting from 0. However, to prevent confusion with functional character codes, undefined codes, etc., symbols, numbers, and alphabetic characters are The code is 32 added, and in katakana it is 6.
The code is the addition of 4.

Therefore, in the case of characters, when the code is 0 to 31 (data <
2014), 121-15], (7F11<Data A0
+1) and 121 to 151 (DPII<data), this subroutine is terminated as an error. If the data is in the character allocation range, if the data is <80H (for symbols, numbers, and alphabets), 32 is subtracted from the data and it is reproduced as character data, and the data is>9F.
When the value is H (katakana), 64 is subtracted from the data and the result is reproduced as character data. As a result, the reproduced character data returns to character data in which numbers, symbols, alphabetic characters, and katakana are assigned in continuous codes.

Next, the character code is multiplied by 144 and this is set as the read address F of the character pattern memory (character memory). This is to specify the start address of the character data since 144 bytes are allocated to one character. Next, read the character data from the pattern memory and input 8
Multiply it and store it in line register Y, store the start address XADR in X register and advances the start address XADR to the next one.

In the case of halftone mode, its density gradation data is the sum of 128 as already explained, and 128
If ≦data≦191, the above-mentioned halftone pattern subroutine is executed, the start address is updated, and this subroutine is ended. If the data is outside the range, this subroutine is terminated and the halftone pattern subroutine is not executed.

(i) CR (return) operation setting (Fig. 25) This subroutine performs (a) initial value setting (default), (n) instruction decoding, which will be described later, or CR specification data stored in register CR by dip switch reading. Update the page memory read/write address based on the page memory. 0 in the CR specification data instructs to execute only CR, so in that case,
Set the axis start address to the first start address.

Since 1 of the CR specified data instructs to execute only F,
In that case, the Y-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. CR specification data 2 specifies both CR and LF, so in that case, set the s-axis start address to the first start address, and set the y-axis start address to the number of lines equivalent to the character size L and line spacing V. Update to the value added to the current value.

(H) LF (Line feed) setting (Figure 26) This subroutine performs (A) initial value setting (default), (J) command decoding (described later), or based on LF designation data stored in register LF by dip switch reading. to update the page memory read/write address. LF
Since the specified data 0 instructs execution of only LF, in that case, the Y-axis start address is set to the first start address. Since 1 in the LF designation data instructs to execute only CR, in that case, the X-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. LF specification data 2 is CR and LF
are specified together, so in that case, set the X-axis start address to the first start address, and update the V-axis start address to the current value plus the number of lines equivalent to character size I and line spacing V. .

(n) Centronics input (FIG. 28) When the interrupt prohibition is released, a ready (receivable) signal is output to the host 200. When data is received from the host 200, the data is taken in from the Centronics interface 41, the host 200 is set to busy (reception not possible), and interrupts from outside are prohibited.

(TE) Bit image processing (Figures 27a and 27b)
Figure) Since 8 vertical lines (1 byte) are one unit of 7 traces, in order to convert this to an address in line numbers, multiply the ■axis start address by 8 and set the Y-axis in-address Y. , just set the start address for the X axis. Then, the horizontal width (■) and vertical width (J) of the area designated by the received data are set as target values. Next, the line number counter CC is cleared, the absolute address YY is calculated, and the value obtained by subtracting 304 from it is set as the absolute address yY. Next, the width counter C is cleared and reference is made to see whether or not inversion writing is to be performed, and (n) centronics input is executed to store the received data (bit data) in the focus buffer with a width of 1 minute. When inverted writing is specified, the data bits "1" and "0" are inverted and stored at this time. When one line of bit data corresponding to the width is stored in the pit buffer, (e) Execute the write area/address setting, check whether or not to write after clearing, and if it is write after clearing, set the bank. Writes bit data for one horizontal line of the pit buffer, increments the line counter CC by 1, clears the horizontal counter C, receives l horizontal line width, writes to the bit buffer, and sets the write area address. and writes to a predetermined bank of the page memory. When the contents of the line number counter CC reach J+1, writing of the w:J line has been completed, so this subroutine is ended. If write after clear is not specified, after setting the write area address, transfer the width (C+1) from the page memory setting bank to the memory buffer.
byte) and clear the bit data counter BC.

When overwriting is specified, each bit of the pit buffer and each bit of the memory buffer are logically summed (OR)ed in the order in which they are arranged, and the updated memory is stored in the focus buffer, and the bit data counter is set to 1 for each bit of updated memory. When the count is increased and the contents of the bit counter BC exceeds the contents of the width counter C, that is, when the logical sum of one line in width is performed, the contents of the pit buffer are written to the setting value of the page memory, and the line number counter CC is set to 1. Count up. When exclusive OR is specified, the bit data in the page memory is exclusive ORed with the bit data in the pit buffer using the same procedure as for logical OR, and the bit data is transferred to the bit data (ZFA). Update memory and then write to page memory.

(G) Conversion of lowercase and uppercase letters (Fig. 29) Referring to the command table shown in Table 1, commands are composed of uppercase letters and numbers. This conversion subroutine is provided so that commands can be interpreted even if they are in lowercase English letters.

First, an uppercase English letter is 96〈data〈123, so anything outside of this is a lowercase English letter. The English small-M character number is a code that is 32 times larger than the English capital letter, so it is 3 from the input code.
Correct the code indicating the value obtained by subtracting 2 into a character code.

When the conversion is completed, the flag S is set to OFF, indicating that conversion is not required.

(S) Partial erasure (FIGS. 30a and 30b) Partial erasure is equivalent to storing "O" in a designated area in the same manner as the above-mentioned (te) bit image processing. Since it is sufficient to store rOJ in the entire designated area, partial erasure is performed by writing "0" to the leading bit of each line in the designated area and transferring this along the line.

(d) Command table writing (command table tabulation) (31st
Figure) 11AM command table write area address cy=.

Clear all data from ~50 (column M in Table 1).

This is the content from Step 1 to Step 7. Next, data is written in each column H and row N and the meaning of their matrix as shown in Table 1.

(nu) Instruction 11jii! Reading (FIG. 32) Clears the row N register CX and column N register CY, and receives command data at the aforementioned Centronics input. If it is a command, the beginning of the data is always ESC, and if it is other than that, it is data indicating 0 or a number of 32 or more. Therefore, if the data is not 0 and not 32 or more, the lowercase/uppercase conversion flag Sv is referred to, and if it is on, conversion is necessary, so the above-mentioned (g) lowercase/uppercase conversion is executed.

If it is off, the conversion has finished, so refer to the data as is and compare the contents of the input data with the data at the matrix intersection specified by the contents of the row N register Cx and column N register Cv (Table 1). Then, the contents of registers CX and Cv are counted up until data matching the input data is read out.

That is, first, the function character code of the input data is entered in columns 0 to 50 (row N=O of the command table (Table 1)).
It is possible to write M=50, and in the example in Table 1, it is 121.
6 has been written, and A = 17 to 50 are empty: "0" is written in all) and data 1, 2, 3, etc. are compared sequentially from that of M = O. and if it matches, H
is fixed and the row N is sequentially increased by 1, and the data at the matrix intersection specified by A and N is compared with the data below the functional character code of the input data.

If you read and compare the data in row N=3 and they are not the same, then increment 1M by 1 and compare the same data.If the data in row N=0~3 match the input data, then The value of column H at this time is the input command NO, and the data of row Nl of the column indicates the subroutine specified by the command. Since the default is text mode, the function character code part of the command is rOJ.
At this time, 0, which instructs pattern processing (font processing), is stored in the processing instruction register OP. In other cases, data in row N=4 of the column having data matching the input command data is stored in the instruction register OP.

(v) Processing operation selection (Fig. 33) In this subroutine, a subroutine is set according to the contents of the processing instruction register OP. The O in the processing instruction register OP indicates pattern processing (font processing) as described above.
Therefore, in this case, (n) pattern processing is set. 0P=2 performs (TE) bit image processing, 0P=
0P= (1) print, 0P=14 (1) print, 0P-5 (b) whole memory erase, 0P=
16 (1) print, OP = 27 (evening)
When OP=28, set the CR operation, (H) LF operation setting, and when 0P=24, set the (E) instruction rewrite.

()) Parameter calculation (1) (Fig. 34) When there are four parameters in the command: XI, X2, yl, and Y2, these indicate the start address. xl is X
Upper 8 bytes of address + X2 are lower 8 bytes rYI
is the top 8 hate of X address.

Since y2 is the lower 8 bytes, 256Xx1+x2 is the start address register SAX number, 256Xy1+
Y2 is stored in the start address register 5AVE:.

(c) Parameter calculation (2) (Figure 35) If the command parameters are 8, sl Store in address register SA■, 01 to c4
indicates the end position (relative address) from the start address, so 256
Store a in y-address byte counter YADCI:
XADC is stored in the target byte register I, and a value obtained by multiplying the contents (bytes) of 'i'ADC by 8 and further adding 7 is stored in the target in-number register J. Note that adding 7 means that when '/ADC is 0, it is the number of lines that is 0.
This is because it refers to the area from 7 to 7, so it is set to 7 at the end.

(H) Parameter setting (1) Start address parameter (Fig. 368) Execute the parameter calculation described in ()) and store the calculated address in the X address register (current position register) XADR and the X address register. Both are data in bytes.

(2) Bit image parameters (Figure 36b) Execute the above-mentioned (c) parameter calculation (2). The X direction is in byte units, and the X direction is in line units.

(3) Partial erasure parameter (Figure 36c) (c) mentioned above
Execute parameter calculation (2). The X direction is in byte units, and the X direction is in line units.

(4) LF operation parameters (Figure 36e) Register LF
The value of parameter n in the LF operation designation command is stored in .

(5) Halftone mode parameter (Fig. 36d) The value of parameter r1 in the halftone mode command is stored in the pattern table selection register PT.

When n=0 (end of halftone mode: return to default, same meaning as specifying text mode), set the font size to 3.
Byte (half-width), vertical byte 6 bytes (48 lines: full-width)
, set the character spacing H to 1 byte and the line spacing V to 0 (default). When N=O is not (halftone instruction), set the horizontal W of the pattern size to 1 by 1-,
Set the vertical length to 1 byte (8 lines), and set the inter-pattern space horizontal H and vertical ■ to 0.

(6) Character spacing parameter (Figure 36f) Store the value of parameter n of the one character spacing designation command in the character spacing parameter register H.

(7) Reverse write parameter (Figure 36g) Write the value of parameter n of the memory data inverse designation command to the reverse write instruction register RE.

(8) Number of prints when memory is retained after printing (Fig. 36h) The value of the parameter n of the print non-clear command is stored in the print number register CN.

(9) Number of prints from print 1 to after memory erase (
(Figure 36i) Store the value of parameter n of the Print Clear command in the print number register CN.

(10) CR operation parameters (Figure 363) Register C
The value of parameter n in the CR operation designation command is stored in R.

(11) Character size selection parameter (Figure 36) Store the value of parameter n of the character size specification command in the character size register S, and when the stored value (n) is 0, the horizontal V is 3 bytes (half-width ), set the vertical length to 6 bytes (48 lines). When it is 1, the lever is 3 bytes, and the L is 3.
Byte, when 2, W is 3 bytes, L is 12 bytes, when 3, beam is 6 bytes, [, is 6 bytes, 4
At that time, set the lever to 6 bytes and L to 3 bytes.

5, set the lever to 3 bytes and L to 12 bytes.

(12) Line spacing parameter (Figure 361) Value of parameter n of the line spacing command.

Stored in the line spacing register ■.

(13) Overwrite parameter (Figure 36m) Write the value of parameter n of the write specification command to the write specification register RO
Store in.

(14) Instruction rewrite parameters (Figure 360) Clear the row N counter C, and write the column data to the 1st 0 position of the rewrite register EX, and the position 1 corresponding to row N = 0° 1.3.4. 2.3 and 4, sequentially the command N=
O, N=1. , N=3 and N=4 data (parameters) are stored.

()) Parameter setting selection (Fig. 37) Similar to the above-mentioned (v) processing operation selection, the content of the processing instruction register OP is referred to in (j) instruction decoding, and the above-mentioned ((v)) is selected according to the contents of OP.
h) Execute the subroutine for parameter setting (Figures 36a to 36n).

(v) Parameter processing (Figure 38) Referring to the data stored in the processing instruction register OP in the above (v) instruction decoding, if it is O, it is text mode, and if it is 27 or 28, it is CR. (return) or LF (line feed), this routine ends. In other cases, clear the counter C, read the parameters one by one using the Centronics input, and set the counter to 1.
The count is up and the number of reads is the command row N =
The number P of the parameter 3 is the number specified in advance, and the Centronics input data indicates 32 (0 indicates the end, but the function character code is 0 to 32, so
0+32 indicates the end (0) indicates the end of the command, so ()) executes parameter setting selection and ends this subroutine.

(E) Instruction rewriting In the above-mentioned (14) instruction rewriting parameters, change data (parameters) in the command are transferred to the rewriting register EX in the column, row N=O data, N22 data, N=3 data, and Nl. Therefore, the first 0 data of EX, ie column data, is stored in the command table column address register CY, and row N=O, N=1 . N=3
and N = 4 d, respectively EX(7) No. 2 1~
Write the data of number 4 and 3.

FIG. 40 shows the output timing of page memory data of the device 100. When outputting to the plotter 300,
A gate signal from the plotter 300 is applied to the data WDAy'Ak plotter 300 every line in synchronization with GATE.

By executing each of the above subroutines, the start address immediately after the power is turned on will be as shown in Table 3 below, and the subsequent start address will be as shown in Table 4 below. The rest is as shown in Table 5 of the first order.

Table 4 (Immediately after power-on) Table 5 Previous processing: Post-text processing Text secondary address Halftone: Next address Bit image: Wait for 4N constant. If not specified, it will remain stopped.

Previous processing: Post-halftone processing Text Secondary address Intermediate: Next address Bit image: Waiting for specification. If not specified, it will remain stopped.

Pre-processing two-bit image Post processing Text: Position after CR or LF operation.

Halftone mode bit image: Wait for CR or LF and subsequent designation. If not specified, it will remain stopped.

Note that the address data given from the host 200 to the device 100 is in bytes, and in text mode and halftone mode, the write start address is set by ()) parameter division (1), and in bit image mode, (c) parameter division. In calculation (2), a write start address and a write end address are set. These addresses are in bytes.

As explained above, immediately after the power is turned on, the initial settings [(1) writing area setting table, (d) command table writing and (
b) Erase entire memory] and is waiting for command input. When an external interrupt occurs, (nu) executes instruction decoding,
(f) Execute parameter processing, (v) Execute processing operation selection and execute one selected process.

Next, several types of processing operations in response to commands will be described.

(1) Rewriting the command table When a command instructing to rewrite the command table arrives from the host 200, the number of parameters (5) is set in the parameter register P by decoding the command, and 24 is set in the processing operation register OP. Next, in (to) parameter processing, five parameters are transferred from the host 200 via Centronics input. Then go to ()) parameter setting selection and 0
Since P=24, (]4) instruction rewrite parameter (third
6n), store the five parameters in the conversion register
Since P=24, the program proceeds to (e) instruction rewriting, and in this subroutine, the contents of the column specified by the first parameter of the command table (Table 1) are rewritten. Note that if a column that has already been written to is specified, it is literally a rewrite, but if a column that has not been written to (row N; a column in which 0 is written to 1) is specified, a new command is executed. will be written.

In this way, command rewriting (and writing) is performed by the host 20.
Since this can be done with a command table rewrite command of 0, the host 200 can change the commands (standard commands) set in the control program and add new commands to the device 100. That is, it is possible to change command definitions and create new commands.

(2) A text mode processing start address specification command is sent from the host 200 to the device 10.
If given 0, this is text mode since it specifies only the starting address. In halftone mode and bit image mode, an end address is always specified.

Upon receiving the start addressing command, the device 100 (
n) Set the number of parameters to 4 in the parameter register P by decoding the instruction, set 1 to the processing operation register OP,
Next, in (to) parameter processing, four parameters are transferred from the host 200 via Centronics input. Then, proceed to ()) parameter setting selection, and since 0P=1, proceed to (1) start address parameter (Figure 36a), ()) execute parameter calculation (1), and set the start address to start address register XADR and YA
DR and finish setting the text mode start address.

After that, when the host 200 sends the character code, (
N) Set OP-〇 by decoding the instruction, and since it is 0P-0, pass through the parameter processing as it is and proceed to the primary (N)
Select the processing operation to proceed to pattern (font) processing, convert the character code, read the character pattern data from the pattern memory (character memory), store it in the character buffer memory, and convert the character code according to the set character size. ) half-width characters, (ri) half-width half-length characters, (ke) half-width double-width characters, or (
C) Proceed to full-width character preprocessing.

When proceeding to one of the first three methods, address calculation is performed, and (e) V-include area/address setting is executed, character pattern data is subjected to predetermined character size processing, and is written into the page memory. (C) When proceeding to full-width character preprocessing, create character pattern data in the full-width character buffer by enlarging the character pattern data in the character buffer memory from 1 bit horizontally to 2 horizontal pinpoints, and according to the character size specification ( e) Full-width characters.

(i) Proceed to full-width half-length characters or (shi) full-width double-length characters, calculate the address there, and then (e) execute write area/address settings to apply the specified character size processing to the character pattern data. and write it to page memory.

Note that the default is text 1-mode, so when the character code is sent from the host 200 from the beginning after the power is turned on, 0P=0 is set in (nu) instruction decoding, and 0
Since P = 0, it passes through parameter processing as it is, and then proceeds to (n) pattern (font) processing by selecting (v) processing operation, converts the character code τ code, and stores the pattern memory (character memory). ) reads character pattern data and stores it in the character buffer memory, and converts it to (ki) half-width characters according to the set character size.

(ri) Half-width half-length character 2 (k) Half-width double-length character or (c) Full-width character Proceed to preprocessing. The operation is the same as when receiving the character code data described above.

(3) Halftone mode Halftone mode specification command is sent from the host 200 to the device 10
If given to 0, the device 100 sets the number of parameters to 1 in the parameter register P in (nu) instruction decoding, sets 7 in the processing operation register OP, and then sets one parameter in (to) parameter processing. is transferred from the host 200 via Centronics input. Then, proceed to ()) parameter setting selection, and since 0P=7, proceed to (5) halftone mode parameter (36d), where depending on the value of parameter n, if N=O, this indicates the end of halftone. Instructs the writing format to be the default text mode (standard)
Set to . N= ] ~ 4 specifies the type of gradation, so
At this time, the writing format is set to be continuous writing starting from 1st beep. Next, (v) processing operation selection is 0P=7, so it passes through as is.

After that, when the host h200 sends the halftone code,
(J) Set OP20 in instruction decoding, and since op=o, (J) directly pass through parameter processing, then (J) proceed to (G) pattern (font) processing in processing operation selection, and then (S) Proceed to the halftone pattern and write to the page memory. Text 1 mode 1 and halftone mode share a subroutine in this way because the pattern area is predetermined.

(4) Image mode bit 1 to bit 1 - When the image mode designation command arrives, the device 100 sets F'-8, 0P = 2 by (nu) command decoding, and then (to) sets 8 by parameter setting. Since 0P=2 in ()) parameter setting selection, proceed to (2) bit image mode parameters (Figure 36b) and (c) parameter calculation (2).
) is executed, and by selecting (v) processing operation, the process proceeds to (t) image processing, where bit data is received at the centronics input and written to the page memory.

(5) Printle non-clear or printle clear When these commands arrive, the device 100 sets P=1, 0P=10 or 11 in (n) command decoding, and (v) host parameter (n) in parameter processing. 200 through the Centronics input, then pass through the ()) parameter setting selection as is, proceed to (4) printing in the (ne) processing operation selection, execute the number of print outputs indicated by the parameter n, and select the non-clear or The page memory is held or cleared according to the clearing.

(6) Logical operations Logical operations include (S) inversion writing in the halftone pattern subroutine in the halftone mode, and inversion writing 2 overwriting (OR) in (TE) bit image processing in the focus image. ) or exclusive OR writing is selectively performed as specified in advance by the parameters of the command.

When other commands arrive, data processing [(v) command decoding - (v) parameter processing - (v) processing operation selection] is similarly executed to execute a predetermined subroutine.

Note that in the above embodiment, only the write start address is specified by the halftone mode command, but
Similar to the -Image mode 1- command, four parameters indicating the end address may be added to set the end address together with the start address in the same way as in the bit image mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1.
4 is a block diagram showing the structure of the pattern ROM shown in FIG. 1, and FIG. 5 is a block diagram showing the structure of the interface port 40 shown in FIG. 1. FIG. 6 is an explanatory diagram showing memory divisions of the page memory 20. FIG. 7 is a flowchart showing an overview of the operation of the device 100;
Figures 8, 9, 10, and 1. FIGS. 12, 13, 14, and 15. FIGS. 16, 17, 18, and 19. FIGS. 20, 21, 22, and 23. Figures 24a, 24b, 25, and 26. Figures 27a, 27b, 28, and 29. Figures 30a, 30b, 31, and 32. Figures 33, 34, 35, and 36a. Figure 36b, Figure 36c, Figure 3Gd. Figures 36e, 36f, and 36g. Figures 3611, 36i, and 36j. Figure 36, Figure 361, Figure 36m. Figure 3611, 37m1. FIG. 38 and FIG. 39 are flowcharts showing the operation flow of the subroutine, respectively. FIG. 40 is a time chart showing the data transfer timing when data is transferred from the device ioo to the plotter 300. 100: Information storage device 11: ROM12:
RAM 13: CPU3J: Pattern Memory Patent Applicant Ricoh Common Bus Co., Ltd. Figure 6 4 High/F East Figure 11 Figure 12 Commissioner of the Patent Office Mr. Kazuinu Wakasugi, Indication of Case Patent Application No. 042587, 1982
, Title of the invention Information storage device 3, Person making the amendment, Incident and relationship Patent applicant address 1-1-l''13-6 Nakamagome, Inu F11-ku, Tokyo
Name (674) Ricoh Co., Ltd. Representative Hama 1) Hiro 4, Agent 103 Telephone 03-864-60
52 Address: 2-27-6-5 Higashi Nihonbashi, Chuo-ku, Tokyo, subject to amendment

Claims (11)

[Claims] (1) Page memory in which one bit corresponds to each pixel of one page; Pattern memory that stores at least one of character pattern data and density gradation expression pattern data; Input/output interface; Instruction decoding means that decodes and sets processing operations and parameters; Executes logical operation processing set by the instruction decoding means, and reads each bit information of the page memory and each of the bit information or long bit information read from the pattern memory. A logical operation means for performing a logical operation to obtain operation processing bit information; a writing means for writing the bit information into a predetermined area of the page memory; and a page memory output means for outputting the data of the page memory a predetermined number of times. Information storage device. (2) The information storage device according to claim (1), wherein the predetermined area is an area set by instruction decoding means. (3) Theory 111! Logical operations include OR, exclusive OR, priority writing of pattern memory read information or input bit information, inverted write of pattern memory read information or input bit information, inverted write of page memory data, and page memory erase. An information storage device according to claim (1) or (2). (4) The writing means converts the input character code into character pattern data represented by the code, and writes the data obtained by processing the pattern data into a predetermined area of the page memory. Mode writing means: An intermediate device that converts the input gradation code into gradation pattern data specified by the code, and writes the data obtained by processing the pattern data into a predetermined area of the page memory. and bit image mode writing means for writing data obtained by processing the input bit image data by the logic operation means into a predetermined area of the page memory; Information storage device described in ( ). (5) The bit image writing means marks the end of the writing area as
The information storage device according to claim 4, wherein the information storage device is determined by a relative value from the start position in the same address unit as the start position. (6) In the text mode writing means, the first write area after power is turned on uses the write start end of the page memory as the start point, and after execution of any write mode, the start point of the character write area is
When the previous process is in text mode, it is next to the end point of the previous write process, when the previous process is in halftone mode, it is next to the end point of the previous write process, and when the previous process is in bit image mode, it is next to the end point of the previous write process. The information storage device according to claim 4, wherein the position is the position after return or line feed processing. (7) The halftone mode writing means uses the writing start end of the page memory as the starting point for the first convolution area after power is turned on, and the starting point of the halftone pattern writing area after executing any of the writing modes. is next to the end point of the previous write process when the previous process is in text mode, is next to the end point of the previous write process when the previous process is in halftone mode, and is next to the end point of the previous write process when the previous process is in bit image mode. The information storage device according to claim 4, wherein the position is the position after the return or line feed processing when . (8) The bit image writing means waits for a specification to determine the first writing area after power is turned on, and after executing any of the writing modes, the starting point of the bit image writing area is The scope of the above-mentioned claims is determined by waiting for the designation when the mode is set, waiting for the designation when the previous processing is the halftone mode, and determining the return or line feed processing and waiting for the designation when the previous processing is the bit image mode. The information storage device according to paragraph (4). (9) The information storage device according to claim (1), wherein the page memory output means outputs the data of the page memory a number of times set by the instruction decoding means. (10) The information storage device according to claim 1, wherein the page memory output means clears or holds the page memory in accordance with a post-output memory processing instruction set by the instruction decoding means. (11) The information storage device according to claim 1, wherein the page memory output means outputs data of a predetermined section of the page memory to the output device in synchronization with a signal provided by an external output device. (J2) The input/output interface is equipped with a DMA controller, and the page memory output means transfers the page memory data to the output device by using the DMA controller to transfer it to a parallel-in-serial-out buffer, and then transfers the data in the page memory to the output device. The information storage device according to claim 1, which outputs serial data in synchronization with operation.