JPS59168539A - Information memory - Google Patents

Abstract

PURPOSE:To select and set a character size in an information memory by writing the character pattern data to a page memory after enlarging and contracting the character data in lateral ratio and longitudinal magnification ratio corresponding to the character size parameter. CONSTITUTION:The character pattern data (bit) which is equimultiplied, contracted and enlarged in response to the sizes of characters designated by a host 200 is stored in a memory unit of a page memory 20. It is possible to select the longitudinal and lateral sizes independently of each other. Thus various combinations is possible between the host 200 and an output device since no change is especially required for the functions of these host and output device.

Description

[Detailed description of the invention] ■Technical field The present invention relates to a computer and a word processor.

Input board 9 Creates page data of bit information distribution in response to instructions from an information processing device (hereinafter simply referred to as host) such as a plotter, and serves as a plotter.

The present invention relates to an information storage device that outputs to an output device such as a CRT display, and particularly relates to an information processing device, also called an intelligent interface, that also performs data processing.

■Conventional technology In the past, the host used its own number to create bit information and give it to the output device. Tebu IJnt out,
Perform display etc. .

Therefore, the processing standards of the host itself and the processing standards of the +=Bs power device are both strict and fixed, and combinations of hosts and output devices that can be connected to each other are extremely difficult, resulting in various inconveniences. There is 1 power. For example, even if you want to change the operation mode, it is not possible, such as IJ, you can only select the size of characters in the horizontal direction, force 1 is possible, you cannot do it in the vertical direction, or vice versa, force 1 is available, and horizontal.

It is not possible to select the size vertically at the same time, or separately for horizontal and vertical, and in most cases the host-output device combination does not allow this, limiting the user's font size. Ru.

Therefore, without changing the functions of the host or output device, an information storage device with an extended function that connects them and allows a wide range of horizontal and vertical sizes to be selected with a high degree of freedom, that is, an intelligent The emergence of an interface is desired.

■Purpose The present invention provides an information storage device that enables various combinations of host and output device without changing the functions of the host and output device, and also allows selection and setting of character size in both horizontal and vertical directions. The primary purpose is to
The second purpose is to provide an information storage device that expands the character size selection function of combinations of output devices, and which is relatively easy to process text character writing areas and is compatible with various hosts and output devices. A fourth purpose is to provide an information storage device.

■Configuration The present invention will be described below based on embodiments shown in the drawings.

FIG. 1 shows a schematic configuration of an embodiment of the present invention.

In FIG. 1, an information storage device 100 is an embodiment of the present invention, which receives information from a host 200, writes bit information to a page memory of the device 100, and writes bit information of the page memory to a plotter 300. give.

The host 200 includes a word processor, a plotting and tabulating device,
Single character data and coordinate data from computers, scanners, keyboards, data storage devices, etc.

It inputs, processes, and stores image information such as bit information and density gradation data.

Plotter 300 is a recording device capable of dot recording. In addition to the plotter, the output device may be a CRT display, or may be an information processing device such as a computer, word processor, or data storage device.

The information storage device 100 mainly includes a microprocessor (hereinafter abbreviated as CPtJ) board 10° page memory 20. Pattern memory 30. Interface board 4
0 and a common bus 50. l [In initialization immediately after turning on, the ROMII control program is written into the work memory RAMI2.

FIG. 2 shows the configuration of electrical elements of the CPU board 10.

The CPU board 10 is a ROM that stores a control program.
II. RAM as work memory12. Microprocessor (CPU) 13° clock pulse generation m14. Control signal decoding circuit 15. Address latch circuit 16. Data bus driver 17. Data buffer 18. Parity check circuit 19. Address multiplexer 11a, memory refresh control circuit 12a, bus timing pulse generator 13a, address bus buffer 148, data bus buffer 15a, read/write control 16a
2 interrupt control circuit 17a, timer 18a, and common bus 50.

FIG. 3 shows the configuration of the page memory 20. The page memory 20 consists of 144 64 KB D-RAMs.
024 KByje memory array memory unit 21. Address multiplexer 22. Input/output buffer 2
3. It is composed of a refresh control circuit 24 and a unit selection circuit 25.

FIG. 4 shows the configuration of the pattern memory 30. The pattern memory 30 stores character patterns (1 character 48 vertical lines = 48
It is provided with a memory array 31 that stores bit information of dot, 3 horizontal bytes = 24 dots) and bit information of density gradation (turn (1) (turn 8 x 8 dots). Character patterns include Japanese characters, alphabets, Including numbers and other required characters and symbols, the density gradation pattern is 4 groups with different tones such as contrast and shading, each group has 64 patterns (64 gradations), totaling 4 x 64.
Contains patterns. In addition to the memory array 31 , the pattern memory 30 includes memory address selectors 32 . Memory bank selector 33. Timing pulse generator 34 and buffer 35
Equipped with

J2 indicates a connection terminal portion.

FIG. 5 shows the configuration of the interface port 40. The interface port 40 is a Centronics interface 41 that is an interface with the host 200.
1. A plotter interface 42 is an interface with the plotter 300, and a serial interface 4 is a serial interface for exchanging data with other external devices.
4゜DMA (Direct Memory Ac
cess) controller 43, bus interface 4
5. It consists of an input/output buffer memory 46, an R5232C (parallel interface) 47, and an R542248.

The centro interface 41 is a parallel interface and receives data from the host 200. Plotter interface 42 is an output interface and outputs page data to a plotter. The serial interface 44 is a two-way interface for sending and receiving data. The buffer memory 46 can be used for wavelengths as part of work memory and bit memory (page memory).

Next, the functions of each element will be explained in more detail.

Memory Unit 21 The memory unit 21 is divided into four subpages based on address classification, and each subpage is further divided into four banks. This situation is shown in FIG.

The numerical representation of the address in FIG. 6 is in hexadecimal notation (usually represented by H).

When performing DMA transfer, l) M^controller 43
has the CPU No., the PAGE No. of the transfer data is set to 1dRITE L in the I10 area of the controller 43 corresponding to the CPU 13, and the DMA controller 43 is controlled.

When erasing the memory of the memory unit 21, PAGE
No is arbitrary, MSII bit ON data is placed in VRI in I10 area, 64K of 8000+1-8FFFFH
Write data to Byte. It is possible to write to all memories at the same time with 64 Byt,e usage. data (delete r
64 Bytes in the direction of the arrow in Figure 6.
The same data is written simultaneously in units of e. Therefore, memory erasing time is extremely short.

The interface port 40 plotter interface 42 is synchronized with the clock from the plotter 300 and transfers data from the memory unit 30 according to the operation of the DMA controller 43.

The DMA controller 43 performs block transfer in units of 300 B'yte, and returns the common bus 50 to the CPU 13 every time the 300 Byte transfer is completed. Commands to the plotter 300 and status from the plotter are read by the CPU 13.

The Centronics interface 41 controls data transfer between the CPU 13 or I) MA controller 43 and the host 200. When data is directly read by the CPU t 3, an interrupt is generated by a strobe signal from the host 200, and an acknowledge signal is generated by the data read by the CPU 13. In data transfer in the DMA controller 43, a request A is issued to the DMA controller 43 every time a serial signal is received. Generates an acknowledge signal when data is stored in memory.

The serial interface 44 controls serial transmission and reception of data by the DMA controller 43 or the CPU 13. When using the DMA controller 43, the serial interface 44 performs a DMA transfer when the transmit buffer becomes empty or when data is input to the receive buffer.
Request MA. When the CPU 13 directly handles transmitted and received data, an interrupt is generated and a service request is made to the CPU 13.

The buffer memory 46 has addresses FCOOO to FDF.
It is an FF memory and can be accessed by the CPU 13 and the DMA controller 43. By turning off the dip switch, memory 46 is disabled.

Next, to explain the setting procedure of the DMA controller 43, first, specify the command register, specify the bank number, specify the DMA transfer address, specify the number of DMA transfer yte, specify the mode register, and set the mask register. Reset. This starts DMA. D.M.A.
When the process is completed, the mask register is set to 1~.

The plotter interface 42 reads the status of the plotter 300, sets the DMA controller 43 if recording is possible, and specifies and sets a command. When a command is specified, data transfer by interruption is started, and when data transfer for all lines has been completed for a number equivalent to the set number of sheets, the DMA mask register is set.

During DMA transfer, the Centronics interface 41 senses the DMA controller 43, then transfers data using an interrupt, and sets the [lNA mask register and register] upon completion.

The serial interface 44 is used during DMA transfer.

Set the DMA controller 43, set the serial mode, and set the serial command. This starts data transfer by interruption. When the data transfer is completed, the DMA mask register is set.

The page memory focus map, data transfer, command format, etc. are as follows.

(1) Basic form a, page memory bitmap size 3296 bits (vertical) x 2400 bits (horizontal) 412 Bytes
300 Bytes b, Bitmap writing method Full horizontal sequential scanning (by external clock synchronization) C. Bitmap reading method Full horizontal sequential scanning (by external clock synchronization) d. Data transfer mode (receiving) b) Text mode ) Halftone mode C) Bit image mode e, 4 types (4 groups) of halftone expression, each group has 64 density gradations, one density pattern is 8 x 8 dot square matrix f: print area corresponding to bitmap 279 mm x Width 203 mm (2) Page memory bit map a, horizontally divided into 4 (divided into 4 subpages) 1 subpage 824 lines (bits) x 2400 bits. Each subpage consists of 4 banks.

b. Addressing method Start position specified relative address (start position is absolute address)
. The coordinate origin is at the top left.

The start address is common to each motor, and is set in the X (horizontal: #k) direction in units of 1yhie (8Bjte).

The y (vertical: vertical) direction is also [lyt, e (8Bj shi e:
81ine) units.

b, Address unit horizontal direction Byte unit (from left to right) vertical direction 1i
ne unit (from top to bottom) c, #end address specification The end address is a relative address with the starting position as a reference, and corresponds to the number of columns of data.

b) In text mode, unspecified. It is determined by the character size, character pitch, LFjl (line feed amount), and number of lines.

In halftone mode (mouth), the horizontal direction is the number of wards (l Byt
e unit), and the vertical direction is also the number of sections (81ine: IByine).

In bit image mode (c), the horizontal direction is byte units, and the vertical direction is 1ine (bit) units.

d. Range that can be written in the valid data bit map memory (3296 dots vertically x 2400 dots horizontally). Data (bits) that exceed this range (writable area) are invalid.

b) In the case of text mode, the range does not exceed the maximum number of existing addresses.

(3) Data transfer a, character data (character code data) alphabets, numbers, and kana conform to JIS C-6220. Based on 8 unit code. For Kanji mode.

Compliant with JIS C, 6226.

b, halftone density data IByte/section; 13inary (0-63) section=
Pattern = 8 x 8 bits There are 32 types of functional character codes from 0 to 31, exclusive of Bynary codes 0 to 31, and 3
Alphabets, numbers, and symbols are assigned to 2 to 120, so to prevent confusion with these, density gradations 0 to 120 are assigned.
The data specifying 63 is a value obtained by adding 128 to the value indicating the real value, and when decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

C, bit image data 1 bit I' / pel; Byte unit MSB
-=L (left @pixel) LsD゛---R (rightmost pixel) d, numerical data Binary; Byte unit e unit - data transfer order from MSD to LsD (from L to R: from the leftmost LByte to the right l: transfer 1 yte).

f, control code JIS C-6220, extended control code using a function character code based on 8 unit code and ESC code.

Commands using ESC codes are completed with SP. 5
P=Space.

Note that the above functional character codes are 32 types from 0 to 31, occupying the 0 to 3 characters of the F3ynary code, and alphabetical characters, numbers, and symbols are assigned to Shigamo 32 to 120. In order to prevent confusion between
8 is added to the value, and when decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

(4) Control command The contents of the control command are as follows.

a, Command format % expression % b, Area specification command format ESC + (alphabet) + x1x2 yl y2 +cl c
2 C3c, a +5PXIX2: Horizontal start address (
Absolute address) y1y2: Vertical start address (absolute address) c1c2: Horizontal end address (relative address) c
3c4: Vertical end address (relative address) Relative address is a count value from the start address. Each address
-Two part-time jobs in the evening. Alphabetic characters indicate mode specification or command type.

C, Defold The mote is in text mode, and the starting address is the coordinate origin.

d.Mode specification Text mode ESC+A+x1x2 y'ly y2 +SP When halftone mode and bit image mode are finished, it automatically returns to text mode (default), so mode specification is not necessarily required from text mode to other modes. There is no end address specification in text mode.

Halftone mode ESC+G+n+SP n=0~4: n=o ends halftone mode, n
=1 to 4 designate each of the four groups of gradation types.

Bit image mode ESC+B+x1x2 y1y2 +cIC2C3C4
→-5Pe, write format % formula % n=0 or 1; n=o is memory clear & write.

n = 1 means overwriting (memory data and transfer data O
R). The data is "1" when it is recorded and "0" when it is not recorded.

n=2 is exclusive OR (exe, OR) writing.

f, Erase entire page memory ESC 1 E + SP g, Erase partial page memory ESC + D + x1x2 y + y2 +c1c2 c3
The c4 +SP address is in 81ine units.

h0 Character size specification ESC + S + n + SP n = O ~ 5; n = 0 is the same size (reset), n = I is 1 times the width and 1/2 times the height, n = 2 is 1 times the width and 2 times the height, n = 3
is 2 times the width and 1 time the height, n=4 is 2 times the width and 1/2 times the height, n=
5 indicates double width and double height.

n = O instructs to reset the font size, and reset (
Default) is set to equal size.

i3 character space ESC+ll+n+SP n = O~32, and the space is expressed in units of 1 dora.

j0 line spacing ESC+V+n+SP n is a number with 81ine as one unit. Default is n=o
.

k, print & memory clear ESC+Pn+5P n=o to 99 represents the number of printouts (number of page memory transfers). If n=o, it is assumed that n=1.

1. Print and non-clear ESC+N+n+SP n = 0 to 99, representing the number of printouts (number of page memory transfers). If n=o, it is assumed that n=1.

m, Definition of carriage return (CR) ESC + R + n + SP n = O is CR only, n = I is only line feed LF without CR, n = 2 is both CR and line feed LF.

Definition of n, line feed (LF) ESC + F + n + SP n = O is LF only, n = 1 is CR only, n = 2 is C
Both R and LF.

There are dip switches for setting the definitions of CR, LF, and the above definitions of m, n are commanded.

If not, it follows the definition set by the DIP switch.

0, return CR P, line feed LF With the above configuration and the control program stored in the ROMII, the information storage device 100 has the following characteristics in general.

(]) The memory unit 1 has a memory (page memory) whose number of pixels (number of dots = number of bits) is equal to or more than the number of pixels (number of bits) for processing one page of the plotter 300. (pattern: pixel) and write it in the area specified by the host 200 of memory units 1 to 21;
Converting the data into a halftone pseudo halftone pattern (bit information of the halftone pattern corresponding to the halftone data continues) and writing it into the area specified by the host 200 of the memory unit 21; c) From the host 200 A page memory is created using bits (pixels) in three modes: bit data (pixels) are written directly as bit images into an area designated by the host 200 in the memory unit 21. It is possible to switch between three modes within one page.

(2) Writing to the memory unit 21 is performed by setting the writing start position of each mode to the 0th power of 2 in units of pixels (in the embodiment, n=
3). Preferably n=5.

(3) In the above (2), in the bit image mode (c), the end position designation that defines the end of the specified area is specified by a relative value from the start position in the same address unit as the start position.

(4) In (2) above, if there is no particular designation from the host 200, the write start position is immediately after the device 100 is started (when data is received for the first time after the power is turned on), and the bit information is transferred to the memory unit. 21 coordinate origin, in other cases, the start position specified immediately before is the return position, and if the previous end mode is a bit image of 1), from the return line feed position, and the character of a) In the case of a halftone pattern (pattern or opening), the specified address is the address following the address that ended immediately before.

(5) The host 200 can specify the number of times the memory data for one page of Memories 1 to 21 is output, and whether the data in the memory unit 21 is to be retained or deleted after that number of data outputs can also be specified from the host 200. It is.

(6) Data from host 200 and memory unit 21
It is possible to perform logical operations on the memory data specified by the host 200, and update the result of the operation to the area specified by the host 200. Logical operations include logical sum (OR), exclusive logical sum (Exc, OR) + priority writing of host data, and inverted writing of host data.

These are inversion writing of memory data and memory erasing.

(7) Memory data in the memory unit 21 is transferred to the plotter 300 in synchronization with the speed of the plotter 300.

(8) It has a standard command table for interpreting commands from the host 200 to the device 100, accepts loads from the host 200, rewrites the command table, uses this for command interpretation, and reads the command table from the host 200. allowed for changes.

(9) In (8) above, the format of the command is composed of a functional character code, a character code, and a parameter (numeric code), and the number of each used is variable and not limited.

(10) In (8) and (9) above, the command table is a variable-length matrix, and the lengths of its rows and columns are variable (not limited).

(11) In (8) to (10) above, each command is assigned to each column.5 Each column has a line for the number of characters used in the command, a line indicating the end of the character code, and a line for the parameter size. The number of lines corresponds to the line indicating the command line and the line indicating the processing routine, and the line indicating the end of the character code of each column is set to 0, and the end of the used column string (command string) is the first column. The line (function character code string) is determined as "0".

(12) Same-sized memory, reduced memory, and enlarged memory for character patterns are possible, and character pattern data (bits) can be stored in memory unit 21 in these modes according to character size specification from host l-2 (10). to memory.

(13) In (12) above, the vertical size and horizontal size can be selected separately, and character pattern data (bits) are set in vertical and horizontal sizes according to instructions from the host 200.
is stored in the memory unit 21.

(14) The driver l-matrix structure (bit data distribution) of the original character pattern is an integral multiple (1 or more) of the address unit when specifying the writing position, and the space between characters is an integral multiple (1 or more) of the address unit. (including 0) and can be specified by the host 200.

(15) In (14) above, the dot matrix structure of the character pattern has an integral multiple of twice the address unit in the vertical direction, and the space between character lines is an integral multiple of the address unit (0
) can be arbitrarily specified from the host 200.

(16) There are four types (four groups) of halftone patterns.

Each group has 64 pieces (64 gradations). In (1) above, an area of the memory unit 21 designated by the host 200 is designated with gradation data (density data) from the host 200 from among the halftone pattern groups designated by the host 200. Identify a halftone pattern and write that pattern.

(17) In (16) above, when the host 200 notifies (declares) a halftone prior to the transfer of tone data, the tone data is stored in at least IB1 attribute data (with tone data) at a predetermined position. data indicating that there is)
Interpret Byt, e as gradation data.

(18) In (17) above, IByte gradation data has the following.

Contains attribute data (data indicating groups) for a plurality of Bj and t specifying gradation groups.

(19) In (16) above, the host 200 writes the gradation storage write area (closed area: start end address and end address)
Transfer the specified data. When specifying a writing area in this way, the host 200 also transfers attribute data specifying a tone group.

(20) The host 200 can define the functional character codes CR (plotter return) and LF (plotter line feed) using commands.

(21) If there is no definition of CR or LF from the host 200 (default), the definitions according to the state of the designated switch that defines these definitions are followed.

(22) Equipped with a DMA controller 43,
Image data (pixels) are transferred from the memory unit 21 to the plotter 300 by a DMA controller 43 to an 8-bit buffer, converted to serial data synchronized with the recording operation of the plotter 300, and then transferred to the plotter 300. Output.

(23) The DMA controller 43 can also be applied to data input/output with the host 200, and data transfer with the host 200 can be performed in two modes: a CPU mode in which data is first taken into the accumulator of the CPU 13 and then sent out; Transfer is possible in DMA mode in which the roller 43 transfers.

Table 1 below shows the contents of the standard command table.

A comparison between each of columns 1-16 in Table 1 and the contents of the command is shown in Table 2 below.

Table 2 **Memory data inversion specifies that the data in the page memory is inverted and updated. The command is ESC+I+n+SP"C', n = 04;
i: positive (no memory inversion) instruction, n = 1
instructs to rewrite the inversion (negative image).

*** Rewriting the command table instructs to add and change the contents of the table shown in Table 1.

The command is ESC+X+zIZ7 Z3 z4 Z
5 z6 +SP, Zl is data indicating a numerical value specifying column M, Z2 to Z6 are rows N = 1 to 4, respectively
This is information data to be written to.

Next, the operation based on the control program stored in the CPU 13 (7) and the ROM 11 will be explained.

First, reference is made to FIG. 7 which shows an overview. When the power is turned on, the CPU 13 goes through initialization, declares variables, and becomes a blank.
Define the chin and proceed to the main program. In the variable section, define all variables used in the control program. In subroutine definitions, subroutines that are called from the main program and other subroutines are defined. Each processing part that makes up the program is made into subroutines as much as possible, and data processing is actually carried out by calling these subroutines. The main subroutines are (a) to (ma) shown in FIG. Subroutines include elemental subroutines that perform only one process, and compound subroutines that call these subroutines and perform a set of processes.

The main program calls element subroutines or composite subroutines in the order of processing steps and repeats them so that a series of data processing is executed.

In the initial setting of the main program, a subroutine (force) is called to set a read/write area (i'1! coordinate origin immediately after the power is turned on) in the write area setting table. Next, subroutine (d) is called to write standard commands as shown in Table 1 into the command table.

Furthermore, subroutine (a) is called to set an initial value (default 1-). Then, subroutine 5 (a) is called to erase the entire page memory (31). Then, wait for the arrival of a command.

When a command arrives, data processing begins. In data processing, first a subroutine (nu) is called to interpret an instruction (command), and then a subroutine (to) is called to process and set parameters in the command. Next, a subroutine (N) is called to select the processing operation specified by the command. When a processing operation is selected, processing such as memory reading and writing is performed according to a subroutine that executes the processing operation. When the processing is completed, the process returns to the command waiting state before data processing.

Next, each of the subroutines will be explained with reference to FIGS. 8 to 39.

(A) Initial settings (Figure 8) Start address input registers 5AX (x coordinate) and SA
Clear Y (y location if!A) and start address storage registers XADR (x coordinate) and '/ADH (y coordinate)
Clear the virtual bitmap space coordinate register x, ■
Clear. Next, write 3 bytes (24 dots) for the width (λ) of one area (section) of the character pattern and halftone pattern.
, set the height to 6 bytes (48 dots = 48 lines), the space between characters to 1 byte (8 dots), the space between lines to 0, and convert the lowercase English character code to uppercase English character code (using the command is composed of uppercase letters, so this conversion is performed for the purpose of reading even if the input is in lowercase letters.) Set the flag SW to OFF (no conversion), and set the pattern table (character character memory &
density gradation pattern memory) can be referenced in text mode (
character specification) and set the return operation CR to r+
Set only the return CR equivalent to = 0, and change the action LF to n =
Set only the line feed LF equivalent to 0, and set the font size to n ==
Set it to the same size as O, set it without overwriting (OR writing), set it to 1 ~ without reverse rewriting, and set the number of pudding 1 (
The number of times page memory data is transferred to the printer 300 is set to 1 (this is the default setting). The writing area is
Cents outside the actual writing area (that is, no writing).

(B) Erase the entire memory (Figure 9) Set simultaneous writing to all areas, write 0 (non-recorded data) to the write area start address (in bytes), and sequentially transfer the spoons to the next address. .

After performing this transfer 65535 times (the number of bytes for 1329 minutes), erasure of the entire memory is completed. That is, data in all 16 banks are erased simultaneously.

(1) DMA output (Figure 10) When the plotter 300 is ready, clears the subpage counter (register), sets the read line to 1, resets the hardware between the device 100 and the printer 300, Set read bank to 7, set DMA enable to specify DMA operation mode for ports and interfaces, set address to 0, set transfer byte counter to 304, disable interrupts and set subpage to 0. DMA transfer to the plotter 300 is started. When the content of the transfer byte counter becomes 0, the address is set to 0 again, 304 is set to the transfer byte counter again, and DMA is activated.

Thereafter, each time the number of transferred bytes reaches 304 (each time the contents of the transferred byte counter becomes 0), the read line is moved to the next line, and when reading of one bank is completed, reading of the next bank is started. When reading of a page is finished, reading proceeds to the next subpage.

When the number of read lines reaches 3296, DMA is prohibited,
Enable interrupts and end this subroutine.

(1) Print (Figure 11) When the plotter 300 is ready, the above-mentioned (1) DMA
Execute the output and when it is finished, the number of print settings will be 1
If the residual value is 0 after subtracting the month, if memory deletion after printing is set, (a) execute the entire memory deletion subroutine, (a) execute the initial setting subroutine, and then return to the main routine. Return. If memory erasure after printing is not set, proceed to the (a) initial value setting subroutine without executing the entire memory erasure. This print subroutine can be repeated until the number of remaining prints becomes 0.

(E) Writing area/A1 address setting (Figure 12) If the current writing line is 3296 (this does not exist in the effective address), writing for the entire page has been completed. Therefore, the value obtained by subtracting 3296 from the number of writing lines (
0) (this returns to the beginning of writing). If the write line is 3295 or less, continuous writing is possible, so check whether it is necessary to switch banks or subpages, and if necessary, switch banks or subpages. When switching is not necessary, the number of 304 bytes for one line is added to the write absolute address to advance the write position to the next line. Then, the contents of the write line counter (register) are incremented by 1 and this subflow is ended.

(Power) Writing area setting table (bank and subpage settings) (Figure 13) The bank number and subpage number assigned to the line number, with the line number (line counter contents) as an argument.
There is a table in which the bank number and subpage number are determined by referring to this table, and the bank and subpage to be allocated as the write area are set. FIG. 13 shows the bank and subpage allocation obtained by referring to the table.

(g) Half-width characters (standard) (Figure 14) Character pattern memory (Character memory is 3 bytes horizontally and 48 lines vertically, all of these bits are 24 x 4
It is stored in the character memory in the form of 8's arranged in a row. This data is stored in a single line in the same half-width character buffer.

First, the line number counter C is cleared, and the next absolute address Y is calculated, and the value obtained by subtracting 304 (bytes, 304 is the number of bytes for one line) from the absolute address YV is set as the absolute address. This subtraction is an element subroutine of this subroutine, in which 304 is added to the absolute address to advance the write area by one line in the third step of (e) write area/address setting, so this is to be corrected accordingly. It is. 3 in other subroutines described below.
Subtraction of 04 has the same meaning.

When the absolute address Y■ is set as described above, the process proceeds to (e) write area/address setting, and after exiting therefrom, the data of the half-width character buffer is memorized in the set bank.

In this memory operation, the half-width character buffer contains the 3 bytes (24 dots) of the first horizontal column (line O) of the character pattern as the 3 bytes of the first block, and the second
The 3 bytes of the column (first line) are stored as the 3 bytes of the second block, and finally the 3 bytes of the 48th column (47th line) are stored as the final 48th program, so the write The number of lines C multiplied by 3 [(0,
3, 6, 9, . . . ), each consecutive 3 bytes 1- are stored in the set bank. That is, the pattern data bits arranged in one column are converted into 3 horizontal bytes x 48 vertical lines and written into the page memory.

(ri) Half-width, half-length characters (Figure 15) In this case, from a character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column, the number of writing lines C multiplied by 6 [(0, 6 ,12,18,...)
Read every 3 bytes from then on and store it in memory in the set bank. That is, the data with the data of even numbered lines of characters discarded is converted into 3 horizontal bytes x 24 vertical lines and written into the page memory.

(i) Half-width double-length characters (Fig. 16) In this case, a repeat writing counter CC is used. Set by reading every 3 bytes after the position (0, 3, 6, 9,...) where the number of writing lines C is multiplied by 3 from a character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column. Then, the write line is changed and the same 3 bytes are written to the next line.

That is, when the first write is completed, the counter CC is incremented by 1, the same 3 bytes are written to the write line again, the counter CC is further incremented, and the count value becomes 2, and then the counter CC is cleared. be done.

That is, data written twice over two lines of data for each line of characters is converted into 3 bytes horizontally by 96 lines vertically and written into the page memory.

(J) Full-width characters (Figure 17) In this case, each bit of each character line is written twice in succession into a double-width character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column. A full-width character buffer stores a string of bit information in which the same bit information is stored in two consecutive bits.However, the full-width character buffer has twice the focus information as the number of bits of one character pattern.Full-width characters From the buffer, read every 6 bytes starting from the write line number C multiplied by 6 [(0,6°12.18...) and store it in the set bank.In other words, 6 consecutive bytes (information is The contents of one line) are written into the page memory as one line.Therefore, one column of data is converted into 6 bytes (48 dots) x 48 lines (vertical) and written into the page memory.

(S) Full-width half-length characters (Figure 18) In this case, as well, each bit of each character line is stored in the full-width character buffer in the (C) full-width character preprocessing that precedes this routine in the same way as for the (C) full-width characters described above. is written twice, and a string of bit information in which two consecutive bits of the same bit information are stored is stored in the full-width character buffer. However, since reading from the buffer is performed every 6 consecutive bytes starting from the 12th position of the number of lines, the data on even-numbered lines is discarded and written to the page memory, so it is stored in half-length. .

(C) Full-width double-length character (Figure 19) In this case, as well, in the (C) double-width character preprocessing that precedes this routine, each bit of each character line is stored in the double-width character buffer in the same way as for the (C) double-width character described above. is written twice, and a row of bit information in which the same bit information is stored in two consecutive positions is stored in the full-width character buffer. In addition, as in the case of half-width double-length characters in (ke), the double-write counter Cc is used and the same line data (full-width) is written on two consecutive lines, so the page memory has 6 bytes horizontally. ×
Character data is stored in vertical 9G lines.

(S) Halftone pattern (Figure 20) There are four types (groups) of halftones, and 64 gradations are assigned to each group, and each gradation is 1 byte horizontally (8 bits) x 8 lines vertically (8 (bit)=represented by an 8-byte pattern.

In FIG. 20, patterns 1 to 4 indicate types (groups) of halftones. The halftone data indicates the type of halftone and the density gradation. The data indicating the type of halftone is saved as is.

First, to explain from the beginning of the flow, 1 from the halftone data.
Subtract 28. As explained earlier, the command function character code, alphabetic characters, and symbols with numbers 0 to 120 are based on the JIS C-6220, 8-unit code standard (
ASCII code), and in this embodiment, numbers are assigned to functional character codes, alphabetic characters, and symbols according to this standard. Therefore.

If the gradations from 0 to 63 are expressed directly in binary, confusion may occur in identification, so the host 200 and the device 11 use the gradation numbers 0 to 63 plus 128 as gradation data.
I am planning to give it to 100. Therefore, 128 is subtracted from the gradation data in the sub-p- of this halftone pattern to reproduce data representing the gradations 0 to 63 themselves. Next, since one minimum pattern is 8 bytes, the data representing the gradation is multiplied by 8 and stored in the gradation pattern read address register F.

Next, specify the read pattern group using the saved halftone type data, and 8 bytes from the Fth of the group (
64 bits of 1M small pattern) are read in sequence and transferred to the half-width character buffer, the start address YADR (hide) is multiplied by 8 and stored in line register Y, the start address XADR is stored in X register X, Clear write line register C.

Absolute address'/Y=30/IX (Y MOD 208
)+X is calculated. In other words, since the X and Y addresses are consecutive in memory, divide Y by 208, take the remainder, multiply it by 304, add X, and get the absolute address vY.
seek. Next, the value obtained by subtracting 304 from YY is set as YY. Next, it is checked whether or not reverse writing is set, and if it is not set, the process proceeds to normal writing shown in FIG. 21, and if it is set, the process proceeds to reverse writing shown in FIG. 22.

To explain normal writing with reference to FIG. 21, first, execute the above-mentioned (e) write area/address setting to set the write area of the page memory, and then write to the set area. Each byte of the half-width character buffer is written in association with the line number. Each time one byte is written to one line, the line number counter C is incremented by one, and when the count value reaches eight, the writing ends. As a result,■! & This means that a small pattern of 1 byte horizontally and 8 lines vertically was written.

Inversion writing will be explained with reference to FIG. 22. The inverted write is the same procedure as the normal write described above, but the difference is that each bit of each byte is written to the page memory with rlJ set to 10 and 0 set to 1. .

(C) Full-width character preprocessing For (C) Full-width characters, (S) Full-width half-length characters, and (C) Full-width double-length characters, one bit of the character pattern (character) data is horizontally transferred to the full-width character buffer. It is necessary to store two consecutive bits. This storage is performed by this full-width character preprocessing.

In this case, first clear the character read line number counter C, clear the full-width character buffer, and then read the character data (3 bytes of each line are sequentially arranged in one horizontal column; total of 3 x 48 bytes). For every 3 bytes, each bit is written as 2 consecutive bits to the full-width character buffer, and when this is finished, the counter C is incremented by 1,
Next, the next 3 bytes of character data are similarly converted to 6 bytes and stored in the full-width character register. Then, the counter C is incremented by one. The same applies below.

When the contents of counter C reach 144, all the processing of character data for one character has been completed, so when specifying a single character and specifying a full-width character, the above-mentioned subroutine for full-width characters is called. When specified (su)
Proceeds to the subroutine for full-width half-length characters, or (b) if full-width double-length characters are specified, then proceeds to the subroutine for full-width double-length characters.

(n) Pattern processing (Figures 24a and 24b) Patterns (fonts) include character patterns and halftone patterns. The character code follows the ASCII code of JIS C-6220, and according to this regulation, functional character codes are assigned to 0 to 3I, symbols, numbers, and alphabetic characters are assigned to 32 to 120, and 121 to 151 are undefined.

Katakana characters are assigned to 152 to 210, and 211
~230 is undefined. Therefore, symbols, numbers, alphabetic characters, and katakana are assigned codes sequentially starting from 0, but in order to prevent confusion with these functional character codes, undefined codes, etc., when communicating with the host, - symbols, numbers, and alphabetic characters are assigned codes. is a code that adds 32, and in katakana it is 6
The code is 4 multiplied by 11.

Therefore, in the case of characters, when the code is 0 to 31 (data <
2011), 1.21-151 (7F11<Data AO
I+) and 121 to 151 (OFI+<data), this subroutine is terminated as an error. If the data is in the character allocation range, when data < 8011 (symbols, numbers, and letters), the data is 32
Subtract and reproduce it as character data, data) 9
When it is FI+ (katakana), 64 is subtracted from the data and it is reproduced as character data. As a result, the reproduced character data returns to character data in which numbers, symbols, alphabetic characters, and katakana are assigned in continuous codes.

Next, the character code is multiplied by 144 and this is set as the read address F of the character pattern memory (character memory). This is to specify the start address of the character data since 144 bytes are allocated to one character. Next, character data is read from the pattern memory, the start address YADR (byte) is multiplied by 8, and stored in line register Y, and star 1 - address
ADR is stored in the X register
Advance R to the next step.

In the case of halftone mode, its density gradation data is the sum of 128 as already explained, and 128
If ≦data≦191, the above-mentioned halftone pattern subroutine is executed, the start address is updated, and this subroutine is ended. If the data is outside the range, this subroutine is terminated and the halftone pattern subroutine is not executed.

(i) CR (return) operation setting (Fig. 25) This subroutine performs (a) initial value setting (default), (n) instruction decoding, which will be described later, or CR specification data stored in register CR by dip switch reading. Update the page memory read/write address based on the page memory. 0 in the CR specification data instructs to execute only CR, so in that case,
Set the axis start address to the first start address.

CR specification data 1 instructs to execute only LF, so
In that case, the Y-axis start address is changed to the character size and the number of lines corresponding to the interline space V is added to the current value and updated to the actual value. CR specification data 2 specifies both CR and LF, so in that case, set the X-axis start address to the first start address - ■ Axis start address Set the number of lines equivalent to the character size L and line spacing V. Update to the value added to the current value.

(H) LF (line feed) M9 fixed (Figure 26) This subroutine performs (a) initial value setting (default), (described later).
n) Update the read/write address of the page memory based on the LF designation data stored in the register LF by decoding the command or reading the DIP switch. LF specified data 0
Instructs to execute only LF, so in that case, set the Y-axis start address to the first start address. LF
Since l in the specified data instructs to execute only CR, in that case, the X-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. LF specification data 2 specifies both CR and LF, so in that case, set the X-axis star 1-address to the first start address, and set the Y-axis start address to the line equivalent to character size L and line spacing V. Update the number to the current value plus the value.

(T) Centronics input (FIG. 28) When the interrupt prohibition is released, a ready (receivable) signal is output to the host 200. When data is received from the host 1-200, the data is taken in from the Centronics interface 41, the host 200 is set to busy (receivable), and external interruptions are prohibited.

(TE) Bit image processing (Figures 27a and 27b)
Figure) One unit of address is 8 lines (1 byte), so in order to convert this to an address in line numbers, multiply the Y-axis start address by 8 and set the Y-axis in-address V to cell 1 - Set the start address for the B and X axes as is. Then, the horizontal width (■) and vertical width (J) of the area designated by the received data are set as target values. Next, clear the line number counter CC, calculate the absolute address Y■, subtract 304 from it, and set the value as the absolute address vY.Next, clear the width counter C and check whether it is inverted writing or not. (2) Execute centronics input and store the received data (bit data) in the 1-minute width bit buffer.When inverted writing is specified,
At this time, the data focus "1" and "0" are inverted and stored. When one line of bit data corresponding to the width is stored in the focus buffer, (e) Execute the write area/address setting, check whether writing after clearing is possible, and if it is writing after clearing, set the bank. Write bit data for one line width of the bit buffer to , and set the line number counter CC to 1.
It counts up, clears the horizontal counter C, receives one horizontal line, writes to the pit buffer, sets a write area address, and writes to a predetermined bank of the page memory. When the contents of the line number counter CC reach J+1, writing of vertical J lines has been completed, so this subroutine is ended. If write after clear is not specified, after setting the write area address, transfer the width (C+
1 byte), clears the bit data counter 13C, and when overwriting is specified, performs a focus by ORing each bit of the pit buffer and each bit of the memory buffer in order. Update memory is stored in the buffer, the bit data counter is incremented by 1 for every 1 bit of updated memory, and when the contents of the bit counter BC exceed the contents of the width counter C, that is, when the logical sum of the width of one line is performed.

The contents of the pit buffer are written to the setting bank of the page memory, and the line number counter CC is incremented by one.

When exclusive OR is specified, perform the exclusive OR of the bit data in the page memory and the bit data in the pit buffer in the same way as the procedure for logical OR, and update the memory in the pit buffer. then write it to page memory.

(G) Conversion of lowercase and uppercase letters (Fig. 29) Referring to the command table shown in Table 1, commands are composed of uppercase letters and numbers. Therefore, this conversion subroutine is provided so that commands can be interpreted even if they are in lowercase letters.

First, an uppercase English letter is 96〈data〈123, so anything outside of this is a lowercase English letter. Since lowercase English letters have a code 32 greater than uppercase English letters, the code representing the value obtained by subtracting 32 from the input code is corrected to the character code. When the conversion is completed, the flag SW is set to OFF, indicating that conversion is unnecessary.

Partial erasure (FIGS. 30a and 30b) Partial erasure is equivalent to storing rQJ in a given area in the same manner as the above-mentioned bit image processing. Since it is sufficient to store rQJ in the entire specified area, partial erasure is performed by writing "0" to the leading bit of each line in the specified area and transferring this along the line.

(d) Command table writing (command table tabulation) (31st
Figure) RAM command table write area address CY = 0~
50 (column M in Table 1) is cleared.

This is the content from the first step to the seventh step. Next, data is written in each column A and row N and the intersection of their matrix as shown in Table 1.

(J) Instruction decoding (Fig. 32) Clear the row N register Cx and column A register CY, and receive command data from the above-mentioned Centronics input. If it is a command, the beginning of the data must be ESC.
Otherwise, it is data indicating 0 or a number of 32 or more. Therefore, if the data is not 0 and is not 32 or more, the lowercase/uppercase conversion flag 5I11 is referred to, and if it is on, conversion is necessary, so the above-mentioned (g) lowercase/uppercase conversion is executed.

If it is off, the conversion has finished, so refer to the data as is and compare the contents of the input data with the data at the matrix intersection specified by the contents of the row N register Cx and column A register Cv (Table 1). Then, the contents of registers Cx and CY are counted up until data matching the input data is read out.

That is, first, the function character code of the input data is entered in columns 0 to 50 (row N=0 of the command table (Table 1)).
It is possible to write up to M = 50, and in the example in Table 1, up to A = 16 is written, while A = 17 to 50 are empty: "0" is written in all. ) and the data of 1.2.3-... from 820 sequentially, and if they match, fix the gate and increase the row N by 1 one by one and set A and N.
The data at the 71-Riks intersection specified in is compared with the data below the functional character code of the input data.

If the data of row N=3 is read and compared and is not the same, the data is incremented by 1 and a similar data comparison is made.

When the data in row N = 0 to 3 and the input data match exactly, the value in column A at that time is the input command No., and the data in row Itl = 4 in column N is specified by the command. Indicates a subroutine. Since the default is text mode, when the function character code part of the command is rQJ, the processing instruction register oP is set to (n).
0 indicating pattern processing (phono 1 to processing) is stored in memory. In other cases, data in row N=4 of the column having data matching the input command data is stored in the instruction register OP.

(v) Processing operation selection (FIG. 33) In this subroutine, a subroutine is set according to the contents of the processing instruction register oP. The content of 0 in the processing instruction register OP indicates pattern processing (font processing) as described above.
Therefore, in this case, (iv) pattern processing is set. When Or'=2, (TE) bit image processing is performed as 0P.
= 4 performs (S) partial deletion, 0P = 5 (A) complete memory deletion, Or' = 14 (1) pudding 1-, O
Even with I'=16, (1) print, OP=27 (evening) CR operation setting, and OP=28 (chi) LF
Set the operation settings, and (e) instruction rewriting at 0P=24.

()) Parameter calculation (1) (Fig. 34) When there are four parameters in the command: XI, X2, yI, Y2, these indicate the start address. Xl is X
Upper 8 bytes of address + X2 is lower 8 bytes + i is X
Upper 8 bytes of address.

Since y2 is the lower 8 bytes, 256Xx1+X2 is set to star 1 - address register SAX2, 256Xy+
+y2 is stored in the star 1-are 1-less register SAY.

(c) Parameter total 1 (2) (Figure 35) Command parameters are XI X2 y1y2rCI C2C3
In the case of 8 C4s, set 256 X x H→-x2 to the start address register SAX, 256Xly,
+y2 is stored in the start address register SAY, and C
Since 1 to c4 indicate the end position (relative address) from the start address, 256Xc1+c2 is set to X address/byte counter XAD+j:, 256Xc3
+c4 is stored in the y address byte counter YADC,
Set the xADC to the target byte register and the contents of the YADC (
Byte) multiplied by 8 and further added 7 and the value is stored in the target line number register J. In addition, adding 7 is.

This is because when YADC is O, it indicates the area from O to 7 in line number, so it is set to 7 at the end.

(H) Parameter settings (1) Star 1 to address parameters (Figure 36a) Execute the parameter calculations in () above and store the calculated address in the X address register (current position register) XADR.
and stored in the X address register. Both are data in bytes.

(2) Bit image parameters (Figure 36b) Execute the above-mentioned (c) parameter calculation (2). The X direction is in byte units, and the X direction is in line units.

(3) Partial erasure parameter (Figure 36c) (c) mentioned above
Execute parameter calculation (2). The X direction is in byte units, and the X direction is in line units.

(4) LF operation parameters (Figure 36e) Register LF
Stores the value of parameter n in the F action designation command.

(5) Halftone mode parameter (Fig. 36d) The value of parameter n in the halftone mode command is stored in the pattern table selection register PT.

When n=0 (end of halftone mode: return to default, same as specifying text mode), set the horizontal V of the font size to 3
Byte (half-width), 6 bytes of fir (48 lines: full-width)
, set the character spacing H to 1 byte and the line spacing V to 0 (default). When N=O (halftone instruction), the horizontal ν of the pattern size is set to 1 byte, the vertical is set to 1 byte (8 lines), and both the horizontal H and vertical V of the inter-pattern space are set to 0.

(6) Character spacing parameter (Figure 36f) Store the value of parameter n of the character spacing designation command in the character spacing parameter register H.

(7) Reverse write parameter (Figure 36g) Write the value of parameter n of the inverse designation command for memory data to the reverse write instruction register RE.

(8) Number of prints when memory is retained after printing (Fig. 36h) The value of the parameter n of the print non-clear command is stored in the print number register CN.

(9) Number of prints when erasing memory after printing (Figure 36i) The value of parameter n of the print & clear command is stored in the print number register CN.

(10) CR operation parameters (Figure 36j) Register C
The value of parameter n in the CR operation designation command is stored in R.

(11) Character size selection parameter (Figure 36) Store the value of parameter n of the character size specification command in the character size register S, and when the stored value (n) is 0, the width is 3 bytes (half-width ), set the length to 6 bytes (48 lines). When it is 1, W is 3 bytes and L is 3 bytes.
When the part time is 2, the axle is 3;<it.

Set L to 12 bytes, set 3 to 6 bytes], set L to 6 bytes, set 4 to 6 bytes, set L to 3 bytes, set 5 to 3 bytes, set L to 12 bytes. do.

(12) Line spacing parameter (Figure 361) Set the value of the parameter n of the line spacing command to the line spacing register V
Store it in.

(13) Overwrite parameter (Figure 36m) Write the value of parameter n of the write specification command to the write specification register RO
Store in.

(14) Instruction rewrite parameter (Figure 36r+) Row N
Clear the counter C and write to the first 0 of the rewrite register EX.
Column data at the position, and row N=0゜1.3.4
Corresponding places [1, 2, 3 and 4, sequentially with N of the command
=O, N=1. , N=3, and N=4 data (] (parameter) are stored.

()) Parameter setting selection (Fig. 37) Similar to the above-mentioned (v) processing operation selection, the content of the processing instruction register OP is referred to in (j) instruction decoding, and the above-mentioned ((v)) is selected according to the contents of OP.
h) Execute the subroutine for parameter setting (Figures 36a to 36n).

(v) Parameter processing (Figure 38) Refer to the data stored in the processing instruction register OPI in the above-mentioned (v) instruction decoding, and if it is 0, it is text 1-mode, so it is also 27 or 28. and CR (return)
or F (line feed), this routine ends. In other cases, the counter C is cleared, the parameters are read one by one using the Centronics input, the counter is amplified by one count, and the number of readings is the number specified in advance by the number of parameters P in row N = 3 of the command. become,
If the Centronics input data indicates 32 (0 indicates the end, but since the function character code is 0 to 32, 0+32 indicates the end 0), it is the end of the command. , ()) Executes parameter setting selection and ends this subroutine.

(E) Instruction rewriting In the above-mentioned (14) instruction rewriting parameters, change data (parameters) in the command to the rewriting register EX, Kara A, row N=0 data, N-1 data, N=3
data and N=4 data are stored, so set the 1st 0 data of EX, ie column data, in the command table column address register CI/,
Row N of the specified column in the command table = 0. N=],
N=3 and N=4 d, respectively EX(7) second
Write data No. 1 to No. 4 No. 3.

2. FIG. 40 shows the output timing of page memory data in the device 100. When outputting to the plotter 300, the gate signal LGA from the plotter 300
Data WDAT^ is provided to the plotter 300 line by line in synchronization with TE.

By executing each of the above subroutines, the start address immediately after the power is turned on will be as shown in Table 3 below, and the subsequent start address will be as shown in Table 4 below. The rest is as shown in Table 5 below.

Processing text after Table 5 Secondary address Halftone: Next address Bit-r image: Waiting for designation. If not specified, it will remain stopped.

Post-processing text Secondary address Halftone: Next address Bit image: Waiting for designation. If not specified, it will remain stopped.

Post processing Text)-: CR Orori, position after FfJJ.

Halftone mode Pino I-Image: Wait for cR or LF and subsequent designation. If not specified, it will remain stopped.

Note that the address data given from the host 200 to the device 100 is in units of bye 1. In text mode and halftone mode, the write start address is set in ()) parameter calculation (1), and in pip 1 - image mode ( C)
A write start address and a write end address are set in parameter calculation (2). These addresses are in bytes.

As explained above, immediately after turning on the power, the initial setting [(power) i! F-input area setting table 2 (d) Command table writing and (b) Entire memory erase] are executed, and the command input is awaited. When an external interrupt occurs, (v) executes instruction decoding, (f) executes parameter processing, (v) executes processing operation selection, and executes the selected process.

Next, several types of processing operations in response to commands will be described.

(1) Rewriting the command table When a command to rewrite the command table arrives from the host 1-200, the command is decoded and the parameter register is
Set the number of parameters to 5 and open the processing operation register OP.
is set to 24, and then in (to) parameter processing, five parameters are transferred from the host 200 through Centronics input. Then, proceed to ()) parameter setting selection, and since Or' = 24, execute (14) instruction rewrite parameters (Figure 36n), store 5 parameters in conversion register EX, and then (n) process. Proceed to operation selection,
Since 0P=24, proceed to (e) rewriting the instruction.
This subroutine rewrites the contents of the column specified by the first parameter in the command table (Table 1). Note that if a column that already includes 1 is specified, i
When it is L, it literally means rewriting, but when a empty column ZS (column in which 0 is written in row N=1) is specified, 1 new command is written.

In this way, command rewriting (and writing) is performed on the host l-2.
Since this can be done with a command table rewrite command of 00, the hosts 1 to 200 can change the commands (standard commands) set in the control programmer 11 and add new commands to the device 100. That is, it is possible to change command definitions and create new commands.

(2) Text 1-mode processing start address specification command is sent from the host 200 to the device 10.
If set to 0, this specifies only the starting address and is in text mode. In the halftone mode and the p1-image mode, the end address is also specified as well as rjl-l'').

Upon receiving the start addressing command, the device 100 (
N) In command decoding, set the number of parameters 4 to parameter register P, set 1 to 7 in processing operation register OP, then (to) Parameter processing, set 4 parameters from host 1 to 200 with Centronics input. Receive a transfer. Then, proceed to ()) parameter setting selection, and since 0P=1, proceed to (1) star 1-address parameter (Figure 36a), ()) execute parameter division (1) fj, and start the start address. Set the address registers XADR and YADR to complete the setting of the text mode start address.

After that, when the host 200 sends the character code, (
Step) Set OP; 0 by decoding the instruction, and since 0P = 0, pass through the parameter processing as is, and then (step)
Select the processing operation to proceed to pattern (font) processing, convert the character code, read the character pattern data from the pattern memory <Af character memory), store it in the character buffer memory, and convert it according to the set character size ( Proceed to g) half-width characters, (ri) half-width half-length characters, (k) half-width double-length characters, or (c) full-width characters preprocessing.

When proceeding to one of the first three methods, address deletion is performed, and then (e) writing area/address setting is executed, and the character pattern data is subjected to specified character size processing and written to the page memory. . (C) When proceeding to full-width character preprocessing, create character pattern data in the double-width character buffer by enlarging the character pattern data in the character buffer memory from 1 bit horizontally to 2 bits horizontally, and (C) Proceed to full-width character 2 (ri) full-width half-length character or (shi) full-width double-length character, calculate the address there, and then (e) execute write area address setting to set the specified character size to the character pattern data. Perform processing and write to page memory.

Note that the default 1- is in text mode, so when the character code is sent from the host h200 from the beginning after the power is turned on, 0P-0 is set by (nu) command decoding.
Since op=o, it passes through parameter processing as it is, then proceeds to (n) pattern (phono 1-) processing by selecting (n) processing operation, converts the character code, and stores the pattern memory (character memory). ) reads character pattern data and stores it in the character buffer memory, and converts it to (ki) half-width characters according to the set character size.

Proceed to (ri) half-width half-length character, <v) half-width double-length character, or (c) full-width character preprocessing. The operation is the same as when receiving the character code data described above.

(3) Halftone mode Halftone mode specification command is sent from the host h200 to the device 10.
0, the device 100: (nu) sets the number of parameters in the parameter register P in the instruction decoding to 1, sets the processing operation register OP to 7, and then (g) in the parameter processing sets the number of parameters to 1. is transferred from the host h200 via Centronics input. Then, proceed to ()) parameter setting selection, and since 0P=7, proceed to (5) halftone mode parameter (36d), where depending on the value of parameter n, if N=O, this indicates the end of halftone. Instructs the writing format to be the default text mode (standard)
Set to . N=4~4 specifies the type of gradation, so
At this time, a write format is set in which continuous bits are written. Next, (v) processing operation selection is 0P=7, so it passes through as is.

After that, when the host 200 sends the halftone code,
(J) Pass op=o to cellar 1 by decoding the instruction, and since op=o, (J) Pass through the parameter processing as is, and then (
(v) Processing operation selection proceeds to (n) pattern (phono 1-) processing, and then proceeds to (b) halftone pattern to write in the page memory. Since the pattern area is predetermined in the text mode and the halftone mode, the subroutines are shared in this way.

(4) P1-Image mode When the focus image mode designation command arrives, the device 100 sets P=8, 0P=2 by (j) command decoding, and then sets eight parameters by (j) parameter setting. is received from the host 1 to 200, and the ()) parameter setting selection is 0.
Since P=2, proceed to (2) Pi-image mode parameters (Figure 36b) and (c) parameter calculation (2).
) and proceed to (te) bit image processing by selecting (ne) processing operation, where the bit data is received by the sen]ronics input and written to the page memory.

(5) PRINTLENONCLEAR OR PRINT1-&CLEAR When these commands arrive, the device 100 decodes the command and determines P=1. OP = Set IO or 11 to h shi, (to) parameter processing and set parameter (n) to host 2
From 00 to Sen 1 to Receive 5 with Ronix input, go directly through ()) parameter setting selection, proceed to (1) print with (ne) processing operation selection, and execute the number of printouts indicated by parameter n. , non-clear holds or clears the page memory in response to clearing.

(6) Logical operations Logical operations include (S) inversion writing in the halftone pattern subroutine in halftone mode, and inversion writing 2 overwriting (OR) in (te) bit image processing in bit image processing. ) or exclusive OR writing is selectively performed as specified in advance by the parameters of the command.

When other commands arrive, data processing [(v) command decoding - (v) parameter processing - (v) processing operation selection] is similarly executed to execute a predetermined subroutine.

In the above embodiment, only the write start address is specified with the halftone mode command, but similarly to the bit image mode command, four parameters indicating the end address are added. Similarly to the bit image mode, the end address may be set together with the start address.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1.
FIG. 2 is a block diagram showing the configuration of. FIG. 4 is a block diagram showing the configuration of patterns RO to ■ shown in FIG. 1, and FIG. 5 is a block diagram showing the configuration of the interface port 40 shown in FIG. 1. FIG. 6 is an explanatory diagram showing memory divisions of the page memory 20. FIG. 7 is a flowchart showing an overview of the operation of the device 100;
FIGS. 8, 9, 10, and 11. FIGS. 12, 13, 14, and 15. FIGS. 16, 17, 18, and 19. FIGS. 20, 21, 22, and 23. Figures 24a, 24b, 25, and 26. Figures 27a, 27b, 28, and 29. Figures 30a, 30b, 31, and 32. Figures 33, 34, 35, and 36a. Figures 36b, 36c, and 36d. Figures 36e, 36f, and 36g. Figures 36h, 36i, and 36j. Figure 36, Figure 361, Figure 36m. 36n, 37, 38, and 39 are flowcharts showing the operation flow of the subroutine, respectively. FIG. 40 is a time chart showing the data transfer timing when data is transferred from the device OO to the plotter 300. 100: Information storage device II: ROM12: RA
M13: CPU31: Pattern Memory Patent Applicant Ricoh Common Bus Co., Ltd. Figure 6 Figure 4 Bar/No Figure 11 Figure 12 Procedural Amendment (Master) May 26, 1980 Commissioner of the Japan Patent Office Kazuo Wakasugi 1, Case Indication of 1982 Patent Application No. 042583 2
, Title of the invention Information 1fFJ storage device 3, Relationship with the person making the amendment Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo Name
(674) Ricoh Co., Ltd. Representative Hama 1
) Hiro 4, Agent 103 Phone: 03-8671-6
052 Address 2-27-6 Higashi Nihonbashi, Chuo-ku, Tokyo
No. 5, subject of amendment 6, the two lines of the following page of the description of the contents of the amendment are corrected. that's all

Claims (10)

[Claims] (1) Page memory in which 1 bit corresponds to each pixel of one page; Pattern memory 7 output interface that stores character pattern data; Instructions to decode external commands and set processing operations and parameters Decoding means; Converting the input character code into character pattern data represented by the code, expanding or compressing the character pattern data at a horizontal magnification and vertical magnification corresponding to the character size parameter set by the instruction decoding means, and writing the character. An information storage device comprising: text mode writing means for creating embedded pattern data and writing it into a predetermined area of a page memory; and page memory output means for outputting data in the page memory a predetermined number of times. (2) The horizontal magnification is half-width magnification 1, which writes the character pattern data in the pattern memory as is, and full-width magnification 2, which expands 1 bit of one character pattern data horizontally to 2 bits.
The vertical magnification is 1 for full-width writing with the same number of vertical lines as the character pattern data in the pattern memory, and 1 line skipping for 172 lines, which is the number of vertical lines of the character pattern data in the pattern memory. The half-length magnification is 1/2, and the double-length magnification is 2, which is written twice on two consecutive lines with twice the number of vertical lines of the character pattern data in the pattern memory. is divided into two groups, each group includes the above vertical magnification, and the text mode writing means is
The information storage device according to claim 1, wherein the vertical magnification corresponding to the parameter in the horizontal magnification group corresponding to the parameter set by the instruction decoding means is written. (3) The character pattern data in the pattern memory is an integral multiple (1 or more) of the address unit for writing position specification, and the space between characters of the parameter set by the instruction decoding means is an integral multiple of the address unit (from 0 to The information storage device according to claim 1, wherein the information storage device is: (4) The information storage device according to claim (3), wherein the character pattern data in the pattern memory is an integral multiple of twice the address unit in the vertical direction. (5) The information storage device according to claim (1), wherein the predetermined area is an area set by instruction decoding means. (6) The text mode writing means sets the start point of the first writing area after power-on to the writing start end of the page memory, and after - times of writing, the starting point of the character writing area is set to the previous writing area. Claim No. (1) that follows the end point of the writing process of
or (5). (7) The information storage device according to claim (1), wherein the page memory output means outputs the data of the page memory a number of times set by the instruction decoding means. (8) The page memory output means according to claim 1 or 7, wherein the page memory output means clears or holds the page memory in accordance with the post-output memory processing instruction set by the instruction decoding means. Information storage device. (9) The page memory output means is configured to output data of a predetermined section of the page memory to the output device in synchronization with a signal provided by an external output device. information storage device. (10) The input/output interface is equipped with a DMA controller, and the page memory output means transfers the data in the page memory to the output device by using the DMA controller to transfer it to the parallel-in/serial-out buffer, and then transfers the data in the page memory to the output device. An information storage device according to claim 1 or claim 7, which serially outputs data in synchronization with the operation of the information storage device.