JPS59163858A - Gaas logic integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption per a gate by controlling a DFET for a load by an input signal to turn the DFET ON-OFF and operating the DFET in a false complementary type. CONSTITUTION:When an input signal VIN is at a high level, an EFET 51 and a DFET 53 in a driver are turned ON, voltage 56a, 56b among drains and sources operates as limiters to gates in the EFET 51 and the DFET 53, and the flow-in of currents from the gates are inhibited. The drain potential of the DFET 53 is brought to approximately control voltage VSS, and applied to a gate in a DFET 52. On the other hand, when the pinch-OFF voltage of the DFET 52, the both terminal voltage of diodes 541, 542, voltage VSS, etc. are set under some conditions, the EFET 51 is turned ON and the DFET 52 is turned OFF when the signal VIN is at the high level. When the signal VIN is at a low level, the DFET 53 and the EFET 51 are turned OFF, and the DFET 52 is turned ON.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to GaAs logic integrated circuits.

[Technical background of the invention and its problems]

Conventional GaAs logic integrated circuit (hereinafter abbreviated as GaAsIC)
As a circuit configuration method, BFL (Bufferea
FETLogic), 5DFL (5chott
ky Diode FET Loglc) and tri D
CFL (Direct Coupled FET L
ologic) is known, and vigorous research and development is being carried out in various places. The circuit components include FET
, diodes, resistors, etc. Among these, GaAs IC
Schottky gate FETs (MESFETs) are used as FETs that are important for implementation, but they can be roughly divided into two types: normally-on FETs and the latter, which It is in a non-conducting state and is also called an enhancement type. Below, normalion a
'↓F'ET to DFET, normally off type, FET
All EFEs are called 'I'. When the DFET is basically Ti'ET', the DCFLf9 is dropped. BET in Figure 1, 5r) F'L in Figure 2.

,−,□・ Figure '3 shows the circuit configuration of the DCFL.

In the BFL of FIG. 1, DFET units (I11-114) serving as drivers and DFET 12 serving as a load are arranged in series, and the input signal VIN is inverted.

The input date of the next stage is D
Because it is composed of F'ET! , cannot be used in Kashi,
It is necessary to perform a level shift '(r). Therefore, an I/bell shift circuit consisting of a source follower DFET 13, a Schottky diode z4 (141 to I43), and a DFET 15 as a current source is provided in the output stage. The shift circuit uses a DFE as a current source.
Current always flows due to T15, so power consumption is large.

In the 5DFL shown in FIG. 2, an inverter is configured with a DF'ET 21 as a driver and a DFET 22 as a load, and the level shift of the input signal is performed at its input section. That is, Schottky diode 2s for logic dirt
(,?sI,zs2), Schottky diode 24 for level shift and DFET 25 for current source
Since the input level shift circuit is constituted by this and the inverter driver EFET 21 is included, the power consumption is lower than that of the BFL, but power must still be consumed for the level shift.

In the DCFL shown in Fig. 3, an EFET is used as a driver.
31, DFgT as the load, 9. ,? Use.

Therefore, the 7th level of the output signal VOUT can operate the date of the next stage, and can be made to be a level tipple with the input signal vIN. Therefore, BF'L and 5D
There is no need for a level shift circuit as in the case of FI, and operation can be performed with lower power consumption. On the other hand, since the EFET is used as a driver, in order to output a low level, it is necessary to use I as the load DFET.
It is necessary to use a device with a small SS rise current capacity, which has the disadvantage that the drive ability is affected and the operating speed is somewhat slow.

FIG. 4 shows the relationship between delay time per r-) and power consumption of various logics and integrated circuits that have been reported up to now. GaA
It is clear that DCF'L has the lowest power consumption in s-, but BFI using DI'ET.

The operating speed tends to be slightly slower than 1 and 5DFL.
``Yes. Regarding power consumption, Ga'As is St, so when considering the high integration of GaAs IC, the practical upper limit is about 1 W per chip considering the heat dissipation conditions of the IC. This is a direct application of the 5t IC example, and in the case of GaAs, the thermal conductivity is lower than that of Si, so the upper limit may be lower than that of St.

6- Therefore, if we try to realize a GaAs LSI with a scale of several thousand Daltons or more, the power consumption will be several tens of thousands.
It is necessary to lower it to below 0 μwB. It is impossible to achieve this using BF'L or SDF'L, and even if DCFL is used, it is expected that difficulties will occur.

Further, in the case of DCFL, there is a problem in that the operating speed becomes slower due to the increased load as the degree of integration increases. This is due to the small drive ability of the DCFL. Therefore, the load dependence of the propagation delay time τ and d per date is for DCFT, so the capacitance between the ground plane and the ground plane becomes a large load. Over some amount
:′.

・No. 11 is also a load. Moreover, it is generally necessary for the output of one logic r-) to be connected to the power of several logic darts due to the large one-way configuration, and the input capacity of this next stage also becomes a large load. These capacitive loads have a width of 4. 100-200 fF/ with 1m wiring
rtan.

5 to 10 fF/4 for a 4 μm x 4 μm crossover
However, it is estimated that each fanout is about 100 to 200 fF, and the average wiring length in the IC is 31Il+11. The average fanout is 3. If the average number of crossovers is 20, the load capacity carried by one logical dart is 07~],, 4
pF. This is a dart length of 1 μm and a dart width of 10 to 2
In the case of a DCFL logic dart composed of FETs of about 0 μm, the current drive capacity is several mA, and the τ, d is several hundred tones.
corresponds to Furthermore, when considering the interface with the external circuit of the IC, the output circuit is an order of magnitude higher than the capacitive load of the internal circuit.
Moreover, it becomes necessary to drive a large load. In this output circuit, if the speed of the IC is not lost, the output 11
・”, 1 8- It turns out that if we try to realize this, it will be extremely difficult with the currently known circuit configurations.

[Purpose of the invention]

The present invention was made in view of these drawbacks of the conventional GaAs IC circuit configuration, and aims to provide a basic dirt circuit configuration with low power consumption per card and high drive capacity that can withstand increased loads. shall be.

[Summary of the invention]

The present invention uses an EFET as a driver and a DFE as a load.
Based on an inverter circuit using T'e, the load DFgT is controlled on and off by human power signals,
Performs pseudo-complementary operation. Specifically, an inverter is constructed in which one or more Schottky GaAa diodes for level shifting are interposed between an EFET (first GaAsFET) as a driver and a DFET (second GaAsFET) as a load. DFET (third GaAsFET) that selectively supplies a predetermined control power to the second GaAsFET
A DFET (fourth GaAsFET
) to intervene. We prepared a DFET (fifth GaAsFET) whose gate and source were commonly connected, and connected its source to the dirt of the first GaAsFET and its drain to the signal input terminal, and further connected the dirt and source in common. Prepare DFET (sixth GaAsFET) f and connect its source to the third GaAsFET dart,
Connect the drain to all signal inputs. Then, it is necessary to set the characteristics of each element and the potential relationship of each part. (1) When the input signal is at the Akane level and the first GaAaFET is turned on, the third GaAsFET is turned on and the second GaAsFET is turned on.
The second GaAsFE is
Turn T f, H off. For example, if the saturation drain current (drain current when the dirt-source voltage is zero) of the third GaAsFET is made larger than that of the fourth GaAsFET, the control power supply can be set to approximately -1 or -2. Q of
can be applied to the aAsFET gate to turn it off.

10-2 Furthermore, when the input signal is at a low level and the first GaAsFET is turned off, no through current flows even when the third GaAsFET' is turned off and turned on. Also DC
Unlike FL, the current capacity of the load Ii'ET can be increased, so dry -? It is possible to provide a drive capability capable of supplying sufficient load current to the next stage when the FET is off.

There is also a third filter for controlling the load FET Q. 40th GaA
Since the sFET circuit section uses only the load FET as a load, high speed performance is not impaired even if the drive capacity is low and the power consumption is low.

Furthermore, the first. A 5th. By interposing the sixth GaAsF"ET, the input signal level is lower than that of the first and third G
It can effectively suppress the current flow from these gates even when the voltage is higher than the flange voltage of the aAsFET, and also prevents the low level output from rising when the main power supply voltage level is increased. It performs stable in/out movements.

EFET that will become a Lyper (first GaAsFET)
51 and the load DFET (second GaAsFET
) 52 are connected in series between the main power supply VDD and ground to form an inverter. A Schottky GaAs diode 54 (541, 5rt
2). The date of the DFET 52 as a load is connected to the control power supply VSS via a DFET (third GaAsFET) 53, and a DFET (fourth GaAsFET) that is commonly connected between dirt and source.
55k to the drain, ie, to the main power supply VDD.

Here, DFET 53 has a saturation drain current of DFE
It is set to be larger than that of T55. Also, the control power supply VSS is 0 < Vs with respect to the main power supply VDD.
It is set to a predetermined value such that s<'VDD.

The input signal vIN is also supplied to the dart through a common connection between the dart and the source. Output = VOUT is taken out from the drain of EFET 51. First, when input signal v1N is at a high level (vH), driver EFET 51 and DFET 53 are turned on (conducting state). The condition is DFET 53 Vincio 1
3- If the total voltage is V, 2, and the threshold voltage of EFET 51 is Vth, then VH-VrErb > Vss +Vp2
■VHVyEra > Vt1t
It is expressed as ■. However, VFETa is DFET 56
Ton-in-source voltage of a + VFETb DIi
'ET 56 b's drain-source voltage. These two DFETs 56a, 56b are EFgT 5
1. When the input signal applied to the dart of DFET 53 exceeds the clan f voltage between the dart and the source, and a current starts flowing from the dart to the source, it increases its own potential difference between the tunnel and the source, and the EFET 51 .

It operates as a limiter so that a current exceeding a certain level does not flow through the DFET 53 (r-). The threshold current is equal to the saturation train current of DFETs 56a, 56b. Therefore, this saturation current value is EF'ET51
, DFET 53 (D) lamp electric aEVCE +
The VCD voltage is maintained at 14-amp voltage, and the current flowing into the dart does not increase any further. Furathono Den-O is of course Vth.

VF6.1: It is a large value and EFET 51, D
It does not affect the on/off operation of the FET 53. Therefore■.

■Formula can be considered when the gate voltage is less than the clamp voltage: VH > VSS + VF6
■IVH＞Vth ■
’ can be rewritten as

At this time, since DF'ET 53 is on and its saturation drain potential is higher than that of DFET 55, the drain potential of DFET 53 becomes approximately VSS, which is applied to the gate of DFET 52 as a load. Ru. On the other hand, since EFET 5 Z is on, if DF
If ET 52 is on, connect DFET5 from main power supply vDD
2→diode 54. ．． Current flows through 542→EFET 51 to ground. When B, the output terminal potential is vOU
TI + diode 54. , 542 by 2×
VD, the source potential of DFET 52 is 5]? Vss < VOUTl+2 X VD 10V
When pt ■ is established, DFET 52 is turned off (
(non-conducting state). A sufficient condition for this is votr
Since T≧O, Vs s < 2 X Vo + Vp l
■' becomes.

In this way, by satisfying the conditions ■～■′, DF
Regardless of the past state of ET 52, when input signal vIN is high V pel VH, EFET 51 is on;
DFET 52 is turned off.

Next, when the input signal vIN is at a low level vT, the DFE
T 53 and EFET 51 are turned off. The condition is VL < VSS + Vl)2
■VL＜Vth■
It is expressed as At this time, since the DFET 53 is turned off, its drain potential is approximately equal to the main power supply VDD potential. To summarize the conditions for the above operation, VH > VSS +
Vl)2 C)'VH>V
th ■'VBB (2X
VD + Vp X(3)'VL < VSS +
VF6 ■Vt, <Vth
■Vg=Vot+tz
= VDD -2X VD ■VLmiv
out'rt and 0 0. The above formula assumes that a potential equivalent to the rising voltage in the forward direction of the diode is generated in the circuit, but it is sufficient for K to satisfy this if only a small current flows through the diode.

In this example, EFET 5Z and DF"ET 52
is when one is on and the other is off, and the main power supply VDD
→ DFET 52 → Diode 541.542 → The circuit section of control power supply VSS basically performs inversion operation and level shift operation, but its load is DFET 52
, even if the drive capacity is low and the power consumption is low, the high speed performance will not be compromised.

The next thing to consider is power consumption due to current flowing in from the previous stage 18- (equivalent to current flowing out to the next stage). This becomes a problem only when the input signal VN is at a high level vH.9Generally, in circuits using MESFETs, the input signal is applied to the dart of the FET, but since the date is a Schottky junction type, between the dart and source When the voltage exceeds the forward rising voltage (f) of the Schottky junction, current suddenly begins to flow.Therefore, the human input signal has a certain value 1
If it becomes more than this, the 'gravity' due to this will be consumed. However, in this embodiment (b), the DFET 56a.

One of the features of this embodiment is that the low power consumption achieved by complementary operation is further enhanced.

The presence of DF'ET 56 a and DFET 56 b has another effect of relaxing operating conditions.

In FIG. 7, the input/output transmission time of the circuit of this embodiment shown in FIG.
Human output transmission of the circuit excluding! Indicates temporality (x mark).

According to the circuit of this embodiment, even if the human power is higher than ], V, and L, the output it! There is no rising on the surface. DFET 56
a.

In the circuit without 56b, there is a rise, so VDD
There is a limit of 8 degrees IV for B electrons in the setting. However, according to the circuit of this embodiment, tq, b, DFET 56 a
, 56 b, VDD k I V , I-
, Ij 2K W & V
p, = -0.5V Vp, = -0.5V vth "" 0.2 V VD "= 0.8V VcL = 0.7V vDD -3V VSS -IV When set to If all the conditions are satisfied, then the in/ζ-meta operation of the circuit of this embodiment can be performed normally.

Next, considering the above operating conditions, we fabricated a prototype inverter circuit and a ring oscillator circuit using it, and the load capacity t y,
In this case, we measured the propagation delay time and power consumption per case.
A prototype oscillator circuit using a /I) type r) CFL was fabricated and its characteristics were measured. The data will be explained below. Formation of active layers for FETs and Schottky diodes was carried out. Next, the AII G e ohmic electric board is completely formed, and then the Schottky gate electrode of the FET, the Schottky electrode of the Schottky diode, and the (-
FE with pt7 (Gaε deposited and tanta treatment at 400℃)
Control the binge-off voltage, threshold, and hold voltage of T, and set the EFET threshold voltage to 0.2.
V, pinch-off electric FE of DTi”ET is 10,5
It was set to V.

The ring oscillator circuit had 15 stages, and a square Schottky diode with a side of 50 Jim was inserted between the output line and the ground terminal as a capacitive load in each stage. The circuit diagram is shown in FIG.

Table 4 shows the results of measuring the ring oscillator oscillation waveform and determining the propagation delay time τpa, power consumption Pd, and logic amplitude 22-ΔV per stage.

Table 1 Table 4 'f'l load capacity of each stage of ring oscillator Ft li it
pF~! , showing the characteristics in SI1. You can think of it as something that If you look at the circuit in this example, the high speed is 71 points lower than the 5 small DCFL in terms of τpa 'Pd dipping.

f: It became clear that the circuit had excellent waste power consumption. Moreover, the word j Rishin transmission is 2.5V and the dog hears, DCFL
This is 45 times more than the previous year.

In the circuit of this embodiment, EFET51 and DFET52
Although the DFET 55 is essentially a problem due to its quasi-complementary operation, the DFET 55 is of great significance in speeding up the operation when the DFET 52 is turned on from off.

Also, as is clear from FIG. 5, the circuit of this embodiment uses only one EFET, which is difficult to control in the manufacturing process, and all others are 8t! ! It is an easy-to-manufacture FET. As a result, the production yield of the circuit of this embodiment is 0/D type DCFL.
They can be considered to be basically the same level, and the performance/price ratio of the IC is high. In this way, EF with low manufacturing yield
The reason why pseudo-complementary operation can be realized with only one ET is due to the presence of the diode 54 and the supply of the control power supply VSS, which is from /'1-.

The circuit of the present invention has a power supply voltage Vnl), Vss, the number of Schottky diodes 54, and a reverse saturation current (J
], depends on the diode junction area), the pinch-off voltage of DFET25-, the threshold voltage of EFET, etc. can be changed to increase the logic amplitude. Moreover, the circuit of the present invention uses DFET56a.

Since the DFET 56b prevents a clamping phenomenon from occurring at the gate portion of the FET, the I-1 degree of freedom is large when changing each portion to increase the logic amplitude.

Therefore, the circuit of the present invention can easily be operated at a TTL convertible level, and the problem of the interface method between GaAs IC and other circuits can be solved.

Even when building a system using only advanced GaAs ICs, noise resistance measures are important for signal transmission between IC chips, and if you want to increase noise resistance, use EFET 51.
, just change the gate width of DFET 52,
Nevertheless, due to the complementary operation, the power consumption is quite low.26---As detailed above, according to the present invention, the conventional BFL
With the number of devices comparable to that of 5DFL and 5DFL, and the process technology comparable to DCF'L, it is possible to achieve significantly superior high speed, large drive capacity, and low power consumption compared to these circuits.
It plays an extremely important role in the development of GaAsIC into LSI.

In the above explanation, an example using only GaAs IC (i-) was shown, but since the MESFET is a constituent F'ET, the present invention is also applicable to cases where other semiconductor materials such as InP, 81, etc. are used. Is possible.

Also, in FIG. 5, DFET 55 is DF'ET 53
Since it has the role of a load, the same effect can be obtained even if it is replaced with a resistor.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a logic dart circuit using GaAs MESFET called BFL, Fig. 2 is a diagram showing the speed-power consumption range of various logic circuits called 5DFL, and Fig. 5 is an embodiment of the present invention. FIG. 6 is a circuit diagram of a Mototomi 14-wire logic circuit for GaAs IC, and FIG. 6 is a diagram showing the input-output characteristics of the circuit shown in FIG. 5, which was prototyped and measured. S?・EFET (first GaAsFET), 5
2 =-DFET (second GaAsFET), 53-
DFET (third GaAsFET), 541
+542 =-Schottky GaAs diode, 5
5...DFET (4th GaAsFET), 56a
-・-DFET (fifth GaAsFET), 56
b,...DFET (sixth GaAsFET),
VDD ``'Main power supply, VSS...Control power supply.

Claims (1)

[Scope of Claims] (1) A normally-off type first GaAsFET serving as a driver of an inverter circuit, a normally-on type second GaAsFET serving as a load, and these first and second GaAsFETs.
G for level shifting interposed between GaAs FETO of
an aAs diode, a normally-on type third GaAsFET that is controlled by an input signal supplied to the first GaAsFET and selectively supplies a predetermined control power source to the second GaAsFET;・A fourth normally-on type GaAsFgT whose sources are connected in common and whose sources and drains are connected to the gate and drain of the first GaAsFET, respectively, and a dirt source.
:l-connected and the source side is connected to the first GaAsFET.
A normally-on type 50 GaAsFET connected to the dirt of the transistor and having its drain side connected to the signal input terminal, and the third GaAsFET with the dirt and source connected in common and the source side connected to the third GaAsFET.
A sixth normally-on GaAsFET is connected to the dirt of the ET and the drain side is connected to the signal input terminal.When the input signal is at a high level, the first and third GaAsFETs are turned on and the third GaAsFET is No. 2 GaAs FET is turned off, and the input signal is input to the GaAs logic integrated circuit. (3) The fifth GaAsFET has its saturation voltage V
The in-current is set to be smaller than the current corresponding to the forward rising voltage in the dirt-source diode characteristic of the first GaAsFET, and
The sFET has its saturated drain current mirror the third GaA
The G a A according to claim 1 is set to be smaller than the current corresponding to the forward rising voltage in the sFET0-to-source diode characteristic.
s logic integrated circuit.