JPH0411050B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to GaAs logic integrated circuits. [Technical background of the invention and its problems] In recent years, devices with ultra-high speed and low power consumption characteristics have been developed.
GaAsIC is being actively researched in various places. this
In order to take advantage of the high-speed performance of GaAsICs in electronic systems, it is important to increase the integration density of the ICs. for that purpose,
A basic logic gate circuit with low power consumption is essential. DCFL (Direct-Coupled FET
A circuit called Logic) is considered to be the most promising circuit for this purpose, and LSI-level GaAsICs based on this circuit have already been prototyped. DCFL
The basic circuit of is shown in Figure 1. Normally-off type GaAsFET (hereinafter referred to as EFET) 11 for the driver, and normally-off type GaAsFET (hereinafter referred to as DFET) 1 for the load.
2 is used. Input signal V _IN is applied to the gate of EFET 11, and output signal V _OUT is taken out from the drain of EFET 11. FET is a metal shot junction type FET
(MESFET) or p-n junction FET (JFET), when an input signal higher than the rising voltage of the gate-source diode is applied to the gate of EFET 11, a current flows between the gate and source.
There is a clamping effect that the input signal cannot exceed this rising voltage. This rising voltage is
For GaAs MESFETs, it is usually around 0.6 to 0.8V.
Therefore, in DCFL, the high level is 0.6~
0.8V, low level is about 0V, logic amplitude is 1V
This is extremely small compared to SiIC CMOS and TTL circuits. Naturally, therefore, the noise margin is small and the logic level cannot be set to be compatible with CMOS and TTL. This means that GaAsIC
In addition to making internal noise countermeasures difficult, it is extremely susceptible to noise especially as an output signal to the outside of the IC, and it also has the disadvantage of not being able to be directly coupled to a SiIC. On the other hand, the current due to the clamp effect causes unnecessary power consumption, which is an obstacle to reducing power consumption. [Object of the Invention] An object of the present invention is to provide a GaAs logic integrated circuit having a basic logic gate that eliminates the shortcomings of DCFL, such as small logic amplitude, small noise margin, and increased power consumption due to clamping effect. [Summary of the invention] The present invention is a driver that constitutes a DCFL.
EFET (first GaAsFET) and load
In addition to the DFET (second GaAs FET), one or more GaAs diodes are connected between the gate of the FET and the signal input terminal in order to expand the logic amplitude, and
A basic logic gate is configured by providing a discharge circuit that discharges the accumulated charge in the gate of the EFET when the input signal becomes a low level, and in addition to the basic logic gate configuration, the EFET is connected in series with the GaAs diode. DFET (third
The gist is to configure basic logic gates by providing GaAsFETs. [Effects of the Invention] According to the present invention, the logic amplitude and noise margin can be increased by using, as the GaAs diode, one having substantially the same characteristics as, for example, the gate-source diode of the EFET. Therefore, it is possible to realize a GaAs logic circuit whose logic level is set to be compatible with CMOS and TTL. Moreover, in the present invention, by providing a discharge circuit in parallel with the GaAs diode,
It can ensure the same high speed as DCFL. Further, according to the present invention, by providing a DFET in series with the GaAs diode and utilizing the voltage drop between its drain and source, it is possible to effectively suppress the clamp current of the driver EFET and achieve low power consumption operation. . [Embodiments of the Invention] Next, details of the present invention will be specifically explained with reference to the drawings. FIG. 2 shows a circuit that is the basis of the present invention. EFET21, which is a driver, becomes a load.
It is the same as the DCFL in that it is connected to the DFET 22 to form an inverter, but a GaAs diode 23 is connected to the gate of the EFET 21. Here, the characteristics of the diode 23 are made to be the same as those of the diode between the gate and source of the EFET 21. In this circuit configuration, the voltage at the input terminal is V _IN
When , the gate-source voltage of EFET21 is
V _IN /2. Therefore, EFET21, DFET22
EFET11 and DFET in Figure 1 which are DCFL circuits
12, the circuit in Figure 2 will generate the same output terminal voltage V _OUT as the DCFL circuit in Figure 1 when an input signal of exactly twice the voltage as the input signal of the DCFL circuit is applied. It turns out. Naturally, when viewed from the input end, the clamp voltage in the circuit of FIG. 2 is twice that of the DCFL circuit in FIG. 1. In this way, the basic principle of the circuit of the present invention is that the logic amplitude and noise margin are twice as large as those of the DCFL. If you want to make it triple, use diode 23
Just place another diode in series similar to . Generally speaking, when trying to obtain the same output voltage V _OUT as the DCFL shown in Figure 1 with an input signal of N times the voltage, it is necessary to make the characteristics the same as the gate-source diode of EFET21 as shown in Figure 3. Do (N-1)
It is sufficient to arrange GaAs diodes 33 ₁ , 33 ₂ . . . 33 _N-1 connected in series. 31,3
2 correspond to 21 and 22 in FIG. 2, respectively. 1st
A comparison of the input/output transfer characteristics of the DCFL circuit shown in the figure with those of FIGS. 2 and 3 results in the results shown in FIGS. 4a, b, and c. a schematically shows the characteristics of the DCFL in Figure 1, b shows the characteristics of the circuit in Figure 2, V _DD = 1.5V
is assumed. c is a characteristic for the circuit of FIG. 3, where V _DD is at least greater than the input voltage 0.2N to 0.4N corresponding to the transition region of the inverter. Note that since the current of the diode increases exponentially with respect to the terminal voltage, the logic amplitude does not vary much depending on the size of the junction area. In that sense, in terms of reducing the area of the IC,
The diode junction area should be as small as possible so that destruction does not occur even with the maximum current that can flow. However, when considering high-speed operation, signal transmission by capacitive coupling of diodes also contributes to high speed, so from that point of view it is better to have a larger junction area. Therefore, it is necessary to select the bonding area by considering both factors. In this way, basically by adopting the circuit configuration as shown in FIG. 2, it is possible to realize a basic inverter circuit having arbitrary logic amplitude and noise margin, which is better than that of the DCFL circuit. The circuit of the present invention is constructed by adding a discharge circuit to the basic circuit shown in FIG. 2 or 3.
An example thereof is shown in FIG. 51 to 53 are the same as 21 to 23 in FIG. 2, respectively, and a diode 54 is newly connected in parallel with diode 53. However, the polarities of both are opposite. The role of this diode 54 is to speed up the basic inverter circuit shown in FIG. In the circuit shown in Figure 2,
When V _IN changes from low level state to high level,
The capacitance between the gate of EFET 21 and ground is charged by the forward current of diode 23.
When V _IN changes from high level to low level,
The only way to discharge the charge accumulated in the capacitance between the gate and ground of EFET 21 is by the diode between the gate and source of EFET 21 and by the reverse current of diode 23. This is slower than the change from level to low level, and as a result, the operation of the EFET 21 from on to off is also slow, resulting in a slow response speed of the inverter. On the other hand, if the diode 54 exists as shown in Figure 5, when the input changes from high level to low level, the charge stored in the capacitance between the gate and ground of the EFET 51 is discharged through the diode 5.
This can be done using a forward current of 4. As a result, the response speed of the inverter is improved. On the other hand, when the input changes from low level to high level, a reverse bias voltage is applied to the diode 54, so the DC operation of the circuit is not affected. Therefore, the junction area of the diode 54 can be made sufficiently large so that its reverse saturation current can be ignored for the current in the circuit system. This has the effect of increasing the discharge current when the input changes from high level to low level and increasing the speed of the circuit. It contributes to input signal transmission to the gate of the EFET 51 by capacitive coupling, and can contribute to speeding up. Another embodiment of the present invention is a circuit configuration that prevents clamp current from flowing between the gate and source of the driver EFET when the input signal exceeds the clamp voltage of the driver EFET. An example thereof is shown in FIG. 6
1 to 64 are the same as 51 to 54 in FIG. 5, respectively. DFET6 with newly connected gate and source
5 is prepared, its source electrode is connected to the anode of the diode 63, and an input signal is applied to the drain electrode of the DFET 65. This DFET65 is a current limiter, and if you try to flow a current higher than the drain saturation current when the gate and source are connected, a potential drop will occur between the drain and source.
Limit the current so that it does not increase. Therefore, if this drain saturation current value is set as the allowable value of the clamp current flowing between the gate and source of EFET61,
No more clamp current flows,
It is possible to suppress power consumption due to the clamping effect of the EFET 61. However, if the drain saturation current of DFET 62 is smaller than that of DFET 65, the clamping effect is limited by DFET 62, and the existence of DFET 65 becomes meaningless. DFET
62 and DFET65, the point where the logic amplitude can be increased to improve noise resistance is DFET6.
This is the reason for the existence of
Particularly effective for GaAsIC. The effect of this DFET 65 as a clamp current limiter is effective regardless of the presence or absence of the diode groups 63 and 64, and as shown in Fig. 7, it is effective as a clamp current limiter.
It is also effective when applied directly to DCFL circuits. 71,
72 and 75 are 61, 62, and 65 in Figure 6, respectively.
is the same as According to this embodiment, due to the presence of the clamp current limiting circuit, the output voltage V _OUT of the inverter will not be clamped at a high level due to the clamp current at the input of the next stage when a logic circuit is configured.
Basically, it is possible to raise the high level to near the power supply voltage _VDD . On the other hand, since the low level is almost the ground potential, the logic amplitude can be changed to TTL or
It is also possible to perform this at the CMOS level. In FIG. 6, diodes 63, 64 and
Even if the positional relationship of the DFET 65 is reversed, the effect will be the same or even the speed will be improved. FIG. 8 shows the circuit configuration of this embodiment. 81 to 85 are the same as 61 to 65 in FIG. 6, and only their connection relationship is slightly different. The reason why this result improves high speed is that the capacitance to be charged and discharged by the current passing through DFET 85 is the capacitance between the gate of EFET 81 and the ground, whereas in the case of the circuit shown in Figure 6, the current passing through DFET 65 This is because the capacitance to be charged and discharged is the gate-to-ground capacitance of the EFET 61 plus the capacitance of the diodes 63 and 64. In order to confirm the basic operation and switching performance of the circuit of the present invention as described above, we prototyped the basic inverters shown in Figures 1, 2, 5, and 6, and a 31-stage ring oscillator using these. We will explain the data that confirmed the operation by comparing the characteristics. The junction between the FET gate and diode is a shotgun junction type. Formation of active layer for FET and Schottky diode is Cr-doped semi-insulating
This was done by direct selective ion implantation of ²⁸ Si ⁺ into a GaAs substrate. The injection conditions are as shown in Table 1. Further, the dimensions of the device were set as shown in Table 2. After this, in an atmosphere of AsH ₃ (1%) + Ar
Cat press annealing was performed at 850°C for 15 minutes.
Next, an AuGe ohmic electrode is formed, and after this
Pt is deposited as the shot gate electrode of the FET and shot electrode of the shot diode, and the pinch-off voltage and threshold voltage of the FET are controlled using sintering at 400°C.The threshold voltage of the EFET is set to 0.2V, and the pinch-off voltage of the DFET is controlled. was set to −0.5V.

【table】

【table】

[Table] For the circuit thus obtained, the input-output transfer curve was determined by setting V _DD =3V, and the result was as shown in FIG. 9. However, the same inverter is connected to the next stage. a is in Figure 1
DCFL, b is the measurement result of the transfer curve corresponding to the circuit of FIG. 2, c is FIG. 5, and d is the circuit of FIG. 6, respectively. When the input is gradually increased from 0V, the output transitions from a high level state to a low level state. At this time, the high level potential of the output is _VH ,
If the low level potential is V _L and the input voltage when V _OUT = (V _H + V _L )/2 is V _T , then the DCFL in Figure 1
For the circuit, V _T =V _T1 =0.3 ^V , for the circuit shown in Figure 2.
V _T =V _T2 =0.6 ^V , for the circuit shown in Figure 5, V _T =V _T5 =
0.6 ^V , and in the case of the circuit shown in FIG. 6, V _T =V _T6 =0.6 ^V. From this, diodes 23, 53,
63, the transition region input voltage V _T becomes DCFL
It is clear that the logic amplitude has increased and the noise margin has also increased as compared to the circuit. On the other hand, the input voltage V _IN is 0.8 V or more for the DCFL circuit shown in Figure 1, and 0.8 ^V or more for the circuits shown in Figures 2 and 5.
It can be seen that when the voltage is 1.5 ^V or more, the output voltage V _OUT gradually increases from a low level. This is an EFET
This is because current flows from the gate to the source of the EFET (clamping effect), causing a potential drop in the series resistance component within the EFET, which appears at the drain electrode. This is a factor that determines the upper limit of the power supply voltage V _DD in inverter operation. . On the other hand, in the circuit shown in Figure 6, no such rise in V _OUT is observed, and
It can be seen that the power supply voltage V _DD can be set freely. Next, we will discuss the measurement results of the ring oscillator. Ring oscillator measurement is generally used as the most reliable method for determining the switching characteristics of the basic inverters that make up the ring oscillator. From the oscillation period, the transmission delay time of the inverter, that is, the basic logic gate, becomes clear, and the DC power supplied to the ring oscillator is the sum of the power consumed by each inverter, so the power consumption per logic gate is known. Furthermore, the multi-stage ring oscillator corresponds to viewing the switching phenomenon that occurs at high speed by extending the time axis, and since the waveform can be observed below the cut-off frequency of the measurement system, it becomes easy to measure the logic amplitude. Table 3 shows figures 1, 2, and 5.
31 The circuits shown in Figures and Figure 6 are used as a basic inverter.
The characteristics of each inverter obtained from the stage ring oscillator are shown. τ _pd ·Pd/ΔV was considered as an index for comprehensively evaluating noise resistance, high speed performance, and low power consumption, and this was also written down. However, τ _pd is the transmission delay time per gate, Pd is the power consumption per gate, and ΔV is the logic amplitude.

[Table] From this result, it was found that in the circuit shown in Fig. 2, the logic amplitude is doubled, but the high-speed performance is extremely inferior. In other words, the diode 23 contributes to increasing the logic amplitude and noise margin, but it alone does not
The high-speed performance of DCFL cannot be maintained. The cause of this is
As described above, only by inserting the diode 54 as shown in FIG. 5, for example, can the logic amplitude and noise margin be improved while maintaining the high-speed performance of the DCFL. This is clear from the measurement results in Table 3, and in the circuit shown in Figure 2, τ _pd =
What used to be 3.3nsec/gate can be changed to τ _pd =
This means that the speed can be increased by more than an order of magnitude to 0.314 nsec/gate. Furthermore, since the logic amplitude and power consumption remain the same, the effect of the diode 54 is tremendous. The circuit in Figure 5 has a high speed with τ _pd
Although it is about 10% slower than DCFL, the power consumption is almost the same, and the logic amplitude is
2.2 times, DCFL with the index τ _pd・Pd/△V
It was shown that it can be reduced to 1/2. In other words, the circuit shown in Figure 5 has achieved the revolutionary effect of doubling the logic amplitude while maintaining almost the same high speed and low power consumption as DCFL. be. By the way, the data in Table 3 was measured under a power supply voltage V _DD = ^3V . For DCFL, this supply voltage may be a little large to achieve the minimum of τ _pd Pd. Therefore, Table 4 shows the characteristics of the DCFL ring oscillator when V _DD = 1.5 ^V.

[Table] From this table, τ _pd・Pd is 60% compared to when V _DD = 3 ^V.
%, and in that sense, 1.5V is better than DCFL.
This may be a good condition for bringing out the strengths of the company. However, τ _pd is 0.33 ns/gate, which is the fifth
It is inferior to the circuit shown in the figure. In the end, the comprehensive index τ _pd・
Pd/ΔV is also about 20% inferior to the circuit shown in FIG. Moreover, the logic amplitude and noise margin are inferior, but not superior. As described above, the circuit shown in FIG. 5 can increase the logic amplitude and noise margin, which could not be achieved with a DCFL. Moreover, a major feature is that it can be realized without sacrificing high speed and low power consumption. The circuit shown in FIG. 6 has a lower τ _pd than the circuit shown in FIG. 5, but since the clamping effect of the EFET is prevented, the logic amplitude is 1.78V, which is approximately 60% larger. Although the power consumption is slightly lower, at V _DD = 3 ^V ,
Since the power consumption due to the clamp current does not account for a very large proportion, there is no significant difference compared to the circuit shown in FIG. As a result, the comprehensive index τ _pd・Pd/△V is 0.14
[PJ/V] is only slightly inferior to 0.132 [PJ/V] of the circuit shown in FIG. The circuit in Figure 6 has a feature that the circuit in Figure 5 does not have, because the logic amplitude can be increased by increasing V _DD .
Which circuit to select may be determined depending on the conditions required for the circuit. As described above, according to the circuit of the present invention, it is possible to significantly increase the logic amplitude and noise margin without sacrificing the high speed performance of the DCFL circuit. Furthermore, this can be achieved without paying the price of increased power consumption, making it extremely effective as a basic circuit for GaAs logic integrated circuits. The circuit of the present invention is also effective for use in GaAsIC interface circuits. The logic circuit inside the GaAsIC is composed of a conventional DCFL circuit, and by using the circuit of the present invention in the input/output section, it is possible to adapt it to the logic level of SiIC such as TTL and CMOS. FIG. 10 shows an embodiment applied to an input interface circuit. Area A in the diagram is SiIC such as TTL or CMOS, area B
The area is a GaAsIC, _B1 is an interface circuit, and _B2 is a logic circuit section using DCFL. Consider the case where the low level of a TTL or CMOS circuit is defined as V _L and the high level as V _H , and V _H > 2 ^V and V _L < 0.7 ^V. In the input interface circuit of Figure 10, the threshold voltage of EFET101 is
V _th , diodes 103 ₁ , 103 ₂ ..., 103 _N
Letting the number of _-1 's be N, the following must hold: V _L <(N+1)V _th . . . (1) V _H > (N+1) V _th + α . . . (2). Since it is common to set V _th =0.2 ^V , N≧3 is obtained from (1) considering that N is an integer. On the other hand, α=
Since it is about 0.2 ^V , we get N≦8 from (2). Considering the operational margin and process variations in V _th and α, it would be appropriate to select N from among 4, 5, 6, and 7. Among them, it is considered optimal to select N=4, which requires less area. DFET10
Without 5, when the high level of SiTTL or CMOS is large and there is sufficient drive ability (current drive ability), the clamp current flowing between the gate and source of EFET 101 may become excessive and cause damage. , this can be prevented by the DFET 105. This makes it possible to connect directly to the other device, regardless of its output buffer, SiTTL or CMOS, as long as it satisfies the voltage conditions (V _H > 2 ^V , V _L < 0.7 ^V ). can be made to last. FIG. 11 shows an embodiment in which the present invention is applied to an output interface circuit. A area is TTL or
SiIC such as CMOS, the C region is GaAsIC, and this C region consists of a logic circuit section _C1 using a DCFL (or the circuit of the present invention) and an output interface circuit section _C2 . Output interface circuit section C ₂ , C ₃
This part is the basic inverter circuit of the present invention.
The output from the logic circuit section _C1 inside the GaAsIC is first connected to the external SiTTL or CMOS power supply (+5 ^V ).
The signal is input to an inverter consisting of an EFET 116 and a DFET 117, which are made identical to each other. Its output is the inventive circuit of diodes 113 ₁ to 113 _N-1 and 114, DFET115, EFET111, and DFET1.
It is input to an inverter consisting of 12. EFET
Since the inverter consisting of DFET 116 and DFET 117 has no clamping effect, the low level of its output is 0 ^V ,
High levels can rise to nearly +5 ^V. However, the transition voltage (the input voltage when the output goes from low level to high level or vice versa) is the same as that of the DCFL circuit. Therefore, the transition voltage is
Unlike SiTTL and CMOS, this output can be used as is.
Passing it to SiTTL or CMOS input will cause malfunction. One method is to keep the transition voltage the same as the external circuit within a low-noise GaAs chip. The inverter consisting of the circuit according to the invention in region _C3 plays this role. The number N of the diode groups 113 ₁ to 113 _N-1 has the function of changing the transition voltage by (N+1) times, but N=
Approximately 5 is appropriate. As described above, if the circuit of the present invention is used, GaAsIC
This makes it extremely easy to use in electronic systems, including when it is mixed with other logic ICs, and has a significant effect on improving the practicality of GaAsICs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional DCFL circuit, FIGS. 2 and 3 are diagrams showing the basic circuit configuration of the present invention, and FIG. 4 is a diagram showing the DCFL circuit in FIG.
5 is a diagram showing a circuit configuration of one embodiment of the present invention. FIG. 6 is a diagram showing a circuit configuration of another embodiment. Figure 7 shows how to prevent the clamping effect shown in Figure 6.
Figure 8 shows a modification of Figure 6, and Figure 9a shows that it can be directly applied to the DCFL circuit.
~d are diagrams showing the measurement results of the input and output transfer characteristics of the basic inverters shown in Figures 1, 2, 5, and 6, respectively.
FIG. 11 is a diagram showing an embodiment in which the present invention is applied to an output interface circuit of a GaAs IC. 51, 61, 81, 101, 111...driver EFET (first GaAs FET), 52, 62, 8
2,102,112...Load DFET (second
GaAs FET), 53, 63, 83, 103, 11
3...GaAs diode, 54, 64, 84, 1
04,114...GaAs diode (discharge circuit),
65, 85, 105, 115...DFET (third
GaAs FET).

Claims (1)

[Claims] 1. A normally-off first GaAsFET serving as a driver of an inverter circuit and a second GaAsFET serving as a load.
GaAsFET, and one or more transistors connected between the gate of the first GaAsFET and the signal input terminal with a polarity that is forward biased when the input signal is at a high level.
a GaAs diode, and a normally-on type third transistor whose gate and source are connected in series with the GaAs diode to suppress the clamp current of the first GaAs FET.
A logic gate comprising a GaAsFET and a discharge circuit connected between the gate of the first GaAsFET and a signal input terminal and discharging the accumulated charge on the gate of the first GaAsFET when an input signal is at a low level. A GaAs logic integrated circuit featuring: 2. The GaAs logic integrated circuit according to claim 1, wherein the discharge circuit is constituted by a GaAs diode connected in antiparallel to the GaAs diode.