JPS59158452A - Program test device - Google Patents

Abstract

PURPOSE:To test a program by providing plural buffer memories and a fully inputted buffer memory detecting circuit, and collecting a C1 coverage index representing whether or not a branch instruction is executed normally. CONSTITUTION:Every time a CPU1 executes a program and executes the branch instruction, its address data and an address data of destination designated by its branch instruction are stored sequentially in a buffer memory 10. When the buffer memory occupancy detecting circuit 13 detects the storage area of the memory 10 is fully inputted, the circuit 13 changes over an input switching circuit 9 to a buffer memory 11 and an output switching circuit 12 to the memory 10. Every time a branch instruction of CPU1 is executed further, the address data is stored in the memory 11. Furthr, each address data stored in the memory 10 is transferred to a data collecting device 14 to collect the C1 coverage index.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program testing device, and in particular, to a program testing device that tests whether or not each step of the flow branched by the branch instruction has been executed when a program including a branch instruction is executed. The present invention relates to program test equipment such as the following.

BACKGROUND OF THE INVENTION FIG. 1 is a flow diagram showing the flow of a general program that is the background of this invention. In FIG. 1, the program includes steps (abbreviated as SP in the diagram) 1 to 4, step 1 is a branch instruction, and if the content A is determined and YES, steps 2 to 4 of flow A are executed. Proceed to step 3 and execute steps D to D of each step. If No in Step 1, Step 4 of Flow B
Branch to and execute its contents.

In order to test whether a computer can normally execute the above program, it is necessary to debug the created program to find bugs. but,
In order to perform such debugging, a large computer is required, and it has not been possible to directly test the program.

On the other hand, these days, to check the integrity of testing (or debugging) a program, a more efficient method is to check what parts of the program have not yet been executed, rather than how the program has been executed. The need to clarify this has arisen. Recently, coverage analysis has been introduced as a method for testing programs.

In a program that includes a plurality of steps in coverage analysis, the ratio of the number of steps executed at least once is called the C1 coverage index. Until now, there has been no device that collects C1 coverage indicators and tests programs.

OBJECTS OF THE INVENTION Therefore, a main object of the present invention is to provide a program testing device that tests a program by collecting at least a C1 coverage index indicating whether a branch instruction has been executed normally.

Structure and Effects of the Invention To summarize the present invention, there is provided an apparatus for testing a program including at least a branch instruction, which detects data when a central processing means executes the branch instruction. At least two storage means for storing address data are provided, and it is detected whether the storage area of any one of the at least two storage means is empty or full. The detected storage means is configured to store address data representing each of a branch instruction and a destination specified by the branch instruction.

Therefore, according to the present invention, since the 01 coverage index can be sequentially stored in at least two storage means, the processing speed of the floppy disk or magnetic tape for processing the C1 coverage index stored in at least two storage means is Even if the processing speed of the central processing means is slower than the processing speed of the central processing means, the data stored in at least two storage means can be processed in real time without reducing the processing speed of the central processing means.

Hereinafter, this invention will be described in more detail with reference to embodiments shown in the drawings.

Description of examples FIG. 2 is a schematic block diagram of an embodiment of the present invention.

First, the configuration will be explained with reference to FIG. A CPU 1 as a central processing means executes a built-in program, and a data bus DB, an address bus AB, and a control bus CB are connected to this CPLJl. An instruction decoder 2 is connected to the data bus DB. This instruction decoder 2 outputs a signal to the data bus DB when the CPUI executes a branch instruction included in the program.
= A branch instruction is detected by decoding the output fetch data. When the data based on the branch instruction is decoded by the instruction decoder 2, the decoded output is applied to the flip 70 tube 3 and one input terminal of the OR gate 4.

Further, a control circuit 8 is connected to the control bus CB. This control circuit 8 outputs a timing signal every time CPLll executes a program.

This timing signal is applied to the instruction decoder 2 and also to the reset input terminal of the knob 70 via the delay circuit (DL) 7. Delay circuit 7 is 1c
It is delayed by the pu cycle period. Therefore, the flip-flop 3 is set when the instruction decoder 2 detects a branch instruction, and is reset after one CPLJ cycle period has elapsed during which the destination address of the branch instruction is output. That is, the flip-flop 3 is set from the time a branch instruction is output until the address of the destination branched by the branch instruction is output.

The output of flip-flop -0-3 is applied to the other input terminal of OR gate 4. Therefore, the OR gate 4 applies a high level signal to one input terminal of the AND gate 5 from when the branch instruction is output until when the destination address according to the branch instruction is output. A timing signal is applied from the control circuit 8 to the other input terminal of the AND gate 5. therefore,
AND gate 5 provides a timing signal to register 9 from when a branch instruction is output until when the destination address according to the branch instruction is output. On the other hand, address bus AB
A register 6 is connected to. This register 6 is for storing address data representing a branch instruction and a destination specified by the branch instruction. The output of register 6 is given to input switching circuit 9. Input switching circuit 9 is for providing address data stored in register 6 to buffer memory 10 or 11. A timing signal is applied to buffer memories 10 and 11 from AND gate 5. Therefore, the buffer memory 10 or 11 sequentially stores address data applied via the input switching circuit 9 based on the timing signal from the AND gate 5. Buffer memory 10 and 1
The output of 1 is applied via an output switching circuit 12 to a data acquisition device 14 such as a magnetic tape or a floppy disk. The buffer memory fullness detection circuit 13 detects whether the respective storage areas of the buffer memories 1o and 11 are empty or full. When the buffer memory full detection circuit 13 detects that the storage area of the buffer memory 1o is full, for example, it switches the input switching circuit 9 to the buffer memory 11 side and switches the output switching circuit 12 to the buffer memory 10 side. . If the buffer 1 memory 11 is full, the input switching circuit 9 is switched to the buffer memory 1oWJ, and the output switching circuit 12 is switched to the buffer memory 11 side.

FIG. 3 is a flow diagram for explaining the operation of FIG. 2. Next, the operation shown in FIG. 2 will be explained with reference to FIG. CPLJl fetches and executes branch instructions based on the program. Then, data is provided to the instruction decoder 2 via the data bus DB. Based on the timing signal from the control circuit 8, the instruction decoder 2
It decodes the data from the CPUI, outputs a branch instruction decode signal, and sets the flip-flop 3.

At the same time, the decode signal is applied to the AND gate 5 via the OR gate 4.
provides the timing signal from the control circuit 8 to the buffer memories 1o and 11.

On the other hand, the buffer register 6 stores address data output when CPLJl executes a branch instruction. This address data is given to the input switching circuit 9. At this time, the buffer memory full detection circuit 13 detects whether or not each storage area of the buffer memories 1o and 11 is full. For example, if the buffer memory 10 is empty, the input switching circuit 9 is switched to the buffer memory. At the same time, the output switching circuit 12 is switched to the buffer memory 11 side.
switch to the side. Therefore, the buffer memory 19-O reads the address data stored in the register 6 based on the timing signal. After executing a branch instruction, CPLJl outputs the address data of the destination specified by the branch instruction and stores it in the register 6. At this time, the delay circuit 7 delays the timing signal output from the control circuit 8 by one cycle W of CPLll, so the flip-flop 3 maintains its set state.

Therefore, the set output of flip 70 block 3 continues to open AND gate 5 via OR gate 4. For this reason, the timing signal continues to be applied to the buffer memory 10. That is, the buffer memory 10 reads the address data stored in the register 6. After the CPU cycle has passed, the flip 70 knob 3 is reset and the AND gate 5 is closed. Therefore, the buffer memory 10 stores only the branch instruction and the address data of the destination specified by the branch instruction.

The above-described operation is repeated, and each time the CPU 1 executes a program and executes a branch instruction, the address data at that time and the address data of the destination specified by the branch instruction are sequentially stored in the buffer memory 10.

The buffer memory full detection circuit 13 is connected to the buffer memory 10.
When it is detected that the storage area is full, the input switching circuit 9 is switched to the buffer memory 11 side, and the output switching circuit 12 is switched to the buffer memory 10 side. IJ,
11. Every time the CPU 1 executes a branch instruction, address data is stored in the buffer memory 11 side. Further, each address data stored in the buffer memory 10 is transferred to the data collection@1114 via the output switching circuit 12.

As described above, according to this embodiment, each time CPU i executes a branch instruction, the address data of the branch instruction output and the address data of the destination specified by the branch instruction are stored in either of the buffer memories 10 and 11. Since the data in the full buffer memory is immediately read out and collected by the data collection device 14, even if the data collection device ff114 is
Even if the processing speed of pu i is high, the Cl coverage index can be collected without any hindrance.

[Brief explanation of the drawing]

FIG. 1 is a flow diagram showing the flow of a conventional general program. FIG. 2 is a schematic block diagram of an embodiment of the present invention. Figure w43 is a flow diagram for explaining the operation of Figure 2. In the figure, 1 is a CPU, 2 is an instruction decoder, 3 is a flip 70 block, 4 is an OR gate, 5 is an AND gate, 6
is a register, 7 is a delay circuit, 8 is a control circuit,
9 is an input switching circuit, 10゜11 is a buffer memory, 12
13 is an output switching circuit, 13 is a buffer memory full detection circuit,
14 indicates data collection enthusiast W. Figure 3-277-

Claims (1)

Scope of Claims: A program testing device for collecting, in a program including at least a branch instruction, a 01 coverage index indicating whether or not the branch instruction is executed when the program is executed, Central processing means for outputting, when executed, an address signal representing the branch instruction and a destination specified by the branch instruction; and for decoding data output when the central processing means executes the branch instruction. a decoder, at least two storage means, a detection means for detecting whether the storage area of any one of the at least two storage means is empty or full of data; Address data representing each of the branch instruction decoded by the decoder and the destination specified by the branch instruction is stored in the storage means whose storage area is detected to be empty by the detection means. A program test device equipped with a storage means.