JPS59161747A - Program analyzer - Google Patents

Abstract

PURPOSE:To collect only C1 coverage information within a desired address range directly from an actual machine by providing a C1 coverage information detecting circuit, area specifying circuit, overlay memory, etc. CONSTITUTION:The C1 detecting circuit 3 detects a branch instruction among instructions executed by the actual machine CPU1 and generates C1 information on the address of this branch instruction and on whether a conditional branch is caused by the branch instruction or not. The area specifying circuit 4 sets an area wherein C1 tracing is to be carried out, and consequently C1 information in the desired area can be obtained. Further, the overlay memory 5 functions as a buffer memory wherein the output of the circuit 3 is stored temporarily. This constitution collects and records only the C1 coverage information while matching the operation speed of the actual machine CPU with that of a recording device without any decrease, i.e. while operating the CPU1 on real-time basis.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a program analyzer that is connected to a device equipped with a processor and analyzes and records instructions executed during program debugging of the device and program execution paths taken.

(Background of the Invention) In general, in equipment with a built-in processor, that is, a computer system, during the development stage, etc., before shipping the product, thorough debugging is carried out to prevent program defects (bugs:
It is preferable to eliminate all bugs. However, if there are many branch instructions and the program execution path (path: paSS) is complicated, it may be difficult to debug the IS.
If the product is shipped with undebugged paths left in it, problems may occur later due to the baggage of these undebugged paths. Collection of coverage results is a method for evaluating the quality of program error detection at this debugging stage ζ, that is, the extent to which the complete 36 lines of debugging have been completed.
, C1, C2, etc. CO coverage determines whether or not all steps (instructions) have been executed during debugging, and calculates the degree of execution as an index (100 if each instruction is executed at least once). CI coverage determines whether each branch instruction passes through both branch and non-branch paths.

02 coverage determines how many times each loop has been executed.

Conventionally, each of these coverage information has been collected manually, for example by executing a simulation program one step at a time, and there has been no example of collection using a device that has a built-in processor that executes this program, that is, an actual machine. .

That is, collecting such coverage information requires time and effort.

Therefore, the present inventors extracted various data or signals from the system paths (address bus, data bus, control bus) of the actual machine or the lead terminals of the CPU built into the actual machine, and A program analyzer that detects a branch instruction, collects the address of this branch instruction and the address of the instruction executed following this branch instruction, and presents it as a set of information. is proposed.

However, in this proposed program analyzer,
The entire program of one Fuiso was analyzed and C1 information was recorded, which had the disadvantage of increasing the capacity of the recording device or memory.

On the other hand, as programs become modular, layered, or shared, programs that have been modularized in this way have already been 100% evaluated (debugged), so
CI+-
There's no need to race.

Furthermore, even if the program is newly developed, it is wasteful to perform CI tracing on parts that have already been evaluated. In fact, the C1 information may even increase, making 01 coverage processing difficult.

Therefore, the present inventors have further proposed a program analyzer in which a range comparison is performed based on switch or register '1h information, and C1 information recording, that is, Ci l-race, is performed only in a desired address range. However, as mentioned above, in the partially evaluated program, the areas that require C1 tracing do not necessarily exist sequentially, but intermittently (
May be scattered (randomly). On the other hand, with this program analyzer, due to its circuitry and configuration, the number of pirate ranges that can be set is at most several, making it difficult to set a large number of scattered areas.

(Object of the Invention) The present invention is a program analyzer that detects a branch instruction in an actual machine and creates and records the address of the branch instruction and information indicating whether or not a conditional branch has occurred due to the branch instruction. It is an object of the present invention to provide a program analyzer that collects only C1 information in a desired address range.

(Purchase and Effects of the Invention) The present invention provides a method for evaluating the quality of program debugging of equipment equipped with a processor and a program memory.
A program analyzer that collects information uses a bitmap memory that stores data of a predetermined value in bits that correspond to the address space of the program memory and correspond to the address where C1 tracing is desired. This is based on the idea that when program memory is accessed, the bitmap memory is accessed using the address corresponding to the accessed memory address, and it is determined whether the memory vacancy is an address that should be traced to C1. By using such a concept, it is possible to obtain 01 coverage information directly from the actual machine,
You can check and improve program quality, and obtain only the minimum necessary C1 information by excluding areas that have already been debugged from the C1 trace range by standardizing, layering, and structuring the program. can do. In this case, even if already debugged areas are scattered here and there, these areas can be excluded by the bitmap memory and only the areas where C1 information is required can be set. Furthermore, since it does not include any redundant information, the C1 analysis processing time can be shortened. Furthermore, it is possible to randomly trace a desired area,
Based on this information, it is possible to perform more advanced index analysis and improve the quality of the program.

(Explanation of Examples) The present invention will be described in detail below using the drawings.

FIG. 1 shows a system configuration of a program analyzer according to an embodiment of the present invention. In the figure, ``■'' is a device that executes a program to be debugged, that is, a processor (CPU) built into an actual machine. 2 is a program analyzer of the present invention, which includes a CI detection circuit 3, an area specification circuit 4, an overlay memory 5, and a recording device 6 consisting of a floppy disk or a magnetic tape device, etc.
Equipped with.

The CI detection circuit 3 detects a branch instruction among the instructions executed by the CPU of the actual machine, and creates a C11 information indicating the address of this branch instruction and whether or not a conditional branch has occurred due to this branch instruction. This C1 information may be formed by, for example, the address of a branch instruction and the address of an instruction executed following this branch instruction, or may be formed by the address of a branch instruction and a value of 1 or 1 indicating whether there is a conditional branch. It may also be formed with multiple bits of data.The area specifying circuit 4 is provided with an area where C1 tracing is to be performed.This makes it possible to obtain CI information for a desired area, and also allows information to be recorded. The amount can be compressed.

The overlay memory 5 has the function of a buffer that temporarily stores the output of the C1/l extraction circuit 3, and thereby, the operating speed of the actual CPU 1 is not reduced in accordance with the recording "A direct 6", that is, the actual CPU 1 This makes it possible to record CI coverage information while operating in real time.

FIG. 2 shows the detailed block configuration of the area specifying circuit 4 shown in FIG. 1. The area specifying circuit 4 is composed of a bitmap memory 41, a processor 42, a multiplexer 43, an AND gate 44, etc.

The bitmap memory 41 is a memory having a number of pins corresponding to the address bus of the program memory (not shown) of the actual machine, and is used as a CI trace permission flag for each pin. This bitmap memory 41 is
For example, if an actual program memory has a capacity of 64 bytes, it will have a capacity of 64 bits if it is made to correspond one-to-one with the address of the program memory. In addition,
Each bit of the pin-map memory 41 and the address of the program memory do not necessarily have a one-to-one relationship;
For example, one bit of the bitmap memory may correspond to an area consisting of 32 addresses of the program memory', and in this case, the capacity of the bitmap memory 41 may be 2 bits. Therefore, in the former case, it is possible to set the C11-race permission flag for each byte of the program memory, and in the latter case, it is possible to set the 01 trace permission flag for every 32 bytes.

The multiplexer 43 uses the branch instruction address data output from the C1 detection circuit 3' and the processor 4 of the area specification circuit 4.
2 and 9 address data is selectively inputted to the bit massi memory 41. The read pulse T1 applied to one input of the AND gate 44 is generated in a timing control circuit (not shown) in synchronization with the ration code fetch timing signal sent to the control bus of the actual CPU.

In the circuit of FIG. 2, first, the multiplexer 43 connects the address bus of the processor 42 and the bitmap memory 4.
Switch to connect to the address input of No.1. 5. Apply the write signal W from the processor 42 to the bitmap memory 41 to put the memory 41 into a write state, and send the address at which the C11-race is desired from the address bus and data bus of the processor 42 to the program memory of the actual machine. (Data of a predetermined value is written to the corresponding address. For example, as the data of the predetermined value, "1", that is, a c1 trace permission flag is set at the address where C1 tracing is desired.

In this way, after writing a predetermined value of data to the bitmap memory 5 for all the addresses for which C1 tracing is desired, the multiplexer 43 is switched so that the output of the C1 detection circuit 3 and the bitmap memory 41 are -" After connecting the response input and setting the human map memory 41 to the reading state, debugging the actual machine is executed. Then, C1
Every time the detection circuit 3 detects a branch instruction executed by the actual device 1, the address data of the branch instruction is applied to the address input of the bitmap memory 41 via the multi-zorection controller 43. Therefore, the bitmap memory 41 is accessed by the same address l-' as the address h' of the program memory accessed in the actual machine, and its read output is applied to the other input of the ant gate 44 via the output terminal OUT. If the AND gate T1 is applied and the output of the bitmap memory 5 is "1" indicating C1 trace permission, the output of the AND gate becomes "P1" at the timing of the pulse T1. . This output is given as a 1' input to the overlay memory 5, and the overlay memory 5 temporarily stores the 01 detection circuit output signal c1 information at this time. The contents of this overlay memory 5 are sequentially recorded by the recording device 6 as described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a program analyzer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a more specific configuration of an area specifying circuit in the analyzer of FIG. 1. 1... Actual CPU1 2... Program analyzer, 3... C1 detection circuit, 4... Area specification circuit, 6... Recording device, 41... ...
Bitmap memory. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Tatsuo Ito Agent Patent attorney Tetsuya Ime

Claims (1)

[Claims] An instruction executed during program debugging of a device equipped with a processor and a program memory is analyzed, and if the instruction is a branch instruction, C1 information indicating the address of the branch instruction and whether a conditional branch has occurred due to the branch instruction. A program analyzer for creating and recording a program, the program analyzer comprising a bitmap memory storing a predetermined number of data in bits corresponding to an address space of the program memory and corresponding to a desired address to be analyzed. , when the program memory is accessed by the operation of the device, the bitmap memory is accessed by an address corresponding to the accessed program memory address, and the data of the predetermined value is read from the bitmap memory. A program analyzer @door characterized in that it records only the C1 information.