JPS59160249A - Program testing device - Google Patents

Abstract

PURPOSE:To execute easily a program test by collecting a C1 coverage index showing whether the following instruction or an instruction of a jump destination is designated or not by a branch instruction, when a program containing the branch instruction is executed. CONSTITUTION:A CPU18 clears an RAM17 through a multiplexer 12 and OR gates 15, 16. When a CPU1 executes a branch instruction, an instruction decoder 2 decodes and outputs it, sets an FF4 by a timing pulse of an AND gate 3, and stores an address of the branch instruction in an address register 7. The CPU1 outputs the following instruction or an address data of a jump destination. An output of the FF4 is provided to registers 8, 10 by said timing pulse, reads the register 7, and the register 10 stores the following instruction. As for a data of the register 8, the jump destination is instructed by an adding circuit 9, and said data is compared 11 with a data of the register 10, and inputted to a memory 171 and a memory 172 in case of coincidence and dissidence, respectively. In this way, a test of a program is executed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program testing device, and more particularly, to a program testing device that, when a program including a branch instruction is executed, tests whether or not the next instruction or jump destination indicated by the branch instruction has been executed. The present invention relates to a program testing device for such purposes.

BACKGROUND OF THE INVENTION Conventionally, in order to test whether a program on a computer can be executed normally, it has been necessary to debug the created program to find bugs. However, in order to perform such debugging,
It required a large computer, and it was not possible to easily test the program.

On the other hand, these days, to check the integrity of testing (or debugging) a program, a more efficient method is to check what parts of the program have not yet been executed, rather than how the program has been executed. The need to clarify this has arisen. Therefore, recently, coverage analysis has become known as a method for testing programs. In a program that includes multiple steps in coverage analysis, the ratio of the number of steps executed at least once is called the Cl jy coverage index. Distribute data to a data collection device such as a tape or floppy disk, and analyze the 1ft01 coverage index IAI!I+
There are ways to do this. Although this method can create C2 and C3 coverage indices with high rII after the C1 coverage index, it requires a long time for analysis due to badge processing and a large amount of data. In particular, there was a problem in that the *g status of debugging could not be checked in real time during debugging.

OBJECTS OF THE INVENTION Therefore, the main object of the present invention is to collect, when a program including at least a branch instruction is executed, a C1 coverage index indicating whether the next instruction or jump destination instruction is specified by the branch instruction. It is an object of the present invention to provide a program testing device that tests a program using

Structure and Effects of the Invention To summarize the invention, the present invention is a device for testing a program including a branch instruction, which decodes data when a central processing means executes a branch instruction and outputs the decoded data. The address data of the branch instruction output from the central processing means according to the branch instruction and the address data of the next instruction or jump destination address data specified by the branch instruction are stored, and the address data of the next instruction or jump destination is It is configured to discriminate whether or not the data indicates that the branch has proceeded to a predetermined branch destination, and to store a binary signal indicating whether or not the branch has proceeded to the predetermined branch destination based on the discrimination output.

Therefore, according to the present invention, C1, which indicates whether or not the central processing means that actually processes the program has proceeded to the next instruction or jump destination specified by the branch instruction,
Coverage metrics can be collected very easily.

Therefore, by determining the collected C1 coverage metrics, it is possible to more efficiently and objectively reveal which part of the branch instruction has not yet been executed.
It becomes possible to efficiently (develop) high-quality 70 grams.

The invention will be explained in more detail below along with embodiments shown in the drawings.

Description of examples FIG. 1 is a schematic block diagram of an embodiment of the present invention.

First, the configuration will be explained with reference to FIG. A CPU 1 serving as a central processing means actually executes a built-in program, and is connected to a data bus DB, an address bus AB, and a control bus C8.

5- An instruction decoder 2 is connected to the data bus DB.

The instruction decoder 2 detects a branch instruction by decoding fetch data output to the data bus DB when the CPU 1 executes a branch instruction included in a program. When data is decoded by the instruction decoder 2 based on the branch instruction, the decoded output is given to one input terminal of the AND gate 3.
A decode fetch timing pulse T1 is applied to the other input terminal of the ND gate 3 from a control circuit 21 mentioned above. The AND gate 3 flips the decoded output of the instruction decoder 2 in synchronization with this timing pulse T1.
It is applied to the set input terminal of knob 4 and address register 7. The Q output of the flip-flop 4 is applied to one input terminal of an AND gate 5, and the timing pulse T1 is applied to the other input terminal. Therefore, when the flip-flop 4 is set, the AND gate 5 provides a pulse synchronized with the timing pulse T1 to the registers 8 and 10, and also connects the reset input terminal of the flip-flop 6 to the reset input terminal of the flip-flop 4 via the delay circuit 6. It is applied to one input terminal of each of gates 13 and 14. Delay circuit 6 is IC
It is delayed by the P LJ cycle period. Therefore, the flip-flop 4 is set when the instruction decoder 2 detects a branch instruction, and then reset after the ICPLI cycle period for outputting the destination address of the branch instruction.

That is, the flip 70 knob 3 is set from the time a branch instruction is output until the address of the destination to which the branch is to be branched is output by the branch instruction.

A control circuit 21 is connected to the control bus CB. This control circuit 21 generates an operation code fetch timing pulse T1 for synchronizing the CPU 1, which actually executes a program, and the CPU 18, which tests this program. Also,
Address bus AB has address register 7 and register 1.
0 is connected. The address register 7 stores address data when the instruction decoder 2 detects a branch instruction, that is, when the CPU 1 executes the branch instruction. The address data stored in the address register 7 is stored in the register 8 at the subsequent stage. This register 8 is provided because it is necessary to empty the address register 7 for the next processing after address data is stored in the address register 7. The register 10 stores the address data of the destination specified by the branch instruction after the branch instruction is executed. The address data stored in register 8 is given to adder circuit 9. The addition circuit ff19 is for adding, to the address data of the branch instruction stored in the register 8, the difference between the address data and the jump destination address, for example, 3. The output of the adder circuit 9 is compared by a comparator circuit 11 with the jump destination address data stored in the register 1o. When the two match, the comparison circuit i'811 gives a high-level match signal to one input terminal of the ND gate 13, and inverts it with the inverter 21 and outputs it to the AND gate 1.
4 to one input terminal. The AND gate 13 outputs a pulse delayed by the delay circuit 6, that is, after the CPU 1 outputs the next destination address signal based on the branch instruction.
The match signal of the comparison circuit 11 is passed through the OR gate 15 to R
Give it to AM17. On the other hand, AND gate 14 provides a signal to RAM 17 via OR gate 16 when comparison circuit 11 does not output a match signal. The RAM 17 includes a storage area corresponding to the maximum address that the CPU 1 can specify. In other words, if CPU1 is 8 bits, RAM17 is 6 bits.
The storage area 171 on the left side stores a binary signal indicating whether or not the process has proceeded to the next step due to a branch instruction, and the storage area 172 on the right side stores a binary signal indicating whether the branch instruction has proceeded to the next step. A binary signal indicating whether or not the instruction has led to a jump destination step is stored.

This RAM 17 is addressed by address data from multiplexer 12. Multiplexer 12
is the address data stored in register 8 and the CPU
This is used to switch the address data output from 1B.

10-CP 0181. L It performs control for collecting the C1 coverage index, which is a feature of this invention, and provides a clear signal to the above-mentioned OR gates 15 and 16, as well as one input terminal of the OR gate 20 and one input terminal of the AND gate 19. Give a clear signal to the input terminal as well. This OR gate 2
0 is given a read command signal from the CPU 18. O
When the R gate 20 receives the CPU 18 side signal, the R gate 20 switches the multiplexer 12 to the CPU 18 side signal.
switch to the side address. Multiplexer 12 is CPU
When the address is switched to the address on the 18 side, the data stored in the RAM 17 is read out and the CPU 18 side is read out. FIG. 2 is a flow diagram showing an example of a program to be tested according to an embodiment of the present invention.

3 to 5 are flowcharts for explaining the specific operation of one embodiment of the present invention. In particular, FIG.
FIG. 4 is a flowchart for explaining the operation when the RAM 17 is initialized by the PU 18; FIG. 4 is a flowchart for explaining the operation for collecting the C1 coverage index into the RAM 17; FIG. FIG. 3 is a flowchart for explaining the operation of reading the 01 coverage index into the CPU 18. FIG.

Next, the operation shown in FIG. 1 will be explained with reference to FIGS. 2 to 5. First, the CPU 18 initializes the RAM 17 according to the flowchart shown in FIG. That is, C.P.
LllB outputs address data of 0 to its address bus. Then, a clear command signal is issued to switch the multiplexer 12 to the address side of the CPU 18. Also,
The clear command signal is sent to R via OR gates 15 and 16.
Given on AM17. The CPU 18 sequentially updates the addresses and sets O to each address in the RAM 17.

On the other hand, as shown in FIG. 4, the CPU 1 executes the operation of a built-in program, for example, as shown in FIG. 2. When a branch instruction is output from the CPU 1, the instruction decoder 2 detects the branch instruction and outputs detection (F1.A).
The ND gate 3 outputs a detection signal in synchronization with the timing pulse T1, sets the flip 70 knob 4, and causes the address register 7 to store address data when the CPU executes a branch instruction. After executing the branch instruction, the CPU 1 outputs address data representing the next instruction or jump destination. At this timing, the control circuit 21 outputs a timing pulse T1. Then, the AND gate 5 transfers the output of the flip-flop 4 to the register 8 in synchronization with the timing pulse T1.
and 10. Register 8 reads the address data stored in address register 7, and register 10
stores the next instruction output from the CPU 1 or the jump destination address data. Adder circuit 9 is register 8
For example, +3 is added to the address data of the branch instruction stored in the address data. This is because the branch instruction indicates a jump destination three addresses ahead, as shown in FIG.

Comparison circuit 11 compares the address data output from adder circuit 9 and the address data stored in register 10 to determine whether they match. If they match, a high level pulse signal is given to the A and ND gates 13. A pulse signal delayed by the I CPU cycle period is applied to the other input terminal of the AND gate 13 by the delay circuit 6. Therefore, AND gate 13 provides a write signal to RAM 17 via OR gate 15. Note that, at this time, the multiplexer 12 is switched to the CPUI address side. Therefore, RAM1 corresponding to the address data of the branch instruction stored in register 8
The storage area 171 address on the left side of 7 is specified, and a binary signal is written there. If the comparator circuit 11 determines that there is a mismatch between the address data from the adder circuit 9 and the address data stored in the register 10, it outputs a low level signal. This low level signal is inverted by the inverter 21 and applied to the AND gate 14. Therefore, when the address data stored in the register 10 is not the jump destination address but the next address, that is, 13-B shown in FIG. 2, the AND gate 14 indicates 2m! The signal is written to the right storage side 172 of the RAM 17.

This operation is repeated, and each time the CPU 1 executes a branch instruction, a binary signal indicating whether the branch destination is the next step or a jump destination step is stored in the RAM 17.
written to.

Next, referring to FIG. 5, the operation for reading out the binary signal stored in the RAM 17 will be explained.

First, the CPU 1B outputs a read command signal to switch the multiplexer 12 to the address side of the CPU 18. Therefore, from now on, RAM17 is addressed by the address from cpui8.

CPLllB sets address data to O and outputs a read command. A binary signal is read from address 0 of each of the storage area 171 on the left side and the storage area 172 on the right side of RAMI. cpu'+a sequentially updates the address and reads the binary value (fi number) written in address 0 or 5255 of RAM 17 and reads CPtJl.
Output to B data bus.

14- As described above, according to this embodiment, when the CPU 1 executes a branch instruction, the C1 coverage index indicating whether the branch destination is the next step or the jump destination step can be written to the RAM 17. can. Therefore, by determining the contents of the storage area 1iff171 on the RAM 170H side and the storage area 172 on the right side, it is possible to easily determine which destination has been executed by the branch instruction.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a flow diagram of an example of a program to be tested according to an embodiment of the present invention. Figures 3 to 5
The figure is a flowchart for explaining the specific operation of one embodiment of the present invention. In particular, the 353rd RA shown in the 2nd
FIG. 4 is a flowchart for explaining the operation when initially determining M, and FIG. 4 is a flowchart for explaining the operation for collecting the C1 coverage index written in the RAM.
FIG. 5 is a flow diagram illustrating the operation for reading the C1 coverage index written in the RAM. In the figure, 1 is a real l1lcPU, 2 is an instruction decoder,
3.5.13.14 is AND gate, 4 is flip 70
Tsubu, 7 is address register, 8.10 is register, 9
is an adder circuit, 11 is a comparison circuit, 12 is a multiplexer,
15.16 is OR gate, 17 is AND, 1B is CPU
, 21 indicates a control circuit. Patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Scope of Claim] A program test device for converging a C1 coverage index indicating whether or not the branch instruction is normally executed when the program is executed in a program including a plurality of branch instructions, comprising: a central processing means for outputting address data corresponding to the branch instruction and the next instruction specified by the branch instruction or address data of a jump destination when the program is executed; a decoder for decoding data output when the decoder decodes the branch instruction; address data of the branch instruction output from the central processing means and a destination to be jumped by the branch instruction; Atto 1
address data storage means for storing Nos. data; determining means for determining whether address data of a jump destination stored in the address data storage means matches address data indicating that the jump destination has proceeded to a predetermined branch destination; and a binary signal storage means for storing a binary signal representing whether or not a predetermined branch destination has been reached based on the output of the discrimination means.