JPS59158438A - Shift circuit - Google Patents

Abstract

PURPOSE:To keep the difference of delay with time between a parity bit and a data bit of an output data at the occurrence of parity to a small value by generating the parity bit at each byte of an output data. CONSTITUTION:A parity generating means 7 ORes exclusively paritity information of an output of a byte shift means 4 and an output of an exclusive OR means 6 and sets a parity bit in 8-bit to a data in 8-byte in the output of a data shift section 2. In this case, there are two methods to set the logical value of the data bit to 0 by the ineffective means 5 of the effectiveness of the parity information output from the byte shift means 4. As for the 1st method, the parity bit of output bytes 0-7 of the byte shift means 4 is used, and as for the 2nd method, the parity bit of 1-8 of the output bytes of the byte shift means 4 is used.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a shift circuit equipped with a parity bit generator.

(Prior art) Conventionally, in this type of shift circuit, there is no regular relationship between the bit array of input data and the bit array of output data extracted from an arbitrary bit position of the input data. Parity prediction for generating parity bits for output data could not be obtained.

For this reason, the circuit is duplicated and the parity bit is generated from the output of one side, so this type of shift circuit has the disadvantage that the output parity bit lags behind the input data by the time taken to generate the parity. there were.

(Object of the Invention) An object of the present invention is to shift data transferred via byte shift means for shifting input data and invalidation means for invalidating specific bits into adjacent bits in parity generation. Take exclusive OR for every 2 bytes,
By configuring a structure in which a parity pit is generated for each byte of output data using the output of the exclusive OR and the parity information of the output of the byte shift means, the relationship between the parity bit and data bit of the output data in parity generation is improved. An object of the present invention is to provide a shift circuit that reduces the difference in time delay between the two.

(Structure of the Invention) A shift circuit according to the present invention shifts an arbitrary bit position specified by a plurality of shift number specification bits included in input data consisting of a plurality of bytes in a prespecified direction, and shifts this bit position in a prespecified direction. This is an improved version of the system configured to extract output data with a smaller number of bytes than the number of bytes of human data.

The shift circuit according to the present invention is characterized in that it includes a parity generation section, and the parity generation section is constituted by a byte shift means, an invalidation means, an exclusive OR means, and a parity generation means. It is.

The byte shift means is designed to take in data that is 1 byte larger than the output data width from the input data in byte units including parity pits, using the byte shift number designation bits included in the plurality of shift number designation bits. .

The invalidation means includes input data that is shifted to an adjacent byte when a bit-by-bit shift is performed using the byte shift number designation bits included in the plurality of shift number designation bits;
or to invalidate any of the data bits of the input data that are not shifted into adjacent bytes.

The exclusive OR means selects two adjacent data transferred via the byte shift means and the invalidation means.
This is to perform exclusive OR for each byte.

The parity generation means is for generating a parity bit for each byte of output data from the parity information of the output of the exclusive OR means and the output of the byte shift means and K.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a shift circuit according to the present invention.

In the diagram, 1 is a shift number storage register, 2 is a data shift section, 3 is a parity generation section, 4 is a byte shift means, 5 is an invalidation means, 6 is an exclusive OR means, and 7 is a parity generation means. be.

The parity generation section 3 includes a byte shift means 4, an invalidation means 5, an exclusive OR means 6, and a parity generation means 7.

In FIG. 1, shift number storage register 1 is a 6-bit register that stores a 3-bit byte shift number and a 3-bit bit shift number, and indicates a shift value of 0 to 63 bits.

The data shift unit 2 is a shifter exclusively for left shifting, with an input of 16 bytes consisting of 128 data bits and an 8 byte output consisting of 64 data bits, and shifts the input data according to the specified number of shifts. It is.

If shift number storage register 1 indicates that the shift number is θ bits, bits O to 63 of the input data are shifted and output, indicating that the shift number is the maximum 63 bits. In one case, bits 63 to 126 of the input data are shifted and output.

The byte shift means 4 inputs (128 data bits +
16 bytes consisting of 16 variable bits) and the output is
This is a shifter exclusively for left shifting of 9 bytes consisting of 72 data bits + 9 parity bits, and performs byte-by-byte shifts including parity bits according to the specified number of byte shifts.

If shift number storage register 1 indicates that the number of byte shifts is 0, byte O to byte 8 of the input data are shifted and output, indicating that the number of bytes is 7, which is the maximum. In this case, bytes 7 to 15 of the input data are shifted and output.

The invalidating means 5 sets the data bits of the input data excluding the parity bit to a logical value of 0 according to the bit shift number.

In this embodiment, 9 bytes of input data obtained via the byte shift means 4 are invalidated, but 16 bytes of input data before entering the byte shift means f94 are invalidated. and the output is transferred to the byte shift means 4.
It may also be used as an input.

There are two ways to set the logical value of a data bit to 0 according to the number of bits.

In the method of t1, if the shift number storage register 1 indicates that the number of bits is O, the logical value of the data bits from bit 0 to bit 7 of the bit position within the byte is set in each byte of input data. Set to O.

If the number of bit shifts is 1,
In each byte of input data, if the logic value of the data bits of bits 1 to 7 in the bit position within the byte is set to 0, indicating that the number of bit shifts is the maximum of 7, each of the input data In the byte, the value of the data bit in the byte bit position bit 7 is set to the logical value O.

In the second method, if the shift number storage register 1 indicates that the number of bits is O, there are no data bits to be set to a logical value. but,
If the number of bit shifts is 1,
If the logical value of the data bit of bit 0 in the bit position within the byte is set to O in each byte of input data, indicating that the number of bits is 2, then the bit position within the byte is set in each byte of input data. The logic value of the data bits bit 0 and bit 1 of is set to 0.

If the number of bit shifts is 7, which is the maximum, the logical value of the data bits in bit positions bit 0 to bit 6 in each byte of the input data is set to O.

In this embodiment, the invalidating means 5 employs the +1 method.

The exclusive OR means 6 increases the exclusive OR for every two adjacent bytes of the 9 bytes of data bits of the input data obtained via the byte shift means 4 and the invalidation means 5. S Sends 8-bit output. V! The two adjacent bytes are byte 0 in the 9-byte data.
Tonokuite 1, byte 1 and byte 2, byte 2 and byte 3, byte 3 and byte 4, byte 4 and byte 5, byte 5 and byte 6, byte 6 and byte 7, and byte 7
and byte 8.

The parity generation means 7 takes the exclusive OR of the parity information output from the byte shift means 4 and the output of the exclusive OR means 6, and generates the 8-bit parity bit for the 8-byte data output from the data shift section 2. It takes .

When taking the exclusive OR of the output of the parity information from the byte shift means 4 and the output of the exclusive OR means 6, the validity of the parity information output from the byte shift means 4 is determined by the invalidation means 5. There are two ways to do this, depending on how to set the logical value of the data bit to zero.

When the above-mentioned method 1 is adopted as in the nullification means 5 in this embodiment, the parity pits of byte O to byte 7 of the output of the byte shift means 4 are used, and the above-mentioned second method is adopted. In this case, the parity bits of bytes 1 to 8 of the output of the byte shift means 4 are used.

FIG. 2 is a block diagram systematically depicting the circuit configuration of the byte shift means 4. As shown in FIG.

The byte shift means 4 includes nine shift elements 8, 1st to 9th.
The shift element array 8 includes shift elements 10 to 890. Each shift element 810 to 890 provides a 9-bit output to a 16-bit input, and can instruct a left shift of 0 bits to 7 bits by a shift number designation bit consisting of 3 bits.

In order to perform a byte-to-byte shift, the input data is sorted from bit 01 to bit 8 to bit 16 so that a 1-bit shift corresponds to a 1-byte shift on the input data in the shift elements 810 to 890 of 1 to 9.・・・・・・・・・
. . . in the order of 1st to 9th shift elements 810 to
890.

By shifting the data in the byte shift means 4, 9 bytes of data including 64 data bits to be output data are selected from 16 bytes of input data.

FIG. 3 is a block diagram systematically showing the circuit configuration of the invalidation means 50.

The invalidation means 5 in this embodiment is composed of a decoder 9 and a two-man power gate 10.

Decoder 9 receives 3 bits representing the number of bit shifts and outputs 8 bits as represented by output terminals a-h.

When the shift number storage register 1 indicates that the bit shift number is O, the logic values at output terminals a to h are set to zero.

If the number of bit shifts is 1,
The logic value at output terminal a is set to 1, and the logic value at output terminals b-h is set to O. If the bit shift number is 2, the logic value in child c-h is set to 0.

If the bit shift number indicates the maximum number of 7, the logic value at output terminals a to g is set to 1, and the logic value at output terminal 1 is set to O.

The signal on the output terminal a of the decoder 9 and the data bit whose in-byte bit position in each byte of the output of the byte shift means 4 is bit 0 are combined with the first AND game of the two-person gate array 10. A logical AND operation is performed using a two-person gate array 10.

Similarly to the above, an AND is also performed between the signal at the output terminal bh of the decoder 9 and the data bits of bits 1 to 7 of the bit position within the byte in each byte of the output of the byte shift means 4. When a bit shift is performed based on the bit shift number, the logical value of the data bits in each byte in the output data of the byte shift means 4 becomes O, except for the bits shifted to the adjacent byte.

For example, for pi)O, except for the bit shifted out from byte 0, the data bits of byte O have a logic value of 0, and the data bits of the adjacent byte 1 have a logic value of 0.

Therefore, by calculating the exclusive OR between the data bits of byte 0 and byte 1, it is possible to predict the change in the parity bit of the data of byte 0 due to the shift of the bit shift number.

FIG. 4 is a block diagram systematically showing the circuit configuration of the exclusive OR means 6 and the parity generating means 7.

The exclusive OR means 6 is constituted by a 16-manpower exclusive OR element array 11 having 16 man-power exclusive OR elements 1110 to 1180, numbered 1 to 08, and the parity generation means 7 is constituted by Two manual exclusive OR elements 1210-1
It is realized by the two-man exclusive OR element array 12 equipped with 280.

The exclusive OR means 7 outputs byte O of the output of the invalidation means 5.
and byte 1, byte 1 and byte 2, byte 2 and byte 3
Similarly, 2 up to byte 7 and byte 8 are
Exclusive OR of data bits for each byte is performed using 16 manual exclusive OR elements 1110 to 118, respectively.
Bytes 0 to 0 of the output of the byte shift means 4
It is output as a parity change prediction signal by bit shifting the data of byte 7.

The parity generation means 7 generates an exclusive OR of the parity change prediction signal from the exclusive OR means 6 and the parity bits of bytes 0 to 7 of the output of the byte shift means 4.
- O8's two exclusive OR elements 1210 to 1280 generate 8 parity bits for the 8 byte data output from the data shift section 2.

In the above embodiments, in order to clarify the operation of each means, each means was specifically explained using an individual circuit, but the invalidating means 5 is a byte shift means 4 and the number of data bits input for each element. Since they are the same, the output enable function that is generally provided in the components of the disabling means 5 and the output enable function that is also provided in the shift elements 810 to 880 of the first to tooth 8 are used. However, as a result, the byte shift means 4 and the invalidation means 5 can be integrated into hardware.

Similarly, the exclusive OR means 6 and the high IJT generating means 7 can be integrated into hardware.

From ToreK, the time delay of the signal in the parity generation unit 3 is only the time delay due to the byte shift function and the time delay due to the exclusive OR function, and the time delay due to the byte shift function in the data shift unit 2. and the time delay due to the bit shift function.

(Effects of the Invention) As explained above, the present invention performs an exclusive OR operation on the parity generation data transferred via the byte shift means and the invalidation means in parity generation for every two adjacent bytes. By using the exclusive OR output, the harness information of the output of the byte shift means, and the button, the parity bit of the output data in parity generation can be changed by Since the difference in time delay between data bits can be kept small, the shift circuit can be made faster without using high-speed elements, and as a result, increasing the speed of the shift circuit can be prevented from increasing costs. There is an effect that says it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a shift circuit according to the present invention. FIG. 2 is a block diagram showing an embodiment of the structure of the byte shift means of FIG. 1. FIG. 3 is a block diagram showing an example of the configuration of the invalidating means shown in FIG. 1. Fig. 4 is a block diagram showing an embodiment of a configuration in which the exclusive OR means of Fig. 1 and the high IJT generating means are combined. 1...shift) M storage register 2...data shift section 3+0. Parity generation unit 4...byte shift means 5...invalidation means 6...exclusive OR means 7...parity generation means 8...shift element play 9...decoder 10...2 Human power gate array 11...16 Human power exclusive OR element array 12...
Two-man-powered exclusive OR element array 101 to 108...A
ND gates 810-890...Shift elements 1110-1180...16 Manual exclusive OR element 1
210-1280...Two-man-powered exclusive OR element patent applicant Hisashi Inoro, patent attorney representing NEC Corporation

Claims (1)

[Claims] It is configured to shift in the specified direction by an arbitrary bit position specified by multiple shift number specification bits included in input data consisting of multiple bytes, and extract output data with a smaller number of bytes than the number of bytes of input data. In the shift circuit, a byte shift means for taking in from input data data that is one byte larger than the output data width in byte units including a sparity pit by the byte shift number designation bits included in the plurality of shift number designation bits. , when the byte shift number designation bit included in the plurality of shift number designation bits is used to perform bit-by-bit shifting, the input bits are shifted to adjacent bytes (2) or shifted to adjacent bytes. invalidating means for invalidating any of the data bits of the invalid input data; and exclusive means for every two adjacent bytes of data transferred via the byte shifting means and the invalidating means. Exclusive OR means for calculating a logical OR; and - Parity for generating a parity bit for each byte of output data based on parity information of the output of the exclusive OR means and the output of the byte shift means. 1. A shift circuit comprising a parity generation section comprising a generation means.