JPS6025613Y2 - Parity detection circuit - Google Patents
Parity detection circuitInfo
- Publication number
- JPS6025613Y2 JPS6025613Y2 JP10030679U JP10030679U JPS6025613Y2 JP S6025613 Y2 JPS6025613 Y2 JP S6025613Y2 JP 10030679 U JP10030679 U JP 10030679U JP 10030679 U JP10030679 U JP 10030679U JP S6025613 Y2 JPS6025613 Y2 JP S6025613Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- detection circuit
- parity detection
- bit
- parity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Detection And Correction Of Errors (AREA)
Description
【考案の詳細な説明】
本考案は、複数ビットの２進数に含まれる論理“１゛の
数が偶数か奇数かを検出するパリティ検出回路において
、当該回路を構成するトランジスタ数を少なくし、回路
面積の小形化を目的としたものである。[Detailed description of the invention] The present invention is a parity detection circuit that detects whether the number of logical 1's included in a multi-bit binary number is even or odd. The purpose is to reduce the area.
従来、パリティ検出回路は排他的論理和ツリーで構成さ
れｎビットを任意の２ビツトずつの組に分け、順番に各
組の排他的論理和を算出し出力の論理値の°１“ｔ、４
４０“により、データ中の“６１９′の数が奇数個か偶
数個かを検出する。Conventionally, a parity detection circuit is configured with an exclusive OR tree, which divides n bits into groups of arbitrary 2 bits, calculates the exclusive OR of each group in order, and calculates the output logic value °1"t, 4
40" to detect whether the number of "619's" in the data is an odd number or an even number.
本考案は、従来排他的論理和回路により構成していたパ
リティ検出回路を、インバータおよびスイッチの直列回
路とスイッチのみの回路との並列回路で構成される各ビ
ットの回路で構成したパリティ検出回路である。The present invention replaces the conventional parity detection circuit with an exclusive OR circuit by replacing it with a parity detection circuit consisting of a circuit for each bit consisting of a series circuit of an inverter and a switch, and a parallel circuit of a switch-only circuit. be.
以下、図面（８ビツトの場合とする。The following drawings are for 8 bits.
）により詳細に説明する。) will be explained in more detail.
第１図は一従来例を示し、ａは排他的論理和回路により
構成されたパリティ検出回路、ｂは１つの排他的論理和
回路をＮ
（ｃｈａｎｎｅｌ ） ＭＯ３回路により構成したもの
である。FIG. 1 shows a conventional example, in which a is a parity detection circuit constituted by an exclusive OR circuit, and b is one in which one exclusive OR circuit is constituted by an N (channel) MO3 circuit.
第２図ａは本考案の一実施例を示し、１〜８はインバー
タ、１１〜２６はスイッチで、各ビットの論理値によっ
て１′ならばスイッチ１１゜１３．１５，１７，１９，
２１，２３，２５を選択し、６４０ ｔｔならばスイッ
チ１２，１４，１６゜１８．２０，２２，２４を選択す
るものである。FIG. 2a shows an embodiment of the present invention, in which 1 to 8 are inverters, 11 to 26 are switches, and depending on the logic value of each bit, if it is 1', the switch 11°13.15, 17, 19,
21, 23, and 25 are selected, and if it is a 640 tt, switches 12, 14, 16°18.20, 22, and 24 are selected.
ｂはａをＮ （ｃｈａｎｎｅｌ） ＭＯ３回路で構成し
たもので１′〜８′はａの１〜８、ゲートｂＯ′〜ｂ７
′はａの１１．１３．１５．１７．１９．２１．２３．
２５に、ｂＯ′〜ｂ７’は１２，１４，１６゜１８．２
０，２２，２４にあたり、各ビットの論理値によってそ
れぞれｂｉ’、 ｂｉ’のいずれか一方が選択される。b is a configuration of a with N (channel) MO3 circuits, 1' to 8' are 1 to 8 of a, gates bO' to b7
' is 11.13.15.17.19.21.23 of a.
25, bO' to b7' are 12, 14, 16° 18.2
0, 22, and 24, one of bi' and bi' is selected depending on the logical value of each bit.
第２図ａにおいて８ビツト分の回路それぞれに入力され
るデータによって“４１２９ならばスイッチ１１，１３
，１５，１７，１９，２１．２３．２５を選択し、“０
゛ならばスイッチ１２．１４，１６，１８，２０，２２
，２４を選択し、最終段での出力が初段回路の入力側に
印加されている基準信号と合致していなければ各ビット
の回路に入力されたデータは偶数回反転されたことにな
り、すなわち論理４４１１９の数が偶数個であることを
検出する。In FIG. 2a, if the data input to each of the 8-bit circuits is "4129", the switches 11 and 13
, 15, 17, 19, 21.23.25 and “0
゛If so, switch 12.14, 16, 18, 20, 22
, 24, and if the output at the final stage does not match the reference signal applied to the input side of the first stage circuit, the data input to the circuit of each bit has been inverted an even number of times, that is, It is detected that the number of logic 44119 is an even number.
ｂはａをＮ （ｃｈａｎｎｅｌ ）ＭＯ３回路より構成
上たパリティ検出回路で、ゲー６０′〜６７′はスイッ
チ１１． １３． １５． １７．１９，２１，２３．
２５に、６０′〜６７′はスイッチ１２．１４，１６，
１８，２０，２２゜２４にそれぞれに対応し、１′〜８
′はａのインバータ１〜８に対応する。b is a parity detection circuit constructed from N (channel) MO3 circuits, and gates 60' to 67' are switches 11. 13. 15. 17.19,21,23.
25, 60' to 67' are switches 12, 14, 16,
18, 20, 22°24 respectively, 1' to 8
'corresponds to inverters 1 to 8 of a.
以上のように当該パリティ検出回路は、各ビットの回路
をインバータおよびスイッチの直列回路とスイッチのみ
の回路との並列回路で構成することにより、トランジス
タ数を減らし回路面積の小形化の目的を遠戚することが
できる。As described above, the parity detection circuit achieves the distant goal of reducing the number of transistors and reducing the circuit area by configuring each bit circuit with a series circuit of an inverter and a switch, and a parallel circuit of a switch-only circuit. can do.
従来パリティ検出回路は７個の排他的論理和回路で構成
され、この排他的論理和回路１個をＮ（ｃｈａｎｎｅｌ
） ＭＯ３回路で構成した場合に９個のトランジスタ
からなり、すなオ）ち従来パリティ検出回路は７×９で
６３個のトランジスタで構成される。A conventional parity detection circuit is composed of seven exclusive OR circuits, and one exclusive OR circuit is divided into N (channel
) When configured with an MO3 circuit, it consists of 9 transistors; that is, a conventional parity detection circuit consists of 7×9 and 63 transistors.
本考案の場合には、各ビットの回路が４個のトランジス
タからなり、すなわち本考案のパリティ検出回路は４×
８で３２個のトランジスタで従来回路の半数て構成でき
る。In the case of the present invention, the circuit for each bit consists of four transistors, that is, the parity detection circuit of the present invention consists of 4×
8 and 32 transistors, which is half of the conventional circuit.
また、ｂｉ′、ｂ１′への２つの信号がそれぞれ存在す
る場合、該回路の構成でいいがｂｉ′への信号だけの場
合はインバータ回路を付加しｂｉ′への信号をつくる必
要がある。Further, if there are two signals to bi' and b1', the configuration of the circuit is sufficient, but if there is only a signal to bi', it is necessary to add an inverter circuit to generate a signal to bi'.
この場合でも、各ビットの回路にインバータ回路を構成
する２個のトランジスタが加わり、６×８で４８個のト
ランジスタで構成され、従来の回路に比べて回路面積を
減少でき本考案の目的を遠戚でき、高信頼性も得られる
。Even in this case, two transistors constituting an inverter circuit are added to each bit circuit, resulting in a 6 x 8 grid consisting of 48 transistors, which reduces the circuit area compared to the conventional circuit, and goes beyond the purpose of the present invention. can be compared with other products, and high reliability can be obtained.
また、従来回路と当該パリティ検出回路の混成による回
路構成も可能である。Further, a circuit configuration in which a conventional circuit and the parity detection circuit are combined is also possible.
第１図は一従来例を示し、ａは排他的論理和回路で構成
したパリティ検出回路、ｂは１つの排他的論理和回路を
Ｎ （ｃｈａｎｎｅｌ） ＭＯ３回路により構成したも
のである。
第２図ａは本考案の一実施例を示し、１〜８はインバー
タ、１１〜２６はスイッチである。
ｂはａをＮ （ｃｈａｎｎｅｌ） ＭＯ３回路により構
成したパリティ検出回路で１′〜８′はａの１〜８．ｂ
Ｏ′〜ｂ７′はａの１１． １３． １５゜１７．１９
，２１，２３．２５に、ｂＯ′〜ｂ７′はａの１２，１
４，１６，１８，２０，２２．２４それぞれにあたる。FIG. 1 shows a conventional example, in which a is a parity detection circuit made up of exclusive OR circuits, and b is one exclusive OR circuit made up of N (channel) MO3 circuits. FIG. 2a shows an embodiment of the present invention, in which 1 to 8 are inverters and 11 to 26 are switches. b is a parity detection circuit constructed by N (channel) MO3 circuits, and 1' to 8' are 1 to 8 of a. b
O' to b7' are 11. of a. 13. 15°17.19
, 21, 23.25, bO' to b7' are 12,1 of a
4, 16, 18, 20, 22.24 respectively.
Claims (1)
数かを検出するパリティ検出回路において、インバータ
および第１のスイッチの直列回路と第２スイツチのみの
回路との並列回路で構成される各ビットの回路をｎ段直
列接続し、前記第１、 第２のスイッチを各ビットのデ
ータに応じて相捕的に開閉し、初段回路の入力側に基準
信号を印加し、最終段の出力が基準信号と合致している
か否かにより上記ｎビットの２進数のパリティを検出す
るパリティ検出回路。A parity detection circuit that detects whether the number of logic "1's" included in an n-bit binary number is even or odd is composed of a series circuit of an inverter and a first switch, and a parallel circuit of a circuit containing only a second switch. n stages of each bit circuit are connected in series, the first and second switches are opened and closed in a complementary manner according to the data of each bit, a reference signal is applied to the input side of the first stage circuit, and the final stage circuit is connected in series. A parity detection circuit that detects the parity of the n-bit binary number based on whether the output matches the reference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10030679U JPS6025613Y2 (en) | 1979-07-20 | 1979-07-20 | Parity detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10030679U JPS6025613Y2 (en) | 1979-07-20 | 1979-07-20 | Parity detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5619853U JPS5619853U (en) | 1981-02-21 |
| JPS6025613Y2 true JPS6025613Y2 (en) | 1985-08-01 |
Family
ID=29333039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10030679U Expired JPS6025613Y2 (en) | 1979-07-20 | 1979-07-20 | Parity detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025613Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4757504A (en) * | 1986-04-21 | 1988-07-12 | Texas Instruments Incorporated | Polyphase parity generator circuit |
| JP5936908B2 (en) * | 2011-05-20 | 2016-06-22 | 株式会社半導体エネルギー研究所 | Parity bit output circuit and parity check circuit |
-
1979
- 1979-07-20 JP JP10030679U patent/JPS6025613Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5619853U (en) | 1981-02-21 |
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