JPS61221822A - Carry selection adder - Google Patents

Abstract

PURPOSE:To increase the arithmetic speed by performing the second carry selecting operation within a group carry generator and/or a carry selector. CONSTITUTION:Each group carry generator is constituted so as to produce a group carry to be given based the two types of arithmetic results obtained by a minute adder belonging to a prescribed one of (n) pieces of group adders and the group carry given from a lower group adder. At the outset, each minute adder performs the addition of 4 bits. In other words, the additions are carried out simultaneously by the 1st and 2nd arithmetic parts SA1 and SA2 to obtain two types of sum. At the same time, each carry is produced and applied to arithmetic parts GX and GY respectively. While the results of arithmetic are given to an arithmetic part G31 for production of a group carry C31. Here a multiplexer MPX supplies the carry C31 and produces a group carry C47 since the operation is through with both G47(0) and G47(1). When the C47 is fixed, the candidate at one side is selected by the MPX as a carry selection signal. Then the sum of 64 bits is finally decided.

Description

[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a carry selection adder, in particular, a carry selection adder that divides two integers consisting of a plurality of digits into several digits, and performs a carry operation for each digit. The present invention relates to a carry selection adder that performs two types of calculations, one with and one without, and then selects the result of one of the calculations.

(Technical Background of the Invention) When adding two integers consisting of multiple digits, in order to improve the calculation speed, divide these two integers into several digits, perform calculations for each digit, and finally A method of composing each digit is often used. In this case, the operation for each digit is divided into two cases: with and without a carry to that digit.
A so-called carry selection adder (CS A: Car
ry 5electAdder).

FIG. 12 shows an example of C8A which has been commonly used in the past. The adder shown here is a carry selection adder that performs 64-bit binary addition, and will be referred to as C3A64 hereinafter. This C3A64 is composed of four group adders.
It consists of a DD 64 and four group carry generators that provide group carry to each group adder. ADD64 has 64 bits of 2
Given each digit A, B of two integers A and B, each digit S of their sum S. -63 is output as the calculation result. FIG. 13 shows the internal configuration of the ADD 64.

The ADD 64 is composed of four group adders, groups a to d, and each group adder is responsible for 16-bit addition. For example, the a-group adder is A.

0-15.

B 0-15 will be input and S 0-15 will be output.

Each group adder consists of C3A16, which has four minute adders, and four carry selectors, C8-, which provide selection signals to each minute adder.
1, C83, C87, and C811. 14th
・The figure shows the internal configuration of C3A16. C3A16 is α-
It consists of four sub-adders up to β, and each sub-adder is capable of adding 4 bits. For example, the α-minute adder is A.

0-3゜ B will be input and 5O-3 will be output.

Each minute adder has a first arithmetic unit SA1 and a second arithmetic unit SA2.
, and multiplexer MPX.

The first arithmetic unit SA1 is an arithmetic unit that performs addition of input 4-bit integers assuming that there is no carry from the lower digits, and the second arithmetic unit SA2 is an arithmetic unit that performs the addition of input 4-bit integers, assuming that there is no carry from the lower digits. This is an arithmetic unit that performs addition of input 4-bit integers, assuming that In this way, the results of the two operations are temporarily stored in the multiplexer MPX, and later one of the results of the operation is selected, and the sum of the 4-bit integers is output. This selection is made by the selection signal Ca~
Cδ. Further, SA1 is a carry C1, C! generated by the calculation section after the calculation is completed. ,C? Output 1°C0, S
A2 is the carry C3, which is generated by the calculation unit after the calculation is completed.
Output C, C11, and C15 as 0 and 8. For example, C3 represents the carry that occurs at the most significant digit, that is, the third bit, in the case where the operation is performed assuming that there is no carry from the lower digit of 80-30-3.

Now, referring again to FIG. 13, the carry selectors C8-1, C83, C87, and C8I1 will be explained. Each group adder has as inputs, in addition to predetermined bit inputs of the integers A and B, carry inputs C1a-C1d;
As an output, in addition to the predetermined bit output of the sum S, there is also a carry output C.
It has 0a-Cod. For example, in an a-group adder, the predetermined bit inputs of an integer are A and B. -15, the carry force C1a is a carry C-1 from the 11th digit, and the sum output is S. ,,15, and the carry output COa is C0, C7, C11, C15, C3, C, C11, C1.
It is.

The function of the carry selector for group a will be explained below. The carry selectors C8-1, C83, C87°C811 perform a predetermined operation using the carry input C1a and a part of the carry output COa, and send selection signals Ca to Cδ to the respective adders.
give. First, C8-1 is actually a no-operation logic circuit, and as shown in group a in Figure 13, the carry C-1 from the -1st digit is directly used as Ca for the α-minute adder. to multiplexer MPX.

C83 is a logic circuit as shown in FIG. 15, which inputs carry outputs C, C3 and carry C-1 from the -1st digit, and outputs a selection signal Cβ to the β-minute adder. Similarly, C87 and C8I1 are logic circuits as shown in FIGS. 16 and 17, respectively, and output a selector @C7°Ca to the γ-minute adder and the δ-minute adder. In this way, one group adder has four minute adders, but carry between minute adders is determined in advance by checking the presence or absence of carry for each adder.
These calculations are carried out in advance, and later processing is performed by selecting one of them using a selection signal.

Next, referring again to FIG. 12, carry processing between group adders will be explained. As mentioned above, C3A64 is ADD6
It consists of 4 and 4 group carry generators. The group carry generator for group a is Gxa.

It has three calculation units GYa and G15. Gxa, GYal, and the carry output CO8 from the ta group adder are input, and logical values Xa and Ya are generated based on a predetermined operation. The same applies to group b, group C, and group d. Arithmetic unit G15 in each group carry generator. G31. G47.
G63 inputs the X and Y generated in GX and GY of each group, respectively, and performs a predetermined calculation to obtain the group carry C1.
,,C31,C4□,C63 are generated. Logic circuits of GX and GYa are shown in FIGS. 18 and 19.

GXb, GYb, GXo, GYo, GXd.

GYd also has a similar circuit configuration, xb and Yb, respectively.

Generates Xo, Yo, xd, and Yd. G15°G31.
G47. The logic circuit of G63 is shown in FIGS. 20 to 23. In this way, each group adder outputs a carry output CO8~
Once COd is obtained, group carry C15 to each group adder
, C31, C47, and C63 are calculated, and 64-bit addition is finally performed.

The details of the above-mentioned arithmetic theory are omitted here because they are described on pages 82 to 85 of ``High-speed Computing Methods for Computers'' (authored by Ai H, Hang, published by Kindai Kagakusha).

(Problems in the Background Art) Now, consider the calculation time of C3A64 shown in FIG. 12.Here, the calculation processing time of the calculation units SA1 and SA2 shown in FIG. The calculation processing time of the selector C811 is t, and the calculation processing time of the GX shown in FIG. 12 is tX.

The calculation processing time of G31 is t, and the calculation processing time of G47 is t.
, the calculation processing time of G63 is t The calculation processing time of the multiplexer MPX shown in Fig. 4763/14 is t
shall be. Next, consider the process from when C8A shown in FIG. 12 performs addition of 64 bits of PX until the result of the operation is output. The 64-bit integer is distributed to 16 adders of 4 bits each. Here the first
The arithmetic unit SA1 and the second arithmetic unit SA2 perform addition simultaneously to obtain two sums and generate each carry.

Each carry is given to the calculation units GX and GY, and the result of the calculation is given to, for example, the calculation unit G47.

Here, a group carry C47 is generated, and based on this, for example, C811 generates a carry selection signal, the multiplexer MPX selects one of the operation results, and finally the 64-bit sum is determined.

Therefore, the time required until the calculation is finally completed is T. If E, then "OE""SA + tX + t47 + t11 + tHPX. Also, carry C6 in the final 64-bit operation
T is the time until 3 is determined. . Then, TOC=tSA+tx+t63. Kokote calculation unit GX, G47. Since C8I 1 has almost the same gate configuration, t′″”47=t11″t is used as T and Ω.Rewriting the equation of 0, OE T OE = j sA+ 3 j + j HPXT
Oc=tSA+t+iC3. Here, the calculation processing time of 1,163 is actually quite long. This is C811, 18th shown in Figure 17.
This can be easily predicted from the fact that the logic gates of circuits such as GXa shown in the figure and G47 shown in FIG. 22 are quite complex. Therefore, in the conventional C8A, it can be said that the calculation speed is much improved compared to the case where carry selection is not performed, but compared to the actual addition calculation time tSA, time is wasted considerably. Especially T. Since E includes a term of 3t compared to TOC, a considerable delay time occurs. For example, if we consider the d group, after the group carry C47 is generated,
This is because a procedure is performed in which a carry selection is made within the d group for the first time.

As described above, it is currently desired to further improve the calculation speed of the conventional C8A.

C. OBJECTS OF THE INVENTION] Therefore, it is an object of the present invention to provide a carry selection adder with further improved calculation speed.

[Summary of the invention]

The first feature of the present invention is that there are n divisional calculators that add some digits of two integers, and n divisional calculators that give group carries from lower divisional calculators to each of the divisional calculators. In a carry selection adder comprising a group carry generator of The first calculation unit performs an operation on the assumption that there is no carry from the lower digit, and the second operation unit performs the operation on the assumption that there is a carry from the lower digit. m minute adders, (2) two types of operation results performed by each of these minute adders, and a group carry from the lower part adder;
m carry selectors that select either the operation result of the first operation section or the operation result of the second operation section based on The group carry to be given is calculated based on the two operation results performed by the dividing sieve belonging to a predetermined division calculator among the division calculators and the group carry from the lower division calculator. a third arithmetic unit which performs a group carry generation operation on the assumption that the group carry from the lower part arithmetic unit is not carried; , a fourth arithmetic unit that performs a group carry generation operation assuming that the group carry from the lower part calculator has a carry, and a third arithmetic unit based on the group carry from the lower part calculator. A group carry selector is provided for selecting either the calculation result of the fourth performance nose section or the calculation result of the fourth performance nose section, thereby further improving the calculation speed.

The second feature of the present invention is that n group subtracters perform addition of some digits of two integers, and a group carry from a lower group subtracter is given to each group subdivider. In a carry selection adder comprising n group carry generators, each group subdivider is defined as (1) an adder that performs addition of a portion of the digits to be added; a first arithmetic unit that performs an operation on the assumption that there is no carry from the lower digit; a second arithmetic unit that performs the operation on the assumption that there is a carry from the lower digit; m full adders with (2) two types of operation results performed by each of these full adders, and a group carry from a lower group subtracter,
m carry selectors that select either the operation result of the first operation section or the operation result of the second operation section based on Generates the group carry to be given based on the two types of operation results performed by the full adder belonging to a predetermined group subtracter among the group subdividers and the group carry from the lower group subdivider. The carry selector is configured so that the carry selector is configured to perform a carry-over, and all or a part of the carry selector is provided with a third operation for calculating the first candidate to be selected on the assumption that the group carry from the lower group subtracter does not carry a carry. an arithmetic unit, a fourth arithmetic unit that calculates a second candidate to be selected assuming that the group carry from the lower group subtracter has a carry, and a group carry from the lower group subtracter; 1st based on
The present invention further improves the calculation speed by providing a candidate selector for selecting either the candidate or the second candidate.

[Embodiments of the invention]

The present invention will be described in detail below based on illustrated embodiments. 1st
The figure is a block diagram of C3A648, which is the first embodiment of the present invention. This C3A64S is a carry selection adder having both the first and second features of the present invention described above, and is capable of performing 64-bit addition. The features of the present invention will be explained below by comparing FIG. 1 showing the C3A64S with FIG. 12 showing the conventional device 1csA64. First, the 64-bit adder included in the C3A64S is an ADD64S, which has a different configuration from the conventional ADD64. This difference is based on the second feature of the invention, which will be explained in detail later. C3A64S and C
Another difference from the 3A64 is the configuration of the group carry generator. This is based on the first feature of the invention. Looking at the configuration of each group carry generator, the configurations for groups a and b are exactly the same, but the configurations for groups 0 and d are slightly different. For example, looking at group 0,
The arithmetic units Gxo and GYo are the same, but the C3A64S has arithmetic units G47 (0),
G47 (1) and multiplexer MPX are new components. Similarly for the d group, the arithmetic unit G6
3 (0), G63 (1), 3 of multiplexer MPX
is a new component. Arithmetic unit G47(0)
.

The logic circuit of G47(1) is shown in FIGS. 3 and 4.

G47(0) is an arithmetic unit that generates the value of group carry C4□ when group carry C31 is assumed to have no carry, that is, C47(0). The value of the group carry C under the assumption, that is, C
It is a calculation unit that generates. C and C are temporarily stored in the multiplexer MPX, and when C31 occurs, one of them is selected and becomes C4□. The same applies to the occurrence of group carry C63.

The logic circuits of the arithmetic units G63(0) and G63(1) are shown in FIGS. 5 and 6. In this embodiment, the carry selection described above is performed for the group carry generators of the 0 group and the d group, but the carry selection is performed for all the group carry generators of the groups a to d, or other combinations. The effects of the present invention can be obtained even if carry selection is performed for some group carry generators. However, since the final calculation time is dominated by the calculation speed of the slowest group subtracter, it may be meaningless to perform carry selection for a large number of group carry generators, so this embodiment is preferred. This can be said to be an example.

Next, the second feature of the present invention will be described while comparing the configuration of the ADD 64S with that of the ADD 64. A in Figure 2
The configuration of DD64S is shown. ADD64 shown in Figure 13
The difference is in the structure of the carry selector. The configuration for group a is exactly the same for both groups, but for group b and group 0, C81
C811S instead of 1, and C83, C8 in group d
7 and C811, C83S, C87S, and C811S are new components, respectively.

Here, the logic circuits of C83S, C87S, and C8118 are shown in FIGS. 7, 8, and 9. These are shown in Figures 15-1.
Compared to O83 to C811 shown in Fig. 7, the group carry from each lower group adder (this example is for the a group, so it is C-1. The ones for the b, 0, and d groups are: Before the value of 15-31.
, Ca, the first candidate for Cδ, and the second candidate for Cβ, C7°Cδ assuming that the group carry has a carry.
The difference is that candidates for and are calculated. The group carry will later be provided to multiplexer MPX to select one of the candidates. Note that FIG. 10 shows an example of the circuit configuration of the multiplexer MPX. INI is given the first candidate, IN2 is given the second candidate, and the group carry is set to 5E.
When given to LECT, one of the candidates will be output to OUT.

In this manner, in the carry selector marked with the letter S in FIG. 2, the calculation is completed before the value of the group carry is determined, so that the calculation speed is improved. The other carry selectors not marked with the letter S in FIG. 2 may also have such a function, but the final calculation time is dominated by the calculation speed of the slowest minute adder. Even if a large number of carry selectors are provided with this function, there may be cases where it is meaningless, so this embodiment can be said to be a preferred embodiment.

FIG. 11 shows a C3A648' which is a second embodiment of the present invention.
FIG. This C3A648' is a carry selection adder having only the second feature of the invention described above. That is, the configuration of the group carry generator is shown in FIG.
Exactly the same as 3A64, with ADD64 in the 64-bit adder.
The only difference is that S is adopted. The configuration of ADD64S is as described above.

Here, the calculation time of the first embodiment C3A64S will be considered. First, 4-bit addition is performed by each adder. That is, the first arithmetic unit SA1 and the second arithmetic unit SA2
The additions are performed simultaneously to obtain two sums and to generate each carry. Each carry is given to the calculation units GX and GY, and the result of the calculation is given to, for example, the calculation unit G31. Here, a group carry C31 occurs.

At this time, since the calculations of G47(0) and G47(1) have already been completed, multiplexer MPX inputs C31 and generates group carry C47. At this time, for example, in the C811S of the d group, the calculation for the two candidates for C10 has been completed, so when C4□ is determined, one candidate is selected as the carry selection signal by the multiplexer MPX, and finally the 64-bit The sum will be determined. Therefore, if the time until the calculation is finally completed is TIE, TIE = tSA + tX + t31 + tHPX
+″HPX+″HPX.

Furthermore, if the time taken until carry C63 is determined in the final 64-bit operation is Tlo, then 71C" tSA
+tX +t31+tHPX.

Similarly, considering the calculation time of the second embodiment C3A64S', the time until the calculation is finally completed is T2E.
Then, 72E””SA+”X +t47+tHPX +tHP
If the time it takes to determine the carry C in the final 64-bit operation is 2C, then T2C=tSA
+tx+t31+tHPx.

As mentioned above, if the calculation processing time of the calculation unit consisting of almost the same gate configuration is t, and each equation is rewritten as tX `` t31 = t47 = '', then T IE = j sA + 2 j + 3 tHPXT
IC'= j SA + 2 j + t HPXT
2E ” j s^+ 2 j + 2 j Hpx
T −t + 2 t + t, Px2CSA. In the conventional device, as described above, "OE-SA+3t+tHPxTOC=j3A+t+t: a3.

Since the computation time tHPX is generally much shorter than t and t63, it can be seen that the final computation completion time can be considerably shortened.

Here, we will actually perform a circuit simulation and examine how much the calculation speed can be improved. The simulation was performed using the logic circuit simulator 5PICE, and each logic gate was composed of 0MO8 having an n-channel transistor with a channel length of 1.2 μm and an n-channel transistor with a channel length of 165 μm. The additional capacitance and other opening operating conditions were all the same. Figures 24 to 28 show the tS obtained as a result of this simulation.
A't31' tll, t63. A graph for determining tHPX is shown. In each figure, the solid line graph indicates the input signal of each logic circuit, and the broken line graph indicates the output signal of each logic circuit. Therefore, the deviation in the horizontal axis direction of both graphs becomes the calculation processing time of the logic circuit. From these graphs, j 3
^'= 4, 60 n5ec, i 31=1, 76
nsec, t11=t47=tx-2,77nsec
.

t −4, 28 nsec, t = 0. 7
6nsec and 63 HPX round.

When calculating by putting these 8 values into the above formula, (1)
In C3A64, TOE-13, 67n5ec.

TOC = 11, 65 n5ec1 (2) For C3A64S, T1E = 11.41ns
ec, TIC=9, 89 n5ec.

(3) In C3A64S', T2. -11.66n
sec, T2C=9, 89 n5ec. Thus, the first embodiment C3A64S.

Second embodiment C3A64S' Both conventional device C3A6
The calculation speed is improved compared to 4.

(Effects of the Invention) As described above, according to the present invention, in the carry selection adder, a carry selection operation is further performed in the group carry generator and/or the carry selector, so that the calculation speed is further increased. can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the C3A648, which is the first embodiment of the present invention, FIG. 2 is a block diagram of the 64-bit adder ADD64S, which is a part of the components of the C3A64S, and FIGS. 3 to 6 are The logic circuit diagrams in the group carry generator, which are part of the components of the C3A64S, and FIGS. 7 to 9 are ADD6.
A logic circuit diagram of a carry selector which is a part of the 4S component, Figure 10 is a multiplexer MP used in C3A64S.
Logic circuit diagram of A block diagram of the 64-bit adder ADD64, which is a part of it, is shown in FIG.
16 is a block diagram, FIGS. 15 to 17 are logic circuit diagrams of a carry selector which is a part of the components of the ADD 64, and FIG.
Figures 23 to 23 are logic circuit diagrams in the group carry generator, which are some of the components of C3A64, and Figures 24 to 28
The figure is a graph showing the results of simulation using a logic circuit simulator. C3A64. C3A64S, C3A64S'...Carry selection adder, ADD64. ADD64S...64-bit adder, GX, GY, G15. G31°G47. G
47CO), G47(1), G63゜G63(0), G
63(1)... Each arithmetic unit forming the group carry generator, 03A16... 16-bit adder forming the group subtracter, C8-1, C83, C838, C87, C87S,
C811, C3118...Carry selector, MPX...
・Multiplexer, SA1. SA2...4-bit adder, A, B...integer to be added, S...sum obtained by addition, C...carry. Applicant's agent Kiyoshi Inomata Figure 3 Figure 4 Figure 5 Figure 6 Figure 24 interval (π, 5ec) Figure 25 Time (usec) Figure 26 Time (π5ec) Figure 27 B revision 1 %'l (πsec)

Claims (1)

[Claims] 1. An adder for adding two integers each consisting of a plurality of digits, comprising n group adders for adding some digits of the two integers; n group carry generators providing group carries from lower group adders to group adders;
Each of the group adders is an adder that (1) performs addition of some of the digits of the two integers, and there is no carry from the lower digits. a first calculation unit that performs calculations assuming that ) The calculation result of the first calculation unit or the calculation result of the second calculation unit based on the two calculation results performed by the fractional adder and the group carry from the lower group adder. and m carry selectors for selecting one of the group carry generators, and the group carry generator is configured to perform the operation by a fractional adder belonging to a predetermined group adder among the n group adders. Generates a group carry to be given based on the two operation results and the group carry from the lower group adder, and all or a part of the group carry generator
a third arithmetic unit that performs a group carry generation operation assuming that the group carry from the lower group adder has no carry; and a third operation unit that performs a group carry generation operation assuming that the group carry from the lower group adder has a carry; a fourth arithmetic unit that performs a carry generation operation; and selecting either the arithmetic result of the third arithmetic unit or the arithmetic result of the fourth arithmetic unit based on the group carry from the lower group adder; A carry select adder comprising a group carry selector. 2. An adder that adds two integers each consisting of a plurality of digits, including n group adders that add some digits of the two integers, and a lower order adder to each of the group adders. n group carry generators providing group carries from the group adders;
Each of the group adders is an adder that (1) performs addition of some of the digits of the two integers, and there is no carry from the lower digits. a first calculation unit that performs calculations assuming that ) The calculation result of the first calculation unit or the calculation result of the second calculation unit based on the two calculation results performed by the fractional adder and the group carry from the lower group adder. and m carry selectors for selecting one of the group carry generators, and the group carry generator is configured to perform the operation by a fractional adder belonging to a predetermined group adder among the n group adders. A group carry to be given is generated based on the two operation results and a group carry from the lower group adder, and all or part of the carry selector is based on the group carry from the lower group adder. a third arithmetic unit that calculates the first candidate to be selected on the assumption that the group carry is no carry; a fourth calculation unit that calculates a second candidate by calculation; and a candidate selector that selects either the first candidate or the second candidate based on the group carry from the lower group adder. A carry selection adder comprising: