JP2561639B2 - Arithmetic logic unit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a logical operation circuit, for example,
A technology that is particularly effective when used in an arithmetic logic operation unit that has the addition function for operation data that is a BCD (Binary Coded Decimal) code and that uses the conditional addition (Conditional Sum) method Is.

[Conventional technology]

There is an arithmetic logic operation unit having an addition / subtraction function for operation data that is BCD coded every 4 bits. Moreover, there is a conditional addition method as one method for accelerating the arithmetic processing of such an arithmetic logic operation unit.

For the conditional addition method, for example, June 20, 1972
It is described on pages 98 to 108 of "Electronic Computer Course No. 4: System Design of Electronic Computers" published by Nisshin Co., Ltd.

[Problems to be Solved by the Invention]

FIG. 4 shows a partial block diagram of an arithmetic logic operation unit ALU developed by the inventors of the present invention prior to the present invention. The arithmetic logic operation unit ALU in the figure adopts the conditional addition method described above, and has an addition / subtraction function for BCD-coded operation data.

In FIG. 4, the operation data input to the arithmetic logical operation unit ALU has a length of 8 bytes, that is, 64 bits, and is divided into groups of 4 bits. The operation data is a BCD code in which each group has one digit when the arithmetic logic operation unit ALU is set to a predetermined operation mode. The arithmetic logic operation unit ALU includes 16 unit addition circuits provided corresponding to each group of operation data.

Each unit addition circuit of the arithmetic and logic unit ALU has a fourth
Corresponding internal operation data, as illustrated in the figure
Function generating circuits AFG for forming carry propagation functions p0 to p3 and carry generating functions g0 to g3 based on x0 to x3 and y0 to y3, respectively. These carry propagation function and carry generation function have a half adder circuit HA composed of four exclusive OR circuits and an input carry signal of which is a logic "1" or a logic "0".
Generators CGA and CGB, group carry propagator P03 and group carry generator G03
Is supplied to the group function generating circuit GAFG forming the. Of these, the function generation circuit AFG, the half addition circuit HA, and the carry generation circuit CGA form the first addition circuit together with the full addition circuit FAA composed of four exclusive OR circuits. In addition, the function generator AFG, half adder HA, and carry generator CGB
Is a full adder circuit which is also composed of four exclusive OR circuits.
A second adder circuit is constructed with FAB. Full adder circuit F
The output signals of AA and FAB are selectively validated in the selection circuit SEL6 in accordance with the carry signal C04 output from the group carry generation circuit GCG1 and become internal output data s0 to s3.

That is, in this arithmetic logic operation unit ALU, two sets of adder circuits are provided, so that the operation data X0 to X3 and Y0
The addition process for ~ Y3 is performed regardless of the level of the input carry signal, that is, the output carry signal C04 of the preceding group, and when the carry signal CO4 is determined, the calculation result corresponding to that level is selected. As a result, carry operation processing by the group carry generation circuit GCG1 and the like and addition processing by the adder circuit can be performed in parallel, so that the operation processing of the arithmetic logic operation unit ALU is speeded up.

On the other hand, the group carry propagation function P03 and the group carry generation function G03 formed by the group function generation circuit GAFG are supplied to the corresponding group carry generation circuit GCG1. The arithmetic and logic unit ALU consists of four group carry generation circuits GCG1 to GCG4.
And one unit carry generation circuit UCG. The group carry generation circuits GCG1 to GCG4 include group carry propagation functions P03 to P15 to P051 to P63 and group carry generation functions G03 to G15 to G51 to G63 from the group function generation circuit GAFG of the corresponding four sets of unit addition circuits. Are supplied respectively.
The group carry generation circuits GCG1 to GCG4 form output carry signals CO4 to C48 of each group based on these group carry propagation function and group carry generation function, and supply them to the group carry generation circuit of the next stage. At the same time, the unit carry propagation functions UP15 to UP63 and the unit carry generation functions UG15 to UG63 are respectively formed and supplied to the unit carry generation circuit UCG. The unit carry generation circuit UCG is based on the above unit carry propagation function and unit carry generation function
Form the output carry signal Cout as U.

In the above function generation circuit AFG, group function generation circuit GAFG, and unit carry generation circuit UCG, the carry propagation function and carry generation function, group carry propagation function and group carry generation function, and unit carry propagation function and unit carry generation function are well known. Like 1 each
It is formed via a two-stage or two-stage logic gate circuit. As a result, the carry generation unit of the arithmetic and logic unit ALU is of a so-called carry look ahead system, and each output carry signal is formed in a relatively short time even though the operation data is 64 bits long. Becomes

However, the inventors of the present application have found that the arithmetic logic operation unit ALU has the following problems. That is, the arithmetic logic operation unit ALU has a function of performing a decimal addition operation without changing the form of the addition circuit when the operation data X0 to X3 and Y0 to Y3 are BCD codes as described above. . Therefore, in the preceding stage of the function generation circuit AFG, a plus 6 circuit +6 for adding 6 to one of the operation data Y0 to Y3 and an arithmetic logic operation unit ALU
A selection circuit SEL2 is provided for selectively transmitting the output signal of the plus 6 circuit +6 as the internal operation data y0 to y3 when the operation mode is set to the decimal mode and the internal control signal bcd is set to the high level. Further, in the subsequent stage of the selection circuit SEL6, the operation result of the unit addition circuit, that is, the internal output data s0
The output of the minus 6 circuit-6 when the internal control signal bcd is set to the high level and the output carry signal Cout of the corresponding group is set to the logic "0". A selection circuit SEL7 for selectively transmitting signals as output data S0 to S3 is provided.

Here, the output carry signal C04 is formed by the corresponding group carry generation circuit GCG1 as described above, and its level is determined by the output carry signals C16, C32 and C48 of the preceding group carry generation circuits GCG2 to GCG4. Will be confirmed after being done. Therefore, the carry calculation process for forming the output carry signal C04 and the 6 subtraction process by the minus 6 circuit-6 form a critical path of the arithmetic logic operation unit ALU, and the speedup thereof is limited.

It is an object of the present invention to provide a logical operation circuit that speeds up arithmetic processing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
In a logical operation circuit that has a function of adding to BCD-encoded operation data and uses a conditional addition method, minus 6 circuits are provided in the respective stages after the addition circuits provided in two sets, and the output signals of these minus 6 circuits are handled. A group carry propagating function output from the group function generating circuit and a selecting circuit for selectively transmitting according to the group carry generating function are provided.

[Work]

According to the above-described means, the addition process for the operation data and the 6 subtraction process for the operation result can be performed in parallel with the carry operation process by the carry generation unit. Therefore, the arithmetic processing of such a logical operation circuit can be speeded up, and the processing capability of the digital processing device including the logical operation circuit can be improved.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of an arithmetic logic operation unit ALU to which the present invention is applied. 2 and 3, the function generating circuit AFG, carry generating circuits CGA and CGB of the arithmetic and logic unit ALU of FIG. 1 are shown in FIG.
Half addition circuit HA, full addition circuit FAA and FAB, minus 6 circuit-6A
And -6B and a circuit diagram of one embodiment of the group function generating circuit GAFG are shown. An outline of the configuration and operation of the arithmetic logic operation unit ALU of this embodiment will be described with reference to these figures.

Although not particularly limited, the arithmetic logic operation unit ALU of this embodiment is built in a one-chip microcomputer and includes 16 sets of unit adder circuits provided corresponding to 4-bit operation data, as described later. . In Figure 1,
Of these, one set of unit addition circuits provided corresponding to the highest-order operation data X0 to X3 and Y0 to Y3 is exemplarily shown. Since the following description will be given by taking this unit addition circuit as an example, analogy about other unit addition circuits provided corresponding to the operation data X4 to X63 and Y4 to Y63. The circuit elements forming each block in FIG. 1 are not particularly limited together with a unit adding circuit (not shown) of the arithmetic and logic operation unit ALU and a circuit element forming a block (not shown) of the microcomputer. It is formed on a single semiconductor substrate.

The arithmetic logical operation unit ALU of this embodiment performs various arithmetic processing based on binary logical addition in units of 64 bits, although not particularly limited. Arithmetic logic unit
The ALU receives calculation data X0 to X63 (first calculation data) and Y0 to Y63 (second calculation data) via two sets of internal buses (not shown).
Data) and an input carry signal Cin from a carry register or the like (not shown). In this embodiment, each unit adder circuit of the arithmetic and logic unit ALU has a conditional adder method and has two sets of adder circuits whose output data are selectively made effective according to the output carry signals of the corresponding group. . In addition, in a predetermined operation mode, it has a function of performing decimal addition / subtraction processing on operation data which is BCD coded every 4 bits. further,
The arithmetic logic operation unit ALU includes group carry generation circuits GCG1 to GCG4 provided corresponding to four sets of unit addition circuits, and a unit carry generation circuit UCG provided corresponding to all unit addition circuits. The group carry generating circuit and the unit carry generating circuit are of a carry look ahead type, although not particularly limited thereto. as a result,
In the arithmetic logic operation unit ALU of this embodiment, in addition to speeding up the addition processing of each unit addition circuit, addition processing by these addition circuits and carry generation processing by the group carry generation circuit and unit carry generation circuit are performed. Are performed in parallel, the arithmetic processing is speeded up and the time required to form the output carry signal Cout is shortened.

In FIG. 1, the operation data X0 to X3 divided into groups of 4 bits are supplied to the complement generating circuit COM of the corresponding unit adder circuit of the arithmetic logic operation unit ALU, and the selection circuit SEL1 (not shown). The first selection circuit) is supplied to one input terminal. Similarly, the operation data Y0 to Y3 divided into 4 bits each is not particularly limited,
It is supplied to the plus 6 circuit +6 of the corresponding unit addition circuit of the arithmetic logic operation unit ALU, and also the selection circuit SEL2
It is supplied to one input terminal of the (second selection circuit). The input carry signal Cin is supplied to the carry input terminals of the group carry generation circuit GCG4 and the unit carry generation circuit UCG, as described later.

The complement generating circuit COM selectively forms the two's complement or the ten's complement based on the operation data X0 to X3. The output signal of the complement generation circuit COM is supplied to the other input terminal of the selection circuit SEL1. Although not particularly limited, the selection circuit SEL1 is supplied with the internal control signal com from an arithmetic control unit (not shown). The internal control signal com is not particularly limited, but is selectively set to a high level when the subtraction process is performed in the arithmetic logic operation unit ALU.

When the internal control signal com is at a low level, the selection circuit SEL1 selects the operation data X0 to X3 and transmits it to the function generation circuit AFG as internal operation data x0 to x3 (first internal operation data). As a result, the operation data X0 to X3 are transmitted to the adder circuit as they are, and the addition process using the data as the addend is performed. On the other hand, the selection circuit SEL1 selects the output signal of the complement generation circuit COM when the internal control signal com is at the high level, and transmits it to the function generation circuit AFG as the internal operation data x0 to x3. As a result, the complement of the operation data X0 to X3 is transmitted to the adder circuit, and the subtraction process using this as a subtraction is performed.

The plus 6 circuit +6 adds 6 to the operation data Y0 to Y3, although not particularly limited thereto. The output signal of the plus 6 circuit +6 is supplied to the other input terminal of the selection circuit SEL2. Although not particularly limited, the selection circuit SEL2 is supplied with the internal control signal bcd from an arithmetic control unit (not shown). The internal control signal bcd is not particularly limited, but is selectively set to a high level when the arithmetic data X0 to X3 and Y0 to Y3 are both BCD codes and decimal addition processing is performed in the arithmetic logic operation unit ALU. .

When the internal control signal bcd is set to the low level, the selection circuit SEL2 selects the operation data Y0 to Y3 and transmits it as the internal operation data y0 to y3 (second internal operation data) to the function generating circuit AFG. As a result, the operation data Y0 to Y3 are transmitted to the adder circuit as they are, and a binary addition / subtraction process is performed with the calculated data Y0 to Y3 as the augend or the subtraction. On the other hand, the selection circuit SEL2
When the internal control signal bcd is set to high level,
The output signal of the plus 6 circuit +6 is selected and transmitted to the function generating circuit AFG as the internal operation data y0 to y3. As a result, the result of adding 6 to the operation data Y0 to Y3 is transmitted to the adder circuit, and the decimal addition / subtraction process is performed with the result as the augend or the augend.

The function generating circuit AFG is not particularly limited, but as shown in FIG. 2, 44 OR gate circuits and AND gate circuits for receiving the internal operation data y0 to y3 corresponding to the internal operation data x0 to x3, respectively. Including. The output signals of the respective OR gate circuits are carry propagation functions p0 to p3, and the output signals of the respective AND gate circuits are carry generation functions g0 to g3. As a result, carry propagators p0 to p3 are formed under the logical conditions of p0 = x0 + y0 p1 = x1 + y1 p2 = x2 + y2 p3 = x3 + y3, respectively, and carry generating functions g0 to g3.
Are respectively formed under the logical conditions of g0 = x0.y0 g1 = x1.y1 g2 = x2.y2 g3 = x3.y3.

Carry propagators p0 to p3 and carry generator functions g0 to g3
Is supplied to the half adder circuit HA, carry generation circuits CGA (first carry generation circuit) and CGB (second carry generation circuit), and group function generation circuit GAFG.

Although not particularly limited, the half adder circuit HA includes, as shown in FIG. 2, four exclusive OR circuits for receiving the carry propagation functions p0 to p3 and the corresponding carry generation functions g0 to g3, respectively. The output signals of these exclusive OR circuits are half addition data sh0 to sh3, respectively. As a result, the half-added data sh0 to sh3 are sh0 = p0g0 = (x0 + y0) (x0 ・ y0) = x0y0 sh1 = p1g1 = (x1 + y1) (x1 ・ y1) = x1y1 sh2 = p2g2 = (x2 + y2) (x2)・ Y2) = x2y2 sh3 = p3g3 = (x3 + y3) (x3 · y3) = x3y3. These half addition data sh0 to sh3 are nothing but the result of inputting the internal operation data x0 to x3 and y0 to y3 directly to the corresponding exclusive OR circuits. That is, the arithmetic logic unit ALU of this embodiment is
Then, as will be apparent from the description below, the half adder circuit HA
And carry generation circuit CGA and CGB and group function generation circuit
The output signal of the function generator AFG provided in the first stage, that is, carry propagation functions p0 to p3
And the carry generation functions g0 to g3 are used to simplify the circuit configuration. The half addition data sh0 to sh3 are supplied as one input signal of the full addition circuit FAA (first full addition circuit) and FAB (second full addition circuit).

Next, the carry generation circuit CGA is not particularly limited, but as shown in FIG. 2, carry propagation functions p1 to p3
And a plurality of AND gate circuits and OR gate circuits that receive the carry generation functions g1 to g3 in a predetermined combination.
The carry input terminal c of the carry generation circuit CGA is coupled to the power supply voltage of the circuit. As a result, the carry signal input to carry generation circuit CGA is fixed at logic "1". As is apparent from FIG. 2, the carry generation circuit
The carry signals ca0 to ca3 output from the CGA are ca0 = g1 + p1 · g2 + p1 · p2 · g3 + p1 · p2 · p3 ca1 = g2 · p2 · g3 + p2 · p3 ca2 = g3 + p2 · g3 ca3 = c = 1 and corresponding This is nothing but the carry signal for full addition of each bit when the input carry signal is set to logic "1".
These carry signals ca0 to ca3 are supplied as the other input signals of full adder FAA.

Similarly, the carry generation circuit CGB is not particularly limited, but as shown in FIG. 2, carry propagation functions p0 to p3.
And a plurality of AND gate circuits and OR gate circuits that receive the carry generation functions g0 to g3 in a predetermined combination.
Carry input terminal c of carry generating circuit CGB is coupled to the ground potential of the circuit. As a result, the carry signal input to carry generation circuit CGB is fixed at logic "0". As is apparent from FIG. 2, the carry generation circuit
The carry signals cb0 to cb3 output from the CGB are cb0 = g1 + p1 · g2 + p1 · p2 · p3 cb1 = g2 + p2 · g3 cb2 = g3 cb3 = c = 0, and the corresponding input carry signal is a logical “0”. This is nothing but the carry signal for full addition of each bit.
These carry signals cb0 to cb3 are supplied as the other input signals of full adder FAB.

The group function generating circuit GAFG is not particularly limited, but as shown in FIG. 3, a plurality of AND gate circuits and OR gate circuits that receive the carry propagation functions p0 to p3 and the carry generating functions g0 to g3 in a predetermined combination are provided. Including. As is apparent from FIG. 3, the output signal of the group function generating circuit GAFG, that is, the group carry propagation function P03 and the group carry generation function G
03 is formed under the predetermined logical condition of P03 = p0 · p1 · p2 · p3 G03 = g0 + p0 · g1 + p0 · p1 · g2 + p0 · p1 · p2 · g3.

The full addition circuit FAA is not particularly limited, but as shown in FIG. 2, the half addition data sh0 to sh3 output from the half addition circuit HA and the corresponding carry signal ca0 output from the carry generation circuit CGA. Receive ca3 respectively 4
Including exclusive OR circuits. The output signals of these exclusive OR circuits are internal addition data sa0 to sa3, respectively. As a result, the output signal of the full adder FAA, that is, the internal addition data sa0 to sa3 becomes sa0 = sh0ca0 sa1 = sh1ca1 sa2 = sh2ca2 sa3 = sh3ca3, respectively, and when the input carry signal c is logic "1". It is nothing but the result of bit addition. That is, in this embodiment, the full adder circuit FAA constitutes the first adder circuit together with the function generating circuit AFG, the half adder circuit HA and the carry generating circuit CGA. The output signal of the first addition circuit, that is, the internal addition data sa0 to sa3 is supplied to the minus 6 circuit-6A (first minus 6 circuit), and one input of the selection circuit SEL3 (third selection circuit). Supplied to the terminal.

Similarly, the full addition circuit FAB is not particularly limited, but as shown in FIG. 2, the half addition data sh0 to sh3 output from the half addition circuit HA and the corresponding half output data sh0 to sh3 output from the carry generation circuit CGB. It includes four exclusive OR circuits for receiving carry signals cb0 to cb3, respectively. The output signals of these exclusive OR circuits are the internal addition data sb0
~ Sb3 As a result, the output signal of the full adder circuit FAB, that is, the internal addition data sb0 to sb3 becomes sb0 = sh0cb0 sb1 = sh1cb1 sb2 = sh2cb2 sb3 = sh3cb3, respectively, and when the input carry signal c is logic "0". It is nothing but the result of bit addition. That is, in this embodiment, the full adder circuit FAB constitutes the second adder circuit together with the function generating circuit AFG, the half adder circuit HA and the carry generating circuit CGB. The output signal of the second addition circuit, that is, the internal addition data sb0 to sb3 is supplied to the minus 6 circuit-6B (second minus 6 circuit), and one input of the selection circuit SEL4 (fourth selection circuit). Supplied to the terminal.

The minus 6 circuit-6A is not particularly limited, but as shown in FIG. 2, an AND gate circuit that receives the internal addition data sa0 to sa2 output from the full addition circuit FAA in a predetermined combination, an exclusive OR. Circuit and inverter circuit. The output signal of the AND gate circuit is the internal subtraction data ma0, and the output signal of the exclusive OR circuit is the internal subtraction data ma1. The output signal of the inverter circuit is the internal subtraction data ma2. The internal addition data sa3 is directly used as the internal subtraction data ma3. As a result, the internal subtraction data ma0 to ma3 are ma0 = sa0.sa1.sa2 ma1 = sa1sa2 ma2 = .upsilon.ma3 = sa3, and each satisfy the logical condition as a minus 6 circuit. These internal subtraction data ma0 to ma3
Is supplied to the other input terminal of the selection circuit SEL3.

Similarly, the minus 6 circuit-6B is not particularly limited, but as shown in FIG. 2, an AND gate circuit that receives the internal addition data sb0 to sb2 output from the full addition circuit FAB in a predetermined combination, exclusive It includes a logical OR circuit and an inverter circuit. The output signal of the AND gate circuit is internal subtraction data mb0, and the output signal of the exclusive OR circuit is internal subtraction data mb1. The output signal of the inverter circuit is the internal subtraction data mb2. The internal addition data sb3 is the internal subtraction data m as it is.
It is assumed to be b3. As a result, the internal subtraction data mb0 to mb3 are mb0 = sb0 · sb1 · sb2 mb1 = sb1sb2 mb2 = ▲ ▼ mb3 = sb3, which respectively satisfy the logical condition as a minus 6 circuit. These internal subtraction data mb0 to mb3
Is supplied to the other input terminal of the selection circuit SEL4.

Although not particularly limited, the selection circuit SEL3 is supplied with the above-described group carry propagation function P03 from the group function generation circuit GAFG. The selection circuit SEL4 is not particularly limited,
The group carry generation function G03 is supplied from the group function generation circuit GAFG. Further, the internal control signal bcd described above is commonly supplied to the selection circuits SEL3 and SEL4 from an arithmetic control unit (not shown).

The selection circuit SEL3 selects the internal addition data sa0 to sa3 output from the full addition circuit FAA or the internal subtraction data ma0 to ma3 output from the minus 6 circuit-6A according to the internal control signal bcd and the group carry propagation function P03. Then, as the first internal output data, the selection circuit SEL5 (fifth selection circuit)
It is transmitted to one of the input terminals. Similarly, the selection circuit SEL4
Is the internal addition data s output from the full addition circuit FAB according to the internal control signal bcd and the group carry generation function G03.
The internal subtraction data mb0 to mb3 output from b0 to sb3 or the minus 6 circuit -6B are selected and transmitted to the other input terminal of the selection circuit SEL5 as the second internal output data.

Here, the output signals of the minus 6 circuits -6A and -6B are
As is well known, the arithmetic and logic unit ALU is in decimal mode and the output carry signal C00 or C
When out is set to logic "0", it needs to be selectively transmitted. The output carry signal Cout is formed according to the logical condition of Cout = C00 = G03 + P03.C04, where C04 is the input carry signal input from the preceding unit adder circuit to this unit adder circuit. In this embodiment, the full adder circuit FAA is included in the first adder circuit whose input carry signal, that is, C04 is fixed to the logic "1", as described above, and the full adder circuit FAB is included in the input carry signal. C04 is included in the second adder circuit fixed to logic "0". Therefore, the output carry signal Cout becomes Cout = G03 + P03 in the first adding circuit and Cout = G03 in the second adding circuit. That is, the selection circuit SEL3 outputs the output of the minus 6 circuit -6A on condition that the internal control signal bcd is at the high level and either the group carry propagation function P03 or the group carry generation function G03 is logic "1". Signals may be selectively transmitted, and the selection circuit SEL4 sets the internal control signal bcd to the high level and sets the group carry generation function G03 to the logic "1".
The output signal of the minus 6 circuit -6B may be selectively transmitted on the condition that In this embodiment, the group carry propagation function P03 includes the group carry generation function G03.
Therefore, the selection circuit SEL3 further controls the internal control signal bcd.
Is set to the high level and the group carry propagation function P03 is set to the logic "1", the output signal of the minus 6 circuit -6A is selectively transmitted.

The group carry generation circuit GCG1 described later is included in the selection circuit SEL5.
The input carry signal, which is formed from the
C04 is supplied. The selection circuit SEL5 selects the output signal of the selection circuit SEL3, that is, the addition result of the first addition circuit, when the input carry signal C04 is logic "1",
The output data S0 to S3 of this unit adder circuit is used. Further, when the input carry signal C04 is logic "0", the output signal of the selection circuit SEL4, that is, the addition result of the second addition circuit is selected and used as the output data S0 to S3 of this unit addition circuit. As a result, the arithmetic processing required to form the input carry signal C04, the addition processing of the arithmetic data X0 to X3 and Y0 to Y3, and the 6 subtraction processing required in the decimal mode are performed in parallel, and the arithmetic logic The arithmetic processing of the arithmetic unit ALU as a whole is speeded up.

By the way, the group carry generation circuit GCG1 is not particularly limited, but the operation data X0 to X3 and Y0 to Y3 to X12.
To X15 and Y12 to Y15, group carry propagation functions P03, P07, P11 and P15 and group carry generation functions G03, G07, G11 and G15 are supplied from four sets of unit adder circuits. Similarly, the group carry generation circuits GCG2 to GCG4 are supplied to the group carry propagation function P1 from the corresponding four sets of unit addition circuits.
9, P23, P27 and P31 to P51, P55, P59 and P63 and group carry generation functions G19, G23, G27 and G31 to G51, G55, G5
9 and G63 are supplied respectively.

As described above, the input carry signal Cin is supplied to the carry input terminal of the group carry generation circuit GCG4. Although not particularly limited, the carry input terminal of the group carry generation circuit GCG3 is supplied with the carry signal C48 output from the group carry generation circuit GCG4, and the group carry generation circuit GCG3.
The carry input terminal of 2 is connected to the above group carry generation circuit GCG
The carry signal C32 output from 3 is supplied. Furthermore, the carry input terminal of the group carry generation circuit GCG1
The carry signal C16 output from the preceding group carry generating circuit GCG2 is supplied.

The group carry generation circuits GCG1 to GCG4 are carry signals required for each unit addition circuit based on the group carry propagation function and group carry generation function output from the corresponding four sets of unit addition circuits and the input carry signal. Form C04, C08 to C60. Also, the unit carry propagator functions UP15, UP31,
UP47 and UP63 and unit carry generation function UG15, U
Unit carry generation circuit that forms G31, UG47 and UG63
Supply to UCG.

The unit carry generation circuit UCG is the unit carry propagation functions UP15, UP31, UP47 and UP63 and the unit carry generation functions UG15, UG31, UG47 and UG63 supplied from the group carry generation circuits GCG1 to GCG4 and the input carry signal Ci.
An output carry signal Cout as an arithmetic logic unit ALU is formed based on n. This output carry signal Cout
Is transmitted to and held in a carry register (not shown) of the arithmetic and logic unit ALU, although not particularly limited thereto.

In the arithmetic logic operation unit ALU of this embodiment, the carry operation processing by the group carry generation circuits GCG1 to GCG4 is performed by the corresponding group of four group carry propagation functions and group carry generation functions and their respective input carry signals, as described above. Is based on. Similarly, the carry operation processing by the unit carry generation circuit UCG is performed based on the four sets of the unit carry propagation function and the unit carry generation function and the input carry signal Cin as described above. In this embodiment, the group carry propagating function and the group carry propagating function, and the unit carry propagating function and the unit carry propagating function respectively pass through one stage or a stage of logic gate circuit, as exemplarily shown in FIG. As a result, it is formed at a relatively high speed. Further, the addition processing by each unit addition circuit and the carry calculation processing by the group carry generation circuit and the unit carry generation circuit are performed in parallel as described above, and the calculation processing of the arithmetic logic operation unit ALU as a whole is speeded up. Is planned. However, the level of the carry signal output from the group carry generation circuits GCG1 to GCG4 is determined when the level of the input carry signal Cin or the level of the input carry signal from the preceding unit adder circuit is determined. Therefore, this arithmetic logic unit
In the ALU, the carry operation processing by the group carry generation circuits GCG1 to GCG4 becomes a critical path for the operation processing time of the entire arithmetic logic operation unit ALU. However, in the arithmetic logical operation unit ALU of this embodiment, as described above, the addition processing in each unit addition circuit is the conditional addition method including the 6 subtraction processing of the minus 6 circuits, and the group carry generation circuit is used. Is carried out in parallel with the carry calculation processing by. Therefore, in the conventional arithmetic logic operation unit ALU, the 6-subtraction processing that is performed after the levels of the output carry signals Cout and C04 are determined is deviated from the substantial critical path of the arithmetic logic operation unit ALU, and The arithmetic processing time of the arithmetic unit ALU as a whole is further shortened.

As described above, the arithmetic logic operation unit AL of this embodiment is
U includes 16 sets of unit addition circuits provided corresponding to every 4 bits of 64-bit operation data, and a group carry generation circuit and a unit carry generation circuit that are provided in common. The addition method is adopted, and each includes two sets of addition circuits and minus six circuits. The group carry generation circuit and the unit carry generation circuit adopt the carry look ahead method including the group function generation circuit of each unit addition circuit, and each include a function generation circuit composed of one or two stages of logic gate circuits. . As a result, the arithmetic processing of the arithmetic logic operation unit ALU is accelerated by adopting the conditional addition method and the carry look ahead method itself, and the minus 6 circuit is included in the addition circuit adopting the conditional addition method. The 6 subtraction process is performed in parallel with the carry calculation process of the group carry generation circuit and the unit carry generation circuit, whereby the speed is further increased.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a logical operation circuit such as an arithmetic logical operation unit adopting the conditional addition method and carry look ahead method. . That is, (1) In a logical operation circuit having an addition function for BCD coded operation data and employing a conditional addition method, 2
A selection is provided in which minus 6 circuits are respectively provided in the subsequent stages of the adder circuits provided in pairs, and the output signals of these minus 6 circuits are selectively transmitted according to the group carry propagation function and the group carry generation function output from the corresponding group function generation circuit. By providing the circuit, it is possible to obtain the effect that the addition process for the operation data and the 6 subtraction process for the operation result can be performed in parallel with the series of carry operation processes.

(2) According to the above item (1), it is possible to obtain an effect that the arithmetic processing of the entire logical operation circuit such as the arithmetic logical operation unit can be speeded up.

(3) According to the above items (1) and (2), it is possible to enhance the processing capability of a microcomputer or the like including a logical operation circuit such as an arithmetic logic operation unit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and needless to say, various modifications can be made without departing from the scope of the invention. . For example, in FIG. 1, two sets of adder circuits provided in each unit adder circuit are integrated with a function generating circuit, a half adder circuit, a full adder circuit, a carry generating circuit, and a group function generating circuit. May be. In this case, for example, calculation data X0 to X3 and Y0 to
Y3 is directly input to the half adder circuit. Group carry generation circuit
The GCG1 to GCG4 and the unit carry generation circuit UCG may each employ a conditional operation method. The selection circuit SEL3 may use, for example, both the group carry propagation function P03 and the group carry generation function G03 as switching control signals. Further, the selection circuits SEL3 and SEL4 and the selection circuit SEL5 may be integrated into one selection circuit which receives the internal control signal bcd, the group carry propagation function P03, the group carry generation function G03 and the carry signal C04, for example.
The operation data supplied to the arithmetic logic operation unit ALU is
It can have any bit length. The arithmetic logic operation unit ALU may not include the complement generation circuit COM. Furthermore, the arithmetic logic unit AL shown in FIG.
Various embodiments can be adopted, such as the block configuration of U, the specific circuit configuration of each block shown in FIGS. 2 and 3, and the combination of operation data and control signals.

In the above description, the invention mainly made by the present inventor has been described as applied to an arithmetic logic operation unit of a microcomputer, which is a field of application of the background, but the invention is not limited thereto and, for example, various digital It can also be applied to a similar arithmetic logic circuit included in a processor or a digital controller. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a logical operation circuit having an addition / subtraction function for BCD coded operation data and adopting a conditional addition method or a digital device including such a logical operation circuit.

[Effects of the Invention] The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a logical operation circuit having an addition function for BCD-encoded operation data and employing a conditional addition method, minus 6 circuits are respectively provided at the subsequent stages of the adder circuits provided in two sets, and output signals of these minus 6 circuits are provided. By providing a group carry propagation function output from the corresponding group function generation circuit and a selection circuit for selectively transmitting the group carry generation function according to the group carry generation function, the addition process for the operation data and the 6 subtraction process for the operation result It can be performed in parallel with the carry calculation process. This allows
The arithmetic processing of the logical operation circuit can be speeded up, and the processing capability of the digital processing device including the logical operation circuit can be increased.

[Brief description of drawings]

1 is a partial block diagram showing an embodiment of an arithmetic logic operation unit to which the present invention is applied, and FIGS. 2 and 3 show an embodiment of the arithmetic logic operation unit of FIG. Partial circuit diagram, FIG. 4 is a partial block diagram showing an example of a conventional arithmetic logic operation unit. ALU ... Arithmetic and logic unit, COM ... Complement generation circuit,
+ 6 …… Plus 6 circuit, AFG …… Function generator circuit, HA ……
Half addition circuit, CGA, CGB ... Carry generation circuit, GAFG ...
Group function generator, FAA, FAB ... Full adder, −6, −6A, −
6B: Minus 6 circuit, GCG1 to GCG4: Group carry generation circuit, UCG: Unit carry generation circuit, SEL1 to SEL7
...... Selection circuit.

Claims (1)

(57) [Claims] 1. An arithmetic logic operation unit incorporated in a digital processing device composed of a one-chip semiconductor integrated circuit, the complement forming a complement of first operation data divided into groups of 4 bits. A generation circuit; a first selection circuit for transmitting the first operation data or the output signal of the complement generation circuit as first internal operation data according to an addition or subtraction mode; and a second group divided every 4 bits. A plus 6 circuit for adding +6 to the above operation data, and a second selection circuit for transmitting the above-mentioned second operation data or the output signal of the above plus 6 circuit as the second internal operation data in accordance with the binary or BCD operation mode. A first adder circuit receiving the first and second internal operation data and having an input carry signal fixed to logic "1"; and the first and second internal operation data Data, and a second adder circuit whose input carry signal is fixed to logic "0", and a first minus 6 circuit which subtracts -6 from the output signal of the first adder circuit. And a second minus 6 circuit for subtracting -6 from the output signal of the second adder circuit and the first minus 6 circuit when the corresponding group carry is generated in the BCD operation mode. When a corresponding group carry is generated in the BCD operation mode and the third selection circuit which transmits the output signal of the circuit, otherwise the output signal of the first addition circuit as the first internal output data A fourth selection circuit for transmitting the output signal of the second minus 6 circuit as the second internal output data, and the output signal of the second addition circuit for the other components as the second internal output data. Depending on the carry signal, the first or the first Arithmetic logic unit characterized by comprising comprises a unit adding circuit comprising a plurality including a fifth selection circuit for transmitting internal output data as output data, respectively.