JPH01280828A - Logical operation circuit - Google Patents

Abstract

PURPOSE:To increase the working speed of a logical operation circuit and also to improve the processing ability of a digital processor including said logical operation circuit by performing addition processing to arithmetic data as well as minus-6 subtraction processing to said addition result in parallel to carry arithmetic processing performed by a carry generating part. CONSTITUTION:The minus-6 circuits -6A and -6B are set at the next stage of two pairs of addition circuits and selection circuits SEL1-5 are added to transmit selectively the output signals of both circuits -6A and -6B in accordance with group carry transmission functions and group carry generation functions received from the corresponding group function generating circuit GAFG. Thus the addition processing and the minus-6 subtraction processing can be carried out to the arithmetic data and to the result of said addition respectively in parallel to a series of carry arithmetic operations. As a result, the working speed of a logical operation circuit is increased and the processing ability is improved for a digital processor including the logical operation circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a logic operation circuit, for example, B
CD (Binary Coded Decimal)
: It has an addition function for calculation data made into a binary coded decimal code, and it also has a conditional addition function.
The present invention relates to a technique that is particularly effective when used in arithmetic and logic units that employ the nalSum) method.

[Conventional technology]

There is an arithmetic and logic operation unit that has an addition/subtraction function for BCD-encoded operation data every 4 bits. Further, as one method for speeding up the arithmetic processing of such an arithmetic and logic unit, there is a conditional addition method.

Regarding the conditional addition method, for example, June 2, 1972
It is described on pages 98 to 108 of "Electronic Computer Course Part 4: Computer System Design" published by Sanpo on the 0th.

[Problem to be solved by the invention]

FIG. 4 shows a partial block diagram of the arithmetic and logic unit 1-ALU developed by the inventors of the present invention prior to the present invention. The arithmetic and logic operation unit ALU in the figure employs the above-mentioned conditional addition method, and has an addition/subtraction function for BCD encoded operation data.

In FIG. 4, the operation data input to the arithmetic and logic operation unit (ALU) has a length of 8 bytes, that is, 64 bits, and is divided into groups of 4 bits each. The calculation data is a BCD code with each group having one digit when the arithmetic logic unit ALU is set to a predetermined calculation mode.

The arithmetic and logic operation unit ALU includes 16 unit adder circuits provided corresponding to each group of operation data.

Each unit addition circuit of the ALU (arithmetic and logic operation unit)
As exemplarily shown in the figure, the carry propagation function p is based on the corresponding internal operation data xO~x3 and yO~y3.
These carry propagation functions and carry generation functions, which include function generation circuits AFG forming carry generation functions gO to g3 and O to p3, respectively, are generated by a half adder circuit HA consisting of four exclusive OR circuits and its input. The carry signal is supplied to carry generation circuits CGA and CGB fixed at logic "1" or logic "01, respectively, and group function generation circuit GAFG forming group carry propagation function PO3 and group carry generation function G03. Among these, Function generation circuit AFG, half adder circuit HA, and carry generation circuit CG
A is a full adder circuit FA consisting of four exclusive OR circuits.
Together with A, it constitutes a first addition circuit. In addition, a function generation circuit AFG, a half adder circuit HA, and a carry generation circuit C
GB constitutes a second adder circuit together with a full adder circuit FAB, which is also made up of four exclusive OR circuits. The output signals of the full adder circuits FAA and FAB are sent to the selection circuit 5EL.
At step 6, it is selectively enabled according to the carry signal C04 output from the group carry generation circuit GCG1, and is set as internal output data sQ~33.

In other words, in this arithmetic and logic operation unit ALU, by providing two sets of adder circuits, the addition processing for the operation data X0-X3 and YO-Y3 is related to the level of the input carry signal, that is, the output carry signal CO4 of the previous group. When the carry signal CO4 is determined, the calculation result corresponding to the level is selected. As a result, the carry calculation process by the group carry generation circuit GCG1 and the like and the addition process by the adder circuit can be performed in parallel, so that the calculation process of the arithmetic logic unit ALU can be speeded up.

On the other hand, the group carry propagation function PO3 and the group carry generation function GO3 formed by the inter-group number generation circuit 0AFC are supplied to the corresponding group carry generation circuit GCCI.

The arithmetic and logic operation unit (ALU) includes a 0 group carry generation circuit GCGI- which includes four group carry generation circuits GC01 to GCG4 and one unit carry generation circuit UCG.
GCG4 receives group carry propagation functions P03 to P03 from the intergroup number generation circuit GAFG of the four corresponding unit adder circuits.
Six group carry generation circuits GCG1 to GCG4 are supplied with P15 to PO51 to P63 and group carry generation functions GO3 to G15 to 051 to 063, respectively.
Based on these group carry propagation functions and group carry generation functions, output carry signals GO4 to C48, etc. of each group are formed and supplied to the next stage group carry generation circuit, and unit carry propagation functions UP15 to UP63 are formed. In addition, unit carry generation functions UG15 to UG63 are formed and supplied to the unit carry generation circuit UCG. Unit carry generation circuit UC
G forms an output carry signal Cout as an arithmetic and logic operation unit ALU based on the unit carry propagation function and unit carry generation function.

Each carry propagation function and carry generation function in the function generation circuit AFG, the group function group raw number generation circuit C, and the unit carry generation circuit UCG.

As is well known, the group carry propagation function, the group carry generation function, and the unit carry propagation function and unit carry generation function are each formed through one or two stages of logic gate circuits. As a result, the carry generation section of the arithmetic logic unit 1-ALU is of the so-called carry look-ahead type, and each output carry signal is formed in a relatively short time even though the operation data is 64 bits long. become something that

However, the inventors of the present invention have discovered that the above-mentioned arithmetic and logic unit (ALU) has the following problems. That is, the arithmetic logic unit ALU is
As mentioned above, when the calculation data XO to X3 and YO-Y3 are made into BCD codes, the function generating circuit AFG has the function of performing decimal addition calculation without changing the form of the addition circuit. At the front stage, there is a plus 6 circuit +6 that adds 6 to one calculation data YO-Y3, and when the calculation mode of the arithmetic logic unit 1-ALU is set to decimal mode and the internal control signal bed is set to high level, the above A selection circuit 5EL2 is provided that selectively transmits the output signal of the +6 circuit +6 as internal calculation data yo=y3. Further, at the subsequent stage of the selection circuit 5EL6, there is a minus 6 circuit-6 for subtracting 6 from the calculation result of the unit addition circuit, that is, the internal output data 5o-s3, and a group in which the internal control signal bed is set to a high level and corresponds to the minus 6 circuit-6. A selection circuit 5EL7 is provided which selectively transmits the output signal of the minus 6 circuit-6 as output data SO to S3 when the output carry signal CoutfJ<logic@0'.

Here, as described above, the output carry signal CO4 is formed by the corresponding group carry generation circuit GCG1, and its level is the same as that of the previous stage group carry generation circuits GC02 to GC.
It is determined after all output carry signals C16, C32 and C48 of G4 are determined. For this reason, the carry arithmetic processing for forming the output carry signal CO4 and the 6-subtraction processing by the minus 6 circuit-6 become critical buses of the arithmetic and logic operation unit ALU, and their speedup is limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logical arithmetic circuit that achieves high-speed arithmetic processing.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief summary of typical inventions disclosed in this application is as follows.

That is, in a logical operation circuit that has an addition function for BCD-coded operation data and uses a conditional addition method, minus 6 circuits are provided at the rear stage of two sets of addition circuits, and the output signals of these minus 6 circuits are A selection circuit is provided for selectively transmitting a group carry propagation function and a group carry generation function outputted from a corresponding intergroup number generation circuit.

[For production]

According to the above-mentioned means, the addition process to the calculation data and the 6-subtraction process to the calculation result can be performed in parallel with the carry calculation process by the carry generation section.

Therefore, the processing speed of such a logical operation circuit can be increased, and the processing capacity of a digital processing device including the logical operation circuit can be increased.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a mechanical calculation unit ALU to which the present invention is applied. Furthermore, in FIGS. 2 and 3, the function generation circuit AFG and the carry generation circuit CG of the arithmetic and logic operation unit (ALU) in FIG. 1 are shown.
A and CGB, half adder circuit HA, full adder circuit FAA and FA
B, a circuit diagram of an embodiment of minus 6 circuits -6A and -6B and intergroup number generating circuit GAFG is shown. According to these figures, the arithmetic and logic operation unit of this embodiment)A
An overview of the configuration and operation of the LU will be explained.

The arithmetic and logic operation unit (ALU) of this embodiment is, although not particularly limited, built into a one-chip microcomputer, and as described later, has 16 sets of unit addition circuits provided corresponding to 4-pin operation data. include. In FIG. 1, the highest calculation data XO to X3 and YO to Y are shown.
A set of unit adder circuits provided corresponding to No. 3 is exemplarily shown. The following explanation uses this unit addition circuit as an example, so calculation data X4 to X63 and Y4 to Y
As for the other unit adder circuits provided corresponding to 63, please make an analogy.The circuit elements constituting each block in FIG. It is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon along with circuit elements constituting blocks (not shown).

The arithmetic and logic operation unit ALU of this embodiment performs various arithmetic operations based on binary logic addition using 64 bits as a unit, although this is not particularly limited.

The arithmetic and logic operation unit 7) ALU is supplied with operation data XO to X63 (first operation data) and YO to Y63 (second operation data) via two sets of internal buses not shown. An input carry signal Ctn is supplied from a carry register or the like that is not used. In this embodiment, each unit addition circuit of the arithmetic logic unit 7) ALU is
It adopts a conditional addition method, and has two sets of adder circuits whose output data is selectively enabled according to the output carry signal of the corresponding group.
For calculation data that is BCD encoded bit by bit,
Further, the arithmetic and logic unit ALU, which has a function of performing decimal addition and subtraction processing, includes group carry generation circuits GC01 to GCG4 provided corresponding to the four unit adder circuits,
These group carry generation circuits and unit carry generation circuits, including the unit carry generation circuit UCG provided corresponding to all the unit adder circuits, are of a carry look-ahead type, although not particularly limited thereto. As a result, the arithmetic and logic operation unit (ALU) of this embodiment not only speeds up the addition processing of each unit adder circuit, but also speeds up the addition processing by these adder circuits and the group carry generation circuit and unit carry generation circuit. By performing the carry generation processing in parallel, the calculation processing speed is increased and the time required to form the output carry signal Cout is shortened.

In FIG. 1, the arithmetic data XO to X3 divided into groups of 4 bits are, but not particularly limited to, the complement generation circuit CO of the corresponding unit adder circuit of the arithmetic and logic unit ALU.
M is supplied to selection circuit 5ELL (first
selection circuit). In addition, the calculation data YO-Y3 is similarly divided into 4 be/ ) units.
is an arithmetic and logical operation (unif, but not limited to) A
It is supplied to the plus 6 circuit +6 of the corresponding unit adder circuit of LU, and is also supplied to one input terminal of the selection circuit 5EL2 (second selection circuit). The input carry signal Cin is supplied to the group carry generation circuit GC as described later.
G4 and the carry input terminal of the unit carry generation circuit UCG.

The complement generation circuit COM selectively forms a two's complement or a ten's complement based on the calculation data X0-X3. The output signal of the complement generation circuit COM is sent to the selection circuit SEL.
Although not particularly limited, an internal control signal com is supplied to the 9 selection circuit 5EL1 supplied to the other input terminal of 9 selection circuit 5EL1 from an arithmetic control unit (not shown). Although not particularly limited, this internal control signal Com is selectively set to a high level when a subtraction process is performed in the arithmetic logic unit ALU.

When the internal control signal com is set to a low level, the selection circuit 5EL1 selects the calculation data XO-X3 and transmits it to the function generation circuit AFG as internal calculation data xO-x3 (first internal calculation data). As a result, the calculation data XO to X3 are transmitted as they are to the adder circuit, and an addition process is performed using the data as an addend. On the other hand, selection circuit SE
L1 selects the output signal of the complement generation circuit COM when the internal control signal com is set to high level, and transmits it to the function generation circuit AFG as the internal calculation data xO to x3. As a result, the adder circuit has the calculation data XO~
The complement of X3 is transmitted, and subtraction processing is performed using this as the subtraction.

The plus 6 circuit +6 adds 6 to the calculation data YO to Y3, although this is not particularly limited. plus 6 circuit +6
The output signal is supplied to the other input terminal of the selection circuit 5EL2.The 0 selection circuit 5EL2 is supplied with an internal control signal bed from an arithmetic control unit (not shown), although this is not particularly limited. Although not particularly limited, this internal control signal bed can be used for calculation data XO to X3 and YO-Y.
3 are both BCD code and arithmetic logic operation unit) A
When decimal addition/subtraction processing is performed in the LU, it is selectively set to high level.

When the internal control signal bed is set to a low level, the selection circuit 5EL2 selects the calculation data YO to Y3 and transmits it to the function generation circuit AFG as internal calculation data yO to y3 (second internal calculation data). As a result, the calculation data YO to Y3 are transmitted as they are to the adder circuit, and binary addition and subtraction processing is performed using the data as an addend or a minuend.

On the other hand, when the internal control signal bed is at a high level, the selection circuit 5EL2 selects the output signal of the +6 circuit +6 and transmits it to the function generation circuit AFG as the internal calculation data yO=y3. As a result, the result of adding 6 to the calculation data YO to Y3 is transmitted to the adding circuit, and decimal addition/subtraction processing is performed using this as the summand or subtractive.

Although not particularly limited, the function ordering circuit AFG receives the internal calculation data yO-73 corresponding to the internal calculation data XO to x3, as shown in FIG.
Fl! The output signal of each OR gate circuit including the J OR gate circuit and AND gate circuit is set to a carry propagation function pO-p3, and the output signal of each AND gate circuit is set to a carry generation function gO-g3.

As a result, the carry propagation functions po-p3 are, respectively,
po-xo+yO p l =
g3 is formed under the following logical conditions: go-xO-yO gl-xi.yl g2-X2.y2 g3-X3.y3.

Carry propagation function pO~p3 and carry generation open number gO
-g3 is the half adder circuit HA and the carry generation circuit CGA
(first carry generation circuit), CGB (second carry generation circuit) and intergroup number generation circuit GAFG.

Although not particularly limited, the half adder circuit HA includes four exclusive OR circuits each receiving the carry propagation functions pO to p3 and the corresponding carry generation functions gO to g3, as shown in FIG.

The output signals of these exclusive OR circuits are half addition data shQ to sh3, respectively. As a result, the half-added data 5hO-sh3 are shO=p069g, respectively.
O = (xO+yO) @ (xO・yO)=xQ■y.

shl=plegl = (xl+yl)O+ (xi-yl)=xl■yl sh2=p263g2 = (X2・y2) of (x2+y2) =x2$y2 sh3=p3■g3 = (x3+y3) e(x3・y3)= It is formed under the logical condition of X369y3. These half addition data shO to sh3 are not equal to the result of directly inputting the internal operation data xO to x3 and yO to y3 into the corresponding exclusive OR circuit, that is, the arithmetic and logic operation unit 1- In the ALU, as will be clear from the explanation that will be given later, the arithmetic processing by the half adder circuit HA, the carry generation circuits CGA and CGB, and the group number generation circuit GAFG is performed by the output signal of the function generation circuit AFG provided at the first stage, that is, the carry. By performing this based on the propagation functions pO to p3 and the carry generation open number gO to g3, the circuit configuration can be simplified. Half addition data shQ to Sh3 are sent to full addition circuits FAA ($1 full addition circuit) and FAB (second
is supplied as one input signal of the full adder circuit).

Next, the carry generation circuit CG A generates carry propagation functions p1 to CG as shown in FIG. 2, although not particularly limited.
It includes a plurality of AND gate circuits and OR gate circuits that receive p3 and carry generation function gl-g3 in a predetermined combination. A carry input terminal C of this carry generation circuit CGA is coupled to the power supply voltage of the circuit. As a result, the input carry signal to the carry generation circuit CGA is fixed at logic "1". As is clear from FIG. 2, the carry signal Ca output from the carry generation circuit CGA
0=ca3 is Ca0-g1+pl・g2+ pl・p2・g3+pl-p2・p3 cal=g2+p2・g3+p2-p3ca2=g3+
These carry signals caQxca3 are nothing but carry signals for full addition of each pin when the corresponding input carry signal is set to logic "L".
! Provided as the other input signal of gFAA.

Similarly, the carry generation circuit CGB has a carry propagation function pO~ as shown in FIG. 2, although it is not particularly limited.
It includes a plurality of AND gate circuits and OR gate circuits that receive p3 and carry generation functions gO to g3 in predetermined combinations. A carry input terminal C of this carry generation circuit CGB is coupled to the ground potential of the circuit. As a result, the manual carry signal for the carry generation circuit CGH is fixed at logic "0". As is clear from FIG. 2, the carry signal cb output from the carry generation circuit CGB
O~cb3 are respectively cbo=gl+pl・g2+
These carry signals are nothing but carry signals for total addition of each bit when the corresponding input carry signal is set to logic "0°" (bQ=cb3 is co-supplied as the other input signal of the full adder circuit FAB.

The intergroup number generation circuit GAFG is not particularly limited, but the third
As shown in the figure, the carry propagation function pO~p3
As is clear from FIG. 3, the intergroup number generation circuit 0AF includes a plurality of AND gate circuits and OR gate circuits that receive carry generation functions gO to g3 in predetermined combinations.
The output signals of C, that is, the group carry propagation function PO3 and the group carry generation function GO3 are as follows, respectively: PO3=pO-pi・p2・p3 GO3=gO+-po・gt+po-pi・
It is formed under a predetermined logical condition of g2+pQ.pl.p2.g3.

The full adder circuit FAA is not particularly limited, but as shown in FIG.
The output signals of these exclusive OR circuits, including 4f exclusive OR circuits each receiving the corresponding carry signals caO to ca3 outputted from the terminals, are respectively set as internal addition data SaQ-sa3. . This results in
The output signal of the full adder circuit FAA, that is, the internal addition data s
aQ to sa3 are respectively 5aO=shOCa0 sal=shlecal sa2=sh2ca2 sa3=sh3ca3, which are nothing but the addition results of each bit when the input carry signal C is set to logic "1". That is, in this embodiment, the full adder circuit FAA is the function generating circuit A
Together with FG, half adder circuit HA, and carry generation circuit CGA, it constitutes a first adder circuit. This first
The output signal of the adder circuit, that is, the internal addition data saQ~
sa3 is supplied to minus 6 circuit-6A (first minus 6 circuit) and further supplied to one input terminal of selection circuit 5EL3 (third selection circuit).

Similarly, the full adder circuit FAB can be used, although not particularly limited, as shown in FIG. Carry signal CbO-
It includes four exclusive OR circuits each receiving cb3. The output signals of these exclusive OR circuits are used as internal addition data sbo to sb3, respectively. As a result, output No. 13 of the full adder circuit FAB, that is, internal addition data s
bQ to sb3 are respectively 5bQ=shQ■cbO sbl=shl■cbl sb2-sh2ecb2 sb3=sh31EE)cb3, and are nothing but the addition results of each bit when the input carry signal C is set to logic "0". That is, in this embodiment, the full adder circuit FAB is the function generator circuit A.
Together with FG, half adder circuit HA, and carry generation circuit CGB, it constitutes a second adder circuit. This second
The output signal of the adder circuit, that is, the internal addition data 5bOx
sb3 is supplied to the minus 6 circuit-6B (second minus 6 circuit) and further supplied to one input terminal of the selection circuit 5EL4 (fourth selection circuit).

Although the minus 6 circuit-6A is not particularly limited, as shown in FIG. The output signal of the AND gate circuit including the circuit and the inverter circuit is
The output signal of the exclusive OR circuit is defined as internal subtraction data maQ, and the output signal of the exclusive OR circuit is defined as internal subtraction data mal. Furthermore, the output signal of the inverter circuit is internal subtraction data ma2
It is said that Internal addition data sa3 is directly used as internal subtraction data ma3. As a result, the internal subtraction Σ! -ta r
nao~dingna3 is mao=saQ-sal・
aa 2rna 1 ”x a les a '1m
a2-=sa2 m a 3 = sa 3 , and each satisfies the logical conditions for a minus 6 circuit. These internal subtraction data maQ~m
a3 is supplied to the other input terminal of the selection circuit 3EL3.

Similarly, the minus 6 circuit-6B is an AND gate circuit that receives internal addition data sbQ to 5L12 outputted from the above-mentioned W circuit FAB in a predetermined combination, as shown in FIG. 2, although it is not particularly limited. exclusive i, 2. The output signal of the AND gate circuit including the Logic 81 Logic 1 circuit and converter circuit is the internal subtraction data mbQ, and the output signal of the exclusive OR circuit is the internal subtraction data mbQ.
It is assumed that l.

Further, the output signal of the inverter circuit mentioned above is the internal subtraction data m b 2. The internal addition data sb3 is directly used as the internal subtraction data rnb3. As a result, the internal subtraction data m b Q - m b 3 is mbo
=sbo・sbl・sb2 m b 1- s b 1 ■ sb2 m b 2- s b 2 m b 3 = s b 3, and each of them satisfies the logical conditions as a minus 6 circuit. These internal subtraction data m b O
-m b 3 is supplied to the other input terminal of the selection circuit 5EL4.

The selection circuit 5EL3 receives the above group carry propagation function PO3 from the group number generation circuit GAFG, although it is not particularly limited.
is supplied. Furthermore, the selection circuit 5EL4 is supplied with the group carry generation function GO3 described above from the group function generation circuit GAFG, although this is not particularly limited. Furthermore, the above-mentioned internal control signal bed is commonly supplied to the selection circuits 5EL3 and 5EL4 from an arithmetic control unit (not shown).

The selection circuit 5EL3 selects internal addition data saQ to sa3 output from the full adder circuit FAA or internal subtraction data maQ output from the minus 6 circuit-6A according to the internal control signal bed and group carry propagation function PO3.
xma3 is selected and transmitted as first internal output data to one input terminal of the selection circuit 5EL5 (fifth selection circuit).

Similarly, the selection circuit 5EL4 selects the internal control signal bed.
According to the group carry generation function GO3, the full adder circuit F
Select internal addition data 5bO=sb3 output from AB or internal subtraction data mbo=mb3 output from minus 6 circuit-6B and transmit it to the other input terminal of the selection circuit 5EL5 as second internal output data. .

Here, as is well known, the output signals of the minus 6 circuits -6A and -6B are the output carry signal C00 of the corresponding group when the arithmetic logic unit ALU is in the decimal mode.
That is, when CouL is set to logic "0", it needs to be selectively transmitted. In addition, the above output carry signal C
out is Co when CO4 is the input carry signal input to this unit adder from the previous unit adder.
It is formed according to the logical condition: ut-COO-GO3+PO3.CO4. In this embodiment, the full adder circuit FAA is included in the first adder circuit whose input carry signal, CO4, is fixed to logic "1", as described above, and the full adder circuit FAB is included in the first adder circuit, whose input carry signal, CO4, is fixed to logic "1". CO4 is included in a second summing circuit where it is fixed at logic 10°.

Therefore, the output carry signal COLlt is
In the adder circuit, CouL=GO3+PO3, and in the second adder circuit, CouL−CO
3, that is, the selection circuit 5EL3 has internal control (iq
It is only necessary to selectively transmit the output signal of the minus 6 circuit-6A on the condition that bed is at a high level and either the group carry transmission IIIJ function PO3 or the group carry generation function GO3 is at logic °1". and selection circuit 5EL
4 may selectively transmit the output signal of the minus 6 circuit-6B on condition that the internal control signal bed is set to high level and the group carry generation function G03 is logic "1". In this example, the group carry propagation function P0
3 includes the group carry generation function GO3. Therefore, the selection circuit 5EL3 further sets the internal control signal bed to a high level and sets the group carry propagation function PO3 to a logic "
1, the output signal of the minus 6 circuit-6A is selectively transmitted.

The selection circuit 5EL5 includes a group carry generation circuit G, which will be described later.
An input carry signal CO4, which is formed through a regular procedure, is supplied from CG1. When the input carry signal CO4 is set to logic "1", the selection circuit 5EL5 selects the output signal of the selection circuit 5EL3, that is, the addition result of the first addition circuit, and selects the output data S of this unit addition circuit.
O to S3. Further, when the input carry signal CO4 is set to logic "0", the output signal of the selection circuit 5EL4, that is, the addition result of the second addition circuit is selected and used as the output data SO to S3 of this unit addition circuit. As a result, the arithmetic processing necessary to form the input carry signal CO4, the addition processing of the arithmetic data X0-X3 and YO-Y3, and the 6-subtraction processing necessary in the decimal mode are performed in parallel, and the arithmetic logic The arithmetic processing of the arithmetic unit 1-ALU as a whole is accelerated.

By the way, the group carry generation circuit GCG1 can process data X0-X3 and YO-Y3, although it is not particularly limited.
or one ζ corresponding to X12 to X15 and Y12 to Y15
Group carry propagation functions PO3, PO7, Pll and PI3 and group carry generation functions GO3, GO7, Gll and G15 are supplied from four sets of unit adder circuits provided. Similarly, group carry generation circuits GCG2 to GCG4
, the group carry propagation function P19. P23. P27 and P31 to P51
．． P55. P59 and P63 and group carry generation function G19,023. G27 and G31 to G51. G
55. G59 and G63 are supplied respectively.

The carry input terminal of the group carry generation circuit GCG4 is
As mentioned above, the input carry signal Cin is supplied to the terminal (.). Although not particularly limited, the carry input terminal of the group carry generation circuit GCG3 may include the group carry generation circuit ccc.
A carry signal C48 outputted from the group carry generation circuit GCG3 is supplied to the carry input terminal of the group carry generation circuit GCG2. Furthermore, the group carry generation circuit G
A carry signal C16 output from the group carry generation circuit GCG2 at the previous stage is supplied to the carry input terminal of CGI.

Group carry generation circuits GCGI to GCG4 correspond to 4
Group carry output from unit adder circuit) 1!5
! ! Based on the number, group carry generation function, and input carry signal, the carry signal CO required for each unit addition circuit is calculated.
4. Form COB to C60. Also, the unit carry propagation function UPI5, [JP31. UP47 and U
15. to P63 and unit carry generation function U. U
G31. UG47 and UG63 are formed and supplied to the unit carry generation circuit UCG.

The unit carry generation circuit UCG generates a unit carry propagation function UP15. which is supplied from the group carry generation circuits GCG1 to GCG4. UP31゜UP47 and UP6
3 and unit carry generation function UG15. UG3
1. Based on UG47 and UG63 and input carry signal Cin, an output carry signal Cout as an arithmetic and logic operation unit ALU is formed. This output carry signal C
.

ut is, but is not particularly limited to, an arithmetic and logic unit A.
It is transmitted to and held in a carry register (not shown) of the LU.

In the arithmetic and logic operation unit ALU of this embodiment, the carry operation processing by the group carry generation circuits GC01 to GCG4 is performed using four sets of corresponding group carry propagation functions and group carry generation functions and their respective input carry signals. It is done based on. Similarly, carry calculation processing by unit carry generation circuit UCG is performed based on four sets of unit carry propagation functions, unit carry generation functions, and input carry signal Cin, as described above. In this embodiment, the group carry propagation function, the group carry generation function, the unit carry propagation function, and the unit carry generation function each have one or two stages of logic gate circuits, as exemplarily shown in FIG. It can be formed at a relatively high speed by using the media. Furthermore, the addition process by each unit adder circuit and the carry 2iI arithmetic process by the group carry generation circuit and unit carry generation circuit are performed in parallel, as described above, and the arithmetic logic operation unit (ALU) as a whole performs the arithmetic processing. The speed will be increased. However, group carry generation circuits GCG1 to GC
The level of the carry signal output from G4 is determined at the time when the level of the input carry signal Cin or the input carry signal from the unit adder circuit in the previous stage is determined. Therefore, in this arithmetic and logic operation unit I-ALU, the carry operation processing by the group carry generation circuits GC01 to GCG4 becomes a critical bus for the operation processing time of the entire arithmetic and logic operation unit I-ALU.

However, in the arithmetic and logic operation unit ALU of this embodiment, as mentioned above, the addition processing in each unit addition circuit is a conditional addition method including 6 subtraction processing of minus 6 circuits, and the above group carry generation circuit This is done in parallel with the carry operation processing. Therefore, in the conventional arithmetic and logic unit ALU, the output carry signal Cout
The 6-subtraction processing that was performed after the level of C04 and C04 was determined is removed from the practical theoretical path of the arithmetic and logic unit ALU, and the arithmetic processing time of the arithmetic and logic unit ALU as a whole is further reduced. Become.

As described above, the arithmetic logic unit AL of this embodiment
U includes 16 sets of unit adder circuits provided corresponding to every 4 pins of 64 pinto operation data, and a group carry generation circuit and a unit carry generation circuit provided in common.Each unit adder circuit meets the conditions. An additive addition method is adopted, and each includes two sets of adder circuits and minus six circuits. In addition, the group carry generation circuit and unit carry generation circuit, including the intergroup number generation circuit of each unit adder circuit, adopt a carry look-ahead method, and each has a function generation circuit consisting of one or two stages of logic gate circuits. include. the result,
The arithmetic processing of the arithmetic logic unit I-ALU is accelerated by adopting the conditional addition method and the carry look ahead method, and the minus 6 circuit is included in the adder circuit which uses the conditional addition method. By performing the 6-subtraction processing in parallel with the carry calculation processing of the group carry generation circuit and the unit carry generation circuit, the speed can be further increased.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to logic operation circuits such as arithmetic and logic operation units that employ the conditional addition method and the carry lookahead method. . In other words, (11B) In a logical operation circuit that has an addition function for CD-encoded operation data and uses a conditional addition method, two sets of minus 6
By providing a selection circuit that selectively transmits the output signals of these minus 6 circuits according to the group carry propagation function and group carry generation function output from the corresponding intergroup number generation circuit, addition to the calculation data can be performed. The advantageous effect is that the processing and the 6-subtraction processing for the result of the calculation can be performed in parallel with the series of carry calculation processing.

(2) According to the above item (1), it is possible to achieve the effect that the arithmetic processing of the entire logic operation circuit such as the arithmetic logic operation unit can be made faster.

(3) The above (11) and (2) provide the effect that the processing capacity of a microcomputer or the like including a logic operation circuit such as an arithmetic and logic operation unit can be increased.

Although the invention made by the present inventor has been specifically explained based on Examples above, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without getting across the gist of the invention. . For example, in FIG. 1, the two sets of adder circuits provided in each unit adder circuit are a function generator, a half adder, a full adder, a carry generator, and an intergroup number generator. In this case, for example, the calculation data X0-X3 and Y
O-Y3 is directly input to the half adder circuit.

Each of the group carry generation circuits GC01 to GCG4 and the unit carry generation circuit UCG may employ a conditional calculation method. The selection circuit 5EL3 includes, for example, a group carry propagation function PO3 and a group carry generation function GO3.
Both of these may be used as switching control signals. Further, the selection circuits 5EL3 and 5EL4 and the selection circuit 5EL5 may be integrated into one selection circuit that receives the internal control signal bed, the group carry propagation function PO3, the group carry generation function GO3, and the carry signal CO4. The operation data supplied to the ALU (operation unit) can have any bit length. Furthermore, the arithmetic and logic unit ALU may not include the complement generation circuit COM. Furthermore, the block configuration of the arithmetic and logic unit ALU shown in FIG.
Various embodiments may be adopted, such as the specific circuit configuration of each block shown in the figure, and combinations of calculation data, control signals, etc.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to the arithmetic and logic operation unit of a microcomputer, which is the background field of application. It can also be applied to similar arithmetic logic circuits included in processing devices and digital control devices. This invention at least
It can be widely used in logic operation circuits that have addition/subtraction functions for BCD encoded operation data and employs a conditional addition method, or digital devices that include such logic operation circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a logical operation circuit that has an addition function for BCD-coded operation data and uses a conditional addition method, minus 6 circuits are provided at the rear stage of two sets of addition circuits, and the output signals of these minus 6 circuits are By providing a selection circuit that selectively transmits the data according to the group carry propagation function and group carry generation function output from the corresponding intergroup number generation circuit, addition processing to the operation data and 6 subtraction processing to the operation result can be performed in a series. This can be done in parallel with the carry operation processing. This results in
The processing speed of the logical operation circuit can be increased, and the processing capacity of the digital processing device including the logical operation circuit can be increased.

[Brief explanation of the drawing]

FIG. 1 is a partial block diagram showing an embodiment of an arithmetic and logic unit to which the present invention is applied, and FIGS.
FIG. 4 is a partial circuit diagram showing an embodiment of the arithmetic and logic unit shown in FIG. 1, and FIG. 4 is a partial block diagram showing an example of the conventional arithmetic and logic unit. ALU...Arithmetic logic unit, COM...Complement generation circuit, +6...Plus 6 circuit, AFG...Function generation circuit, HA...Half addition circuit, CGA, CGB...
・Carry generation circuit, GAFG... intergroup number generation circuit,
FAA, FAB...Full adder circuit, -6, -6A, -6
B...minus 6 circuit, GCG1 to GCG4... group carry generation circuit, UCG... unit carry generation circuit, SEL 1 to 5EL7... selection circuit.

Claims (1)

[Scope of Claims] 1. It has an addition function for BCD-encoded calculation data, and includes a plus 6 circuit, an addition circuit, and a minus 6 circuit for that purpose, and the conditions include the minus 6 circuit. A logic operation circuit characterized by adopting an additive method. 2. The logic operation circuit includes a complement generation circuit that receives first operation data divided into groups of 4 bits and forms its complement, and an output signal of the first operation data or the complement generation circuit according to the operation mode. a first selection circuit that selects and transmits it as the first internal calculation data; a plus-six circuit that receives second calculation data divided into groups of 4 bits and adds 6 to it; a second selection circuit that selects the calculated data or the output signal of the plus 6 circuit and transmits it as second internal calculation data; and a second selection circuit that receives the first and second internal calculation data and whose input carry signal is a logic a first adder circuit whose input carry signal is fixed at logic "0"; a second adder circuit which receives the first and second internal calculation data and whose input carry signal is fixed at logic "0"; The first step is to subtract 6 from the output signal of the adder circuit.
a second minus 6 circuit that subtracts 6 from the output signal of the second addition circuit, and an output signal of the first addition circuit or the first minus 6 circuit according to the operation mode or the operation result. a third selection circuit that selects and transmits the signal as the first internal output data; and a third selection circuit that selects the output signal of the second addition circuit or the second minus 6 circuit according to the calculation mode or the calculation result and transmits the second internal output data. and a fifth selection circuit that selects the first or second internal output data according to the output carry signal of the corresponding group and transmits the selected internal output data as output data. A logic operation circuit according to claim 1, characterized in that the logic operation circuit comprises: 3. The unit addition circuit includes a function generation circuit that receives the first and second internal operation data and forms a corresponding carry propagation function and carry generation function, and a function generation circuit that receives the carry propagation function and carry generation function and receives the input of the carry propagation function and the carry generation function. a first carry generation circuit whose carry signal is fixed to logic "1"; and a second carry generation circuit which receives the carry propagation function and carry generation function and whose input carry signal is fixed to logic "0".
a carry generation circuit, a half adder circuit consisting of four exclusive OR circuits each receiving the corresponding carry propagation function and carry generation function, and corresponding output signals of the first carry generation circuit and the half adder circuit. a first full adder circuit consisting of four exclusive OR circuits each receiving a second full adder circuit; and a group function generation circuit that receives the carry propagation function and the carry generation function and forms a corresponding group carry propagation function and group carry generation function, the first adder circuit is composed of the function generation circuit, the half addition circuit, the first carry generation circuit, and the first full addition circuit, and the second addition circuit is composed of the function generation circuit, the half addition circuit, and the second carry generation circuit. It is composed of a carry generation circuit and a second full addition circuit, and the third and fourth selection circuits determine the operation result based on the group carry propagation function and the group carry generation function. 3. The logic operation circuit according to claim 1 or 2, wherein the logic operation circuit is