JPH01286021A - Logical arithmetic circuit - Google Patents

Abstract

PURPOSE:To shorten the cycle time of a microcomputer and to raise a processing capacity by executing the arithmetic processing cycle of a logical arithmetic circuit such as an arithmetic and logial unit with a pipe line at high speed. CONSTITUTION:For an arithmetic and logical unit ALU, a combining circuit to cinstitute respective unit arithmetic circuits is parted to a first combining circuit including up to a half adder circuit and a second circuit including after a full adder circuit. A latch circuit LT is provided between first and second circuits and a pipe line processing is executed by first and second combining circuits. As the result, for the ALU, the adding processing of respective unit arithmetic circuits is executed at a high speed. These adding processings and the carry generating processing due to a group carry generating circuit and a unit carry generating circuit are executed in parallel and the arithmetic processing is generally executed at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic operation circuit, for example,
The present invention relates to a technique that is particularly effective for use in arithmetic and logic units such as chip microcomputers.

[Conventional technology]

There is an arithmetic processing device such as a microcomputer that includes an arithmetic and logic operation unit. In these processing units,
The arithmetic logic unit includes multiple stages of combinational circuits substantially in series, such as, for example, plus-six circuits, half-adder circuits, full-adder circuits, and minus-six Igl circuits.

Regarding the arithmetic processing device, for example, Japanese Patent Application No. 1986-215
It is described in No. 776, etc.

[Problem a that the invention seeks to solve]

FIG. 6 shows an arithmetic and logic operation unit ALU of a microcomputer developed by the present inventors prior to this invention.
A partial block diagram of is shown. The arithmetic and logic operation unit ALU in figure r71 employs the so-called conditional addition method, and also uses BCD (Binary Cod
ed Decis+al) Has addition and subtraction functions for coded calculation data.

In FIG. 6, the operation data input to the arithmetic and logic operation unit ALU has a length of 8 bytes, that is, 64 bits, and is divided into groups of 4 bits each. These calculation data are made into a BCD code in which each group has one digit in a predetermined calculation mode. Arithmetic and logical operation UNIF)AL
U includes 16 unit arithmetic circuits provided corresponding to each group of arithmetic data.

Each unit arithmetic circuit of the arithmetic logic unit ALU has a sixth
As exemplarily shown in the figure, for example, the operational logic unit ALU further includes the internal operation data lO~x3.
It includes a selection circuit SEL 1 that operates a function generation circuit AFG that forms carry propagation functions pO to p3 and carry generation functions gO to g3 based on yO to y3, and also adds 6 to the calculation data YO to Y3. The output signal of the plus 6 circuit +6 and the output signal of the plus 6 circuit +6 and the above operation data YO-Y3 or the above plus 6 circuit +6 are selectively converted into internal data y according to the operation mode.
It includes a selection circuit 5EL2 that transmits signals as O to y3.

The arithmetic and logic operation unit 1-ALU further includes a function generation circuit AFG that forms carry propagation functions pO to p3 and carry generation functions gO to g3 based on the internal operation data xO to x3 and yO to y3. The carry propagation function and the carry generation function are common to the half adder circuit HA, the intergroup number generation circuit GAF-G, and the carry generation circuits CGA and CGB whose input carry signals are fixed to logic "1s" or logic "O", respectively. Among these, the function generation circuit AFG, the half adder circuit HA, and the carry generation circuit CGA constitute the first adder circuit together with the full adder circuit FAA. The generation circuit CGB is a full adder circuit F.
Together with AB, it constitutes a second addition circuit.

The output signals of the full adder circuits FAA and FAB are sent to the selection circuit 5.
is selectively enabled by EL3 in accordance with the carry signal CO4 output from the group carry generation circuit GCGl,
These are internal output data sO to s3. These internal output data sO-33 are further outputted as output data SO-S3 after passing through a minus 6 circuit-6 and a selection circuit 5EL4 which are selectively enabled according to the operation mode and the output carry signal Cout.

In other words, in this arithmetic and logic operation unit ALU, by providing two sets of adder circuits, the addition process for the operation data XO to X3 and yo to Y3 is performed regardless of the input carry signal, that is, the output carry signal CO4 of the previous stage group. When the carry signal CO4 is determined, the calculation result corresponding to the level is selected. As a result, the carry calculation process by the group carry generation circuit GC01 and the like and the addition process by the adder circuit can be performed in parallel, thereby speeding up the calculation process of the arithmetic logic unit (ALU).

On the other hand, the group carry propagation function PO3 and the group carry generation function GO3 formed by the inter-group number generation circuit GAFG are supplied to the corresponding group carry generation circuit GCGI.

Arithmetic logic unit 1-ALυ is a 0 group carry generation circuit GCG1 including four group carry generation circuits GCG1 to GCG4 and one unit carry generation circuit UCG.
~GCG4 receives the group carry propagation function P03 from the group number generation circuit GAFG of the four corresponding unit arithmetic circuits.
The 0 group carry generation circuits GCG1 to GCG4 to which P15 to PO51 to P63 and group carry generation functions GO3 to G15 to G51 to G63 are supplied, respectively, perform the respective Group output carry signals CO4 to C48
etc. and supply them to the next stage group carry generation circuit, as well as unit carry propagation functions UP15 to UP63 and unit carry generation function ucts.
to UG63 are respectively formed and supplied to the unit carry generation circuit UCG. Unit carry generation circuit U
CG is an arithmetic logic operation unit ALU based on the above unit carry propagation function and unit carry generation function.
The output carry signal Cout is formed as the output carry signal Cout.

In the function generation circuit AFG, the group function group raw number generation circuit G, and the unit carry generation circuit UCG, each carry propagation function and carry generation function.

As is well known, the group carry propagation function, the group carry generation function, and the unit carry propagation function and unit carry generation function are each formed through one or two stages of logic gate circuits. As a result, the carry generation section of the arithmetic logic unit ALU is of the so-called carry look-ahead type, and each output carry signal is formed in a relatively short time even though the operation data is 64 vias long. Become something.

However, the conventional arithmetic and logic unit A as described above
As mentioned above, although various efforts have been made to speed up the operation of the LU, it still has the following problems:
The LU includes multiple stages of combinational circuits that are substantially in series, such as the plus-six circuit +6, the function generator circuit AFG, the half-adder circuit HA, the full-adder circuits FAA, FAB, and the minus-six circuit-6. , arithmetic and logic unit)
As shown in FIG. 5, the arithmetic processing time T of the entire ALU is, for example, the arithmetic processing time up to the front stage of the arithmetic logic unit ALU, that is, the half adder circuit HA, and the arithmetic processing time up to the rear stage, that is, the full adder circuits FAA, FAB. When the subsequent calculation processing time is T2, it is essentially T-TI+T2. This is the fate of the arithmetic and logic unit I-ALU, etc., which has a complex logical configuration as described above, and its operation This is one of the factors that limits speed-up.

An object of the present invention is to provide a logic operation circuit such as an arithmetic and logic operation unit that achieves high-speed operation processing cycles. Another object of the present invention is to shorten the cycle time of a microcomputer, etc. that includes an arithmetic and logic unit, and to increase its processing capacity.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a plurality of combinational circuits constituting an arithmetic and logic unit, etc. are provided, with a first combinational circuit provided in the preceding stage and including, for example, up to a half adder circuit, and a subsequent stage including, for example, a full adder circuit, etc. and a second combinational circuit, and between these combinational circuits, a data holding circuit is provided that captures the output signal of the first combinational circuit and transmits it to the second combinational circuit according to a predetermined timing signal,
Pipeline processing is performed between these combinational circuits.

[For production]

According to the above-described means, it is possible to substantially speed up the operation processing cycle of a logic operation circuit such as an arithmetic logic operation unit. Thereby, the cycle time of a microcomputer or the like including an arithmetic and logic unit can be shortened and its processing capacity can be increased.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of an arithmetic and logic unit ALU to which the present invention is applied. Also, Figures 2 and 3 W! J shows a partial circuit diagram of an embodiment of the arithmetic and logic operation unit (ALU) of FIG. An overview of the configuration and operation of the arithmetic and logic unit 7) ALU of this embodiment will be explained with reference to these figures. The arithmetic and logic unit ALU of this embodiment is not particularly limited, but! It is built into a chip-type microcomputer, and includes 16 sets of unit arithmetic circuits provided corresponding to the arithmetic data for every 4 pins, as will be described later. A set of unit arithmetic circuits provided corresponding to X3 and YO to Y3 is exemplarily shown. The following explanation will be given using this unit arithmetic circuit as an example, so other unit arithmetic circuits provided corresponding to the arithmetic data x4 to X63 and Y4 to Y63 may be inferred by analogy. The circuit elements constituting the unit, along with the unit arithmetic circuits (not shown) of the arithmetic and logic unit ALU and the circuit elements constituting the blocks (not shown) of the microcomputer, are not particularly Mwi, but are mounted on a single semiconductor substrate such as single crystal silicon. It is formed. Also, in Figures 2 and 3, the channel (
MOSFETs with an arrow added to the back gate) are P
It is a channel type, and is shown to be distinguished from the N-channel MO3FET, which is not marked with an arrow. In FIGS. 2m and 3, the latch circuit LT is shown redundantly for ease of understanding.

The arithmetic and logic operation unit (ALU) of this embodiment performs various types of arithmetic processing based on two-way logical addition using 64 bits as a unit, although this is not particularly limited.

The arithmetic and logic units AL and U receive 64-bit operation data XO to X via two sets of internal buses (not shown).
63 and YO to Y63 are supplied, and an input carry signal C1n is supplied from a carry register (not shown). In this embodiment, the arithmetic logic unit ALU
Each unit arithmetic circuit employs a conditional addition method, and has two sets of adder circuits whose output data is selectively enabled according to the output carry signal of the corresponding group. The arithmetic and logic operation unit (ALU), which has the function of performing decimal addition and subtraction processing on operation data that is BCD coded for each bit, consists of group carry generation circuits GCG1 to GCG1, which are provided corresponding to four unit operation circuits.
These group carry generation circuits and unit carry generation circuits, including GCG4 and unit carry generation circuit UCG provided corresponding to all unit arithmetic circuits, are as follows:
Although not particularly limited, it is assumed to be a carry lookahead method. Furthermore, the arithmetic and logic operation unit) AL of this embodiment
U is a first combinational circuit in which the combinational circuits constituting each unit arithmetic circuit include up to the preceding stage, that is, a half adder circuit;
It is divided into a subsequent stage, that is, a second combinational circuit including a full adder circuit and subsequent stages.

Between the first and second combinational circuits, there is provided a data holding circuit, that is, a launch circuit LT, which captures the output signal of the first combinational circuit and transmits it to the second combinational circuit in accordance with the timing signal -3. and the second combinational circuit perform pipeline processing. As a result, the arithmetic and logic operation unit ALU of this embodiment can speed up the addition processing of each unit operation circuit, and can also perform the addition processing of these addition processing and the above-mentioned group carry generation circuit. Carry generation processing by the unit carry generation circuit and unit carry generation circuit is performed in parallel, which speeds up the calculation process overall, and in addition, by performing pipeline processing, the calculation processing cycle speeds up. .

In FIG. 1, arithmetic data XO to x3 supplied via an internal bus (not shown) are supplied to the complement generation circuit COM of the corresponding unit arithmetic circuit of the arithmetic and logic unit ALU, and are selected. Circuit 5E
It is supplied to one input terminal of L1. On the other hand, the calculation data YO to Y3 are supplied to the plus 6 circuit +6 of the corresponding unit calculation circuit, and also to one input terminal of the selection circuit 5EL2, although this is not particularly limited. 'fj! J
An input carry signal Cin supplied from a carry register (not shown) is supplied to the carry input terminals of the group carry generation circuit GCG4 and the unit carry generation circuit υCG, as will be described later.

The complement generation circuit COM selectively forms a two's complement or a ten's complement based on the operation data xO to x3 according to the operation mode of the arithmetic and logic operation unit ALυ.

The output signal of the complement generation circuit COM is sent to the selection circuit 5EL.
Although not particularly limited, an internal control signal c is supplied to the other input terminal of the 0 selection circuit 5EL1 from an arithmetic operation M control unit (not shown).

m is supplied as a selection control signal. internal control signal co
Although m is not particularly limited, arithmetic logic unit AL
When subtraction processing is performed in U, it is selectively set to high level.

When the internal control signal com is set to a low level, the selection circuit 5EL1 selects the calculation data XO-X3 and transmits it to the function generation circuit AFG as the internal calculation data xO-x3. As a result, the adder circuit has calculation data XO to X.
3 is transmitted as is, and addition processing is performed using this as an addend. On the other hand, when the internal control signal com is set to high level, the selection circuit 5EL1 selects the complement generation circuit COM.
output signal is selected and transmitted to the function generation circuit AFG as the internal calculation data xO to X3. As a result, the complement of 2 or 1O regarding the calculation data XO to X3 is transmitted to the adder circuit, and a subtraction process using this as a subtraction is performed.

Plus 6 circuit +6 is 6 for calculation data YO to Y3.
Add.

The output signal of the plus 6 circuit +6 is the selection circuit 5EL2.
Although not particularly limited, an internal control signal bed is supplied as a selection control signal from an arithmetic control unit (not shown) to the 0 selection circuit 5EL2 supplied to the other input terminal of the 0 selection circuit 5EL2. The internal control signal bed is selectively set to a high level when the operation data XO to X3 and YO to Y3 are both made into BCD codes and 1O base addition/subtraction processing is performed in the arithmetic and logic operation unit (ALU).

When the internal control signal bed is set to a low level, the selection circuit 5EL2 selects the calculation data YO-Y3 and transmits it to the function generation circuit AFG as the internal calculation data yO-y3. As a result, the adder circuit has calculation data YO to Y.
3 is transmitted as is, and binary addition/subtraction processing is performed using this as the summand or subtractive. On the other hand, when the internal control signal bed is set to high level, the selection circuit 5EL2 selects
The output signal of the +6 circuit +6 is selected and transmitted to the function generating circuit AFG as the internal calculation data yO to y3.

As a result, the addition result obtained by adding 6 to the calculation data YO to Y3 is transmitted to the adder circuit, and lO base addition/subtraction processing is performed using this as the summand or subtractive.

The function generating circuit AFG includes four OR gate circuits and an AND gate circuit that receive a combination of the internal calculation data X0 to x3 and the corresponding internal calculation data yO to y3, although not particularly limited thereto, as shown in FIG. including,
The output signal of each OR gate circuit is the carry propagation function pO
~p3, and the output signal of each AND gate circuit is a carry generation function gO~g3. As a result, the carry propagation functions pO~p3 are formed under the following logical conditions, respectively:
g3 is go-xo・yO gl=xl-yl g2-! It is formed under the logical condition 2.y2 g3mx3.y3.

Carry propagation function pO~p3 and carry generation function gO
~g3 is supplied to half adder circuit HA, carry generation circuits CGA and CGB, and intergroup number generation circuit GAFG.

Although not particularly limited, the half adder circuit HA receives the carry propagation functions pO to p3 and the corresponding carry generation functions gO to g3 in combination, as shown in FIG.
The output signals of these exclusive OR circuits are half addition data hO to h3. As a result, the half-added data h-o to h3 are respectively ho-pOeg.

= (xO+yo) e(xo・yO)xoeyO hl■plegl −(xl+yl)e(xi−yl) xleFl h2−1)20g2 − (x2+y2)Φ(X2・y2) x2ey2 h3thought 3eg 3 −(x3+y3) It is formed under the logical condition of (X3·y3) -x3693F3. These half addition data hO~h3 are internal calculation data XO~x3 and y
This is nothing but the result when O-y3 is input directly to the corresponding exclusive OR circuit. In other words, in the arithmetic and logic operation unit 7) ALU of this embodiment, as will be clear from the explanation below, the half adder circuit HA and carry generation circuits CGA and C
The circuit configuration is achieved by performing the arithmetic processing by GB and the group number generation circuit GAFG based on the output signal of the function generation circuit AFG provided at the first stage, that is, the carry propagation function pO-p3 and the carry generation functions gO to g3. This simplifies the process. Half addition data h.

~h3 are respectively supplied to corresponding input terminals of the latch 2 of the latch circuit LT.

The carry generation circuit CGA is not MRed by the samurai, but the second
As shown in WJ, the carry input terminal C of this carry generation circuit CGA includes a plurality of AND gate circuits and OR gate circuits that receive carry propagation functions p1 to p3 and carry generation functions gl-g3 in a predetermined combination. is coupled to the power supply voltage. As a result, the input carry signal to the carry generation circuit CGA is set to logic "1".
j@2r!!J As is clear from J, the carry signals aO to a3 output from the carry generation circuit CGA are respectively aQ g 1 +p 1・g2+ pip2・g3+pl・p2・p3 al-g, 2+p2・g3+p2-p3a2 self-g3+p
These carry signals aQxa3, which are nothing but carry signals for total addition of each bit when the corresponding input carry signal is set to logic "1", are used by the launch circuit LT.
are respectively supplied to corresponding input terminals of latches ti.

Similarly, the carry generation circuit CGB has carry propagation functions p1 to
A carry input terminal C of this carry generation circuit CGH, which includes a plurality of AND gate circuits and OR gate circuits that receive p2 and carry generation functions g1 to g3 in a predetermined combination, is coupled to the ground potential of the circuit. As a result, the input carry signal to the carry generation circuit CGB is fixed at logic "0". As is clear from FIG. 2, the carry signal bO output from the carry generation circuit COB
〜b3 are respectively bo-gl+pl-g2+pl-p2・g3bl-g2
+p2・g3 2−g3 b3−c=0, and these carry signals bo−b3 are not used as carry signals for full addition of each pit when the corresponding input carry signal is set to logic @0”. These carry signals bo−b3 are latch circuit LT
are respectively supplied to corresponding input terminals of latch L3.

The intergroup number generation circuit GAFG is not particularly limited, but the second
As shown in WI, the carry propagation function pO~p
As is clear from FIG. 2, the output signal of the group number generation circuit GAFG, that is, the group carry propagation function, P and the group carry generation function G are, respectively, P■PO・pl・p2・p3 G concession go+po salary gl+po・pi−g2+pQ・pl
・p2・g3 It is formed under the predetermined logical conditions. These group carry propagation function P and group carry generation function G are respectively supplied to corresponding input terminals of latch L4 of launch circuit LT.

The above complement generation circuit COM, plus 6 circuits + 6° selection circuits 5EL1 and 5EL2. Function generation circuit AFG, half adder circuit HA, carry generation circuits CGA and CHB, and group number generation circuit GAFG are connected to this arithmetic logic unit A.
A first combinational circuit provided before the LU is configured.

These combinational circuits execute the series of arithmetic operations described above without interrupting their operation.

The latch circuit LT includes, but is not particularly limited to, four sets of latches L1 to L4 as shown in FIG. , the corresponding carry signal aO~
a3 is supplied respectively. Similarly, the input terminals of the latch 2 are supplied with the corresponding half-added data hO to h3 from the half-adder circuit HA, and the input terminal of the latch L3 is supplied with the corresponding carry data hO-h3 from the carry generation circuit CGB. Signals bO to b3 are supplied, respectively. Further, the corresponding group carry propagation function P and group carry generation function G are respectively supplied to the input terminal of the launch L4.

Trigger input terminal t of latches L1 to L4 of latch circuit LT
A timing signal φ3 is commonly supplied to both from an arithmetic and control unit (not shown). The timing signal φ3 is
Although not particularly limited, it is usually set to low level, and the first
At the timing when the arithmetic processing of the combinational circuit is completed and the output signals of the half adder circuit HA, the carry generation circuits CGA and CGB, and the group number generation circuit GAFG are determined, the signal is temporarily set to a high level.

The latches L1 to L4 of the latch circuit LT are triggered by the timing signal φS being temporarily set to high level, and the corresponding carry signals aO to a3. Half addition data hO to h3. The carry signal bo-b3, the group carry propagation function P, and the group carry generation function G are taken in and held.

The latched 1 output signal of the latch circuit LT is supplied as carry signals c, aQ to ca3 to the corresponding one input terminal of the full adder circuit FAA, respectively. Similarly, the output signals of the lunch L3 are supplied as carry signals cbo to cb3 to the corresponding one input terminal of the full adder circuit FAB.

The output signal of launch 2 is half addition data ahQ~sh3
, and are commonly supplied to the other corresponding input terminals of the full adder circuits FAA and FAB. Furthermore, the output signal of the launch L4 is supplied to the corresponding group carry generation circuit GCG1 as a group carry propagation function P03 and a group carry generation function GO3.

The full adder circuit FAA is not particularly limited, but as shown in FIG.
The output signals of these exclusive OR circuits, including four exclusive OR circuits each receiving a combination of wca3, are internal addition data saQ to sa3. As a result, the output signals of the full adder circuit FAA, that is, the internal addition data saQ to sa3, respectively become 5ao-shQ@can sa1mshll$cal sa2=sh2eca2 8a3-sh3Φca3, which is the same as when the input carry signal C is set to logic "11". Internal addition data s, which is nothing but the addition result of each bit
aQ to sa3 are supplied as one input signal to the selection circuit 5EL3.

Similarly, the full adder circuit FAB receives the half-added data shO-ah3 outputted from the latch circuit LT in combination with the corresponding carry signals cbQ-cb3, respectively, as shown in FIG. 3, although this is not particularly limited. The output signals of these exclusive OR circuits including four exclusive OR circuits are used as internal addition data sbQ to sb3.

As a result, the output signals of the full adder circuit FAB, that is, the internal addition data abo to sb3, are respectively sbOmah
oecb.

5bl-shlΦcbl Sb2-ah2Φcb2 sb3=ah3E9cb3, and the internal addition data s is nothing but the addition result of each bit when the input carry signal C is set to logic °O''.
bo to sb3 are supplied as the other input signals of the selection circuit 5EL3.

The selection circuit 5EL3 is not particularly limited, but as shown in FIG. internal addition data abO to sb3 output from the gate group and the full adder circuit FAB;
A second transmission gate group consisting of four sets of transmission gates receiving
It is composed of three FETs, and the other one is commonly coupled to the other one of the corresponding transmission gates of the other transmission gate group. An input carry signal CO4 is commonly supplied from the group carry generation circuit GCG1 to the gates of the N-channel MO3FETs of the respective transmission gates constituting the first transmission gate group. In addition, the input carry signal CO is applied to the gates of the P-channel MO5FETs of these transmission gates.
4 inverted signals are commonly supplied. Similarly, the N-channel MO3 of each transmission gate constituting the second transmission gate group
An inverted signal of the input carry signal CO4 is commonly supplied to the gates of the FETs. Further, the input carry signal CO4 is commonly supplied to the gates of the P-channel MO5FETs of these transmission gates.

For these reasons, when the input carry signal CO4 is set to high level, the selection circuit 5EL3 selects the internal addition data SaO-aa3 output from the full adder circuit FAA, and sets them as internal output data 30-33. Further, when the input carry signal C'04 is set to low level,
Internal addition data sbQ output from full adder circuit FAB
-sb3 is selected and set as internal output data 30-33.

These internal output data lO~$3 are sent to the selection circuit 5EL.
It is supplied as one input signal of the input signal 4, and is also supplied to the minus 6 circuit-6.

Minus 6 times! -6 is an AND gate circuit, an exclusive OR circuit, and an inverter circuit that receive internal output data sO to s2 outputted from the selection circuit 5EL3 in a predetermined combination, as shown in FIG. 3, although not particularly limited thereto. Of these, the output signal of the AND gate circuit is internal subtraction data maQ, and the output signals of the exclusive OR circuit and inverter circuit are internal subtraction data msl and 111112, respectively. The internal output data 83 is directly used as the internal subtraction data ma3.

As a result, the internal subtraction data man to ms3 become msO-so-slm50 -5o-sl-s2 m53, respectively, and satisfy the logical condition as a minus 6[1 path. These internal subtraction data msQ to ms3 are supplied to the other input terminal of the selection circuit 5EL4.

Although the selection circuit 5EL4 is not particularly limited, similarly to the selection circuit 5EL3 described above, the selection circuit 5EL4 includes a first transmission gate group consisting of four sets of transmission gates that receive internal output data aO to 83 output from the selection circuit 5EL3; Internal subtraction data ms output from the above minus 6 circuit-6
and a second transmission gate group consisting of four sets of transmission gates receiving Q~ms3, each transmission gate is constituted by a pair of N-channel MO3FET and P-channel MO5FET in parallel configuration, and the other is: They are each commonly coupled to the other of the corresponding transmission gates of the other transmission gate group. The above-mentioned internal control signal bed and output carry signal Cout are applied to the gates of the N-channel MO3FETs of each transmission gate constituting the first transmission gate group.
The output signals of the AND gate circuits receiving the signals are commonly supplied. In addition, the P channel MO5F of these transmission gates
An inverted signal of the output signal of the AND gate circuit is commonly supplied to the gates of the ETs. Similarly, the N-channel MO3FE of each transmission gate constituting the second transmission gate group
The gates of T are commonly supplied with an inverted signal of the output signal of the AND gate circuit. Furthermore, the output signal of the AND gate circuit is commonly supplied to the gates of the P-channel MO3FETs of these transmission gates.

For these reasons, the selection circuit 5EL4 selects the arithmetic and logic operation unit when the output signal of the AND gate circuit is at a high level, that is, when both the internal control signal bed and the output carry signal Cout are at a high level. When the ALU is in the decimal calculation mode and the output signal Cout is set to logic "1", the internal subtraction data maQ~ output from the minus 6 circuit-6
Select ma3 and set it as output data SO to S3.

Furthermore, when the a-power signal of the AND gate circuit is set to low level, that is, when either the internal control signal bed or the output carry signal Cout is set to low level, in other words, the arithmetic logic unit ALU is in the binary operation mode. or arithmetic and logical operation unin) AL
U is in decimal operation mode and output carry signal Co
ut is the argument! ! @0''', selection circuit 5EL3
The internal output data sO to s3 output from are selected and set as output data SO to S3.

Above, full adder circuit FAA, FAB and minus 6 circuit-6
The selection circuits 5EL3 and 5EL4 constitute a second combinational circuit provided after the arithmetic and logic unit 1-ALU. These combinational circuits execute the series of arithmetic operations described above without interruption of their operation.

On the other hand, the group carry generation circuit GCGI has the operation f-IX
O~X3 and YO~Y3 to X12~X15 and Y1
From the latch circuit LT of the 4m unit arithmetic circuit provided corresponding to Y2 to Y15, the group carry propagation numerical numbers PO3, PG
? , pH and PI3 and group carry generation function G 0
3.G O? +Gll and G15 are supplied. Similarly, group carry generation circuits GC02 to GCG4 receive group carry outcome functions P19. P23. P27 and P31 to P51. P55. P59 and P63 and group carry generation function G19. G23. G27 and G31 to G
51. G5'5. G59 and G63 are supplied respectively.

The carry input terminal of the group carry generation circuit GCG4 is
As mentioned above, the input carry signal Cin is supplied to the 0
The carry input terminal of the group carry generation circuit GCG3 is
Carry signal C4 from the group carry generation circuit GCG4
A carry signal C32 is supplied from the group carry generation plane BGCG3 to the carry input terminal of the group carry generation circuit GCG2. Furthermore, a carry signal C16 is supplied to the carry input terminal of the group carry generation circuit GCG1 from the group carry generation circuit GCG2 at the previous stage.

Group carry generation circuits GC01 to GCG4 correspond to 4
Form carry signals CO4, CO8 to 06G required by each unit arithmetic circuit based on the input carry signal corresponding to the group carry propagation function and group carry generation function supplied from the unit arithmetic circuit of the set. . Also, based on the above group carry propagation function and group carry generation function, unit carry propagation function UP15.0P31. U.P.
47 and UP63 and unit carry generation function U
G15. UG31. Form υG47 and υG63.

These unit carry propagation functions and unit carry generation functions are supplied to a unit carry generation circuit UCG.

The unit carry generation circuit UCG has unit carry propagation functions UP15.0P31゜υP47 and υP6 supplied from the group carry generation circuits GCGI-GCG4.
3 and unit carry generation function υG15. UG3
1. UG47 and υG63 and input carry signal C1n;
i, an output carry signal Couz is formed as an arithmetic and logic unit ALU. This output carry signal C.

Although not particularly limited, ut is supplied to the selection circuit 5EL4, and is also transmitted to and held in a carry register (not shown) of the arithmetic and logic unit (ALU).

The group carry generation circuits GC01 to GCG4 and the unit carry generation circuit υCG are connected to another second combination unit provided after the arithmetic and logic operation unit ALυ.
Configure the circuit. These combinational circuits perform the above-described arithmetic processing (, - series) without disrupting their operation. In this embodiment, the group carry propagation function, the group carry generation function, the unit carry propagation function, and the unit carry QliR number are is the function generating circuit AFG between the second
As in the case of , each gate is formed at relatively high speed through one stage or 2a of logic gate circuits. Furthermore, addition processing by each unit arithmetic circuit and carry arithmetic processing by the group carry generation circuit and unit carry generation circuit are performed in parallel.
, υ The overall calculation processing speed can be increased.

FIG. 4 shows a timing diagram of one embodiment of the arithmetic and logic unit ALU of FIG.

According to the same figure, the arithmetic logic operation unit A1 of this embodiment
．． An overview of pipeline processing of 0 will be explained.

As mentioned above, the arithmetic and logic operation unit (ALU) of this embodiment is provided in the previous stage with a complement generation circuit COM, a plus 6 circuit +6 or a half adder circuit HA, and a carry generation circuit B.
It includes a first combinational circuit including up to CGA and CGB, and a second combinational circuit provided at the subsequent stage and including full adder circuits FAA and FAB to selection circuit 5EL4.

These combinational circuits are designed so that their operation is not disrupted (
A series of arithmetic processing is executed, and a latch circuit BLT triggered by a timing signal φ3 is provided between these combinational circuits, and with this latch circuit LT as a boundary,
Pipeline processing is performed.

In the fourth WJ, consecutive n-th and (n+1)-th operation cycles are exemplarily shown in order to explain this pipeline processing in an easy-to-understand manner.

In FIG. 4, the arithmetic and logic operation unit (ALU) receives operation data X0-X3 and YO-Y3, respectively, from Xn and Y3.
By being supplied with n combinations, the nth operation cycle is started.

As mentioned above, these calculation data are sent to the complement generation circuit C.
Select circuit 5ELI and 5 from OM and plus 6 circuit +6
It is transmitted to the function generation circuit AFG via EL2, and the carry propagation functions pO to p3 and the carry generation functions gO to g3 are transmitted to the function generation circuit AFG.
is formed. These carry propagation functions and carry generation functions are performed by half adder circuit HA and carry generation circuit CGA.
and CGB, so that the carry signal aox
a3 and bo to b3 and half addition data hO to h3 are formed.

Here, the complement generation circuit COM, plus 6 circuit + 6 or half adder circuit HA, and carry generation circuits CGA and CG
The first combinational circuit consisting of B, etc. requires arithmetic processing time TI. Therefore, the carry signals aO to a3 and bO to b3 and the half addition data hO to h3 are
As indicated by diagonal lines in J, after the calculation processing time T1 has elapsed since the calculation data Xn and Yn were supplied,
It is determined and set to a high level or a low level selectively depending on the combination of an, bn, and hn.

The above carry signals an and bn and half addition data h
n is taken into corresponding launches 1 to L3 of the latch circuit LT in accordance with the timing signal φ$ and is held.

Here, the timing signal φhata is not particularly limited, but
It is temporarily set to a high level approximately at an intermediate point in time when the levels of the carry signal and the half-added data are determined. As a result, carry signals caoxca3 and cbo-cb3 and half-added data sho-sh3 are output signals of the latch circuit LT.
It is formed by a combination of n.

Carry signals Can and cbn and half addition data shn output from the latch circuit LT are sent to the full addition circuit FA.
A and FAB, and further passes through a selection circuit 5EL3, a minus 6 circuit-6, and a selection circuit 5EL4 to form output data 30-33.

Here, the second combinational circuit consisting of the full adder circuits FAA and FAB, the selection circuit 5EL3, etc. requires an arithmetic processing time T2. Therefore, the output data fso-3
3 is determined after the arithmetic processing time T2 has elapsed since the carry signals can and Mcbn and the half-added data shn are determined, and is selectively set high in combination with Sn, as indicated by diagonal lines in FIG. level or low level.

By the way, the arithmetic and logic unit ALU of this embodiment employs pipeline processing as described above. Therefore, the calculation data Xn and Y of the n-th calculation processing cycle
When the carry signals an and bn corresponding to n and the half addition data hn are taken into the latch circuit LT, the arithmetic operations D, -Xn+1 and Yn+1 for the next cycle of arithmetic processing are supplied to the arithmetic and logic unit ALU. be done.

Therefore, these calculation data Xn+1 and Yn+1
The arithmetic processing of the first combinational circuit for the carry signals can and cbn and the arithmetic processing of the second combinational circuit for the half-added data shn are simultaneously executed in parallel. As a result, the actual operation processing cycle of the arithmetic and logic operation unit (ALU) is shortened, and equivalently, the operation processing speed of the arithmetic and logic operation unit (ALU) is increased.

The above pipeline processing is similarly performed between the first combinational circuit and another second combinational circuit consisting of group carry generation circuits GCGI to GCG4 and unit carry generation circuit υCG. This speeds up carry operation processing, and arithmetic and logic operations (UNIF) AL
The speed of the overall arithmetic processing of U can be increased.

As described above, the arithmetic logic unit AL of this embodiment
υ includes 16 sets of unit arithmetic circuits provided corresponding to every 4 bits of 64-bit arithmetic data, and a group carry generation circuit and a unit carry generation circuit provided in common. Each unit arithmetic circuit satisfies the conditions. It adopts an addition method and includes two sets of adder circuits, each of which is selectively enabled. Also, the group carry generation circuit and unit carry generation circuit, including the intergroup number generation circuit of each unit arithmetic circuit, carry The 0.000000000000000 uses a look-ahead method and each includes a function generation circuit consisting of one or two stages of logic gate circuits. Furthermore, the multiple stages of combinational circuits constituting the arithmetic and logic operation unit ALU of this embodiment include a complement generation circuit COM, a plus six circuit +6 or a half adder circuit HA, and a carry generation circuit C.
A first combinational circuit including GA, CGB, intergroup number generation circuit GAFG, etc., and full adder circuits FAA and FA.
It is divided into a second combinational circuit including B to selection circuit 5EL4, etc. A latch circuit LT is provided between these combinational circuits to capture and hold the output signal of the first combinational circuit in accordance with the tying signal φ3, and pipeline processing is performed between these combinational circuits. As a result, the arithmetic processing of the ALU (arithmetic and logical operation unit) is as follows.
By using the conditional addition method and the carry look ahead method, the processing speed can be increased, and by using the pipeline method, the calculation processing cycle can be substantially shortened and the processing speed can be further increased.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a logical operation circuit such as an arithmetic and logic operation unit fitted to a microcomputer or the like. That is, (1) a plurality of stages of combinational circuits constituting an arithmetic and logic operation unit, for example, a first combinational circuit provided in the preceding stage and including up to a half adder circuit, etc., and a subsequent stage including a full adder circuit and the subsequent stage; A data holding circuit is provided between these combinational circuits to take in the output signal of the first combinational circuit and transmit it to the second combinational circuit according to a predetermined timing signal. By performing pipeline processing between the combinational circuits, it is possible to obtain the effect that the actual operation processing cycle of the arithmetic and logic operation unit can be shortened.

B) The above item (1) has the effect of speeding up the calculation processing of the logic operation circuit such as the arithmetic and logic operation unit.

(j) Items (1) and (2) above have the effect of shortening the cycle time of a microcomputer, etc. that includes a logical operation circuit such as an arithmetic and logic operation unit, and increasing its processing capacity.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without deviating from the gist thereof. For example, in FIG. 1, the arithmetic and logic unit ALU may further include third and fourth combinational circuits coupled via a similar launch circuit; ) The ALU may have three or more stages of combinational circuits coupled via latch circuits, and may perform pipeline processing between these combinational circuits.

The group carry generation circuits GCG1 to GCG4 and the unit carry generation circuit UCG may each adopt a conditional calculation method, or may be implemented using full adder circuits FAA and FAB.
The latter stage is an arithmetic logic operation unit AL which may include a minus 6 circuit-6 and adopt a conditional addition method.
The operation data supplied to U can have any bit length. Furthermore, the arithmetic and logic unit ALU may not include the complement generation circuit WicOM. In FIGS. 2 and 3, the data holding circuit provided between the first and second combinational circuits is, for example, It may be a normal flip-flop circuit or a dynamic latch, or
The logic circuits constituting each circuit may be dynamic logic circuits such as precharged logic circuits. Various embodiments may be adopted, such as the specific circuit configuration of each block shown and combinations of the calculation data and control signals shown in FIG. 4.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to the arithmetic and logic operation unit of a microcomputer, which is the field of application that formed the background of the invention. It can also be applied to similar arithmetic logic circuits suitable for digital processing devices and digital control devices. This invention at least
The present invention can be widely used in logic operation circuits including multiple stages of combinational circuits substantially in series, or in digital devices including such logic operation circuits.

(Effects of the Invention) A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a plurality of stages of combinational circuits constituting a logical operation circuit such as an arithmetic logic operation unit, for example, a first combinational circuit provided in the preceding stage and including up to a half adder circuit, etc., and a first combinational circuit provided in the subsequent stage including a full adder circuit, etc. and a second combinational circuit including the following, and between these combinational circuits, the output signal of the first combinational circuit is taken in according to a predetermined timing signal, and the data is held to be transmitted to the second combinational circuit. By providing circuits and performing pipeline processing between these combinational circuits, it is possible to shorten the actual operation processing cycle of the arithmetic and logic operation unit and equivalently speed up the operation processing of the arithmetic and logic operation unit and the like. This makes it possible to shorten the cycle time of a microcomputer, etc. that includes a logical operation circuit such as an arithmetic and logic operation unit, and to improve its processing capacity.

[Brief explanation of the drawing]

1st WJ is a partial block diagram showing one embodiment of an arithmetic and logic operation unit to which the present invention is applied, FIG. 2 and 31! I is a partial circuit diagram showing one embodiment of the arithmetic and logic operation unit of FIG. 1, FIG. 4 is a timing diagram showing one embodiment of the arithmetic and logic operation unit of the first WJ, and FIG. 5 is a conventional FIG. 6 is a partial block diagram showing an example of a conventional arithmetic and logic unit. ALU...Arithmetic unit, COM...
Complement generation circuit, +6...plus 61i! Road, AFG・
...Function generation circuit, HA...Half adder circuit, CGA, C
GB...Carry generation circuit, GAFG...Inter-group number generation circuit, LT...Latch circuit, L1-L4...Latch, FAA, FAB...Full adder circuit, -6...Minus 6 Circuit, GCG1 to GCG4...Group carry generation circuit, UCG...Unit carry generation circuit, 5EL
1-5EL4...Selection circuit.

Claims (1)

[Claims] 1. A first combinational circuit that receives operation data, a data holding circuit that takes in the output signal of the first combinational circuit according to a predetermined timing signal, and a first combinational circuit that receives the output signal of the data holding circuit. 2. A logic operation circuit comprising: 2 combinational circuits. 2. The logic operation circuit according to claim 1, wherein the first and second combinational circuits perform pipeline processing. 3. The logic operation circuit is an arithmetic and logic operation unit that fits into a microcomputer, and the first combinational circuit is a complement generation circuit, a plus six circuit, a function generation circuit, and a half addition circuit of the arithmetic and logic operation unit. , a carry generation circuit, etc., and the second combinational circuit includes a full adder circuit, a group carry generation circuit, a minus 6 circuit, etc. of the arithmetic and logic unit. Or the logic operation circuit according to item 2.