JPS59157759A - 二重化システム - Google Patents

二重化システム

Info

Publication number
JPS59157759A
JPS59157759A JP58030788A JP3078883A JPS59157759A JP S59157759 A JPS59157759 A JP S59157759A JP 58030788 A JP58030788 A JP 58030788A JP 3078883 A JP3078883 A JP 3078883A JP S59157759 A JPS59157759 A JP S59157759A
Authority
JP
Japan
Prior art keywords
bus
controller
control
common bus
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58030788A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6350740B2 (cs
Inventor
Hiroshi Kawakami
拓 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58030788A priority Critical patent/JPS59157759A/ja
Publication of JPS59157759A publication Critical patent/JPS59157759A/ja
Publication of JPS6350740B2 publication Critical patent/JPS6350740B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
JP58030788A 1983-02-28 1983-02-28 二重化システム Granted JPS59157759A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58030788A JPS59157759A (ja) 1983-02-28 1983-02-28 二重化システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58030788A JPS59157759A (ja) 1983-02-28 1983-02-28 二重化システム

Publications (2)

Publication Number Publication Date
JPS59157759A true JPS59157759A (ja) 1984-09-07
JPS6350740B2 JPS6350740B2 (cs) 1988-10-11

Family

ID=12313408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58030788A Granted JPS59157759A (ja) 1983-02-28 1983-02-28 二重化システム

Country Status (1)

Country Link
JP (1) JPS59157759A (cs)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324346A (ja) * 1986-06-27 1988-02-01 Yokogawa Hewlett Packard Ltd 情報伝達方式
JP2010061606A (ja) * 2008-09-08 2010-03-18 Nec Corp Ｐｃｉカード、マザーボード、ｐｃｉバスシステム、制御方法、及びプログラム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324346A (ja) * 1986-06-27 1988-02-01 Yokogawa Hewlett Packard Ltd 情報伝達方式
JP2010061606A (ja) * 2008-09-08 2010-03-18 Nec Corp Ｐｃｉカード、マザーボード、ｐｃｉバスシステム、制御方法、及びプログラム

Also Published As

Publication number Publication date
JPS6350740B2 (cs) 1988-10-11

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