JPS59155921A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS59155921A
JPS59155921A JP58030272A JP3027283A JPS59155921A JP S59155921 A JPS59155921 A JP S59155921A JP 58030272 A JP58030272 A JP 58030272A JP 3027283 A JP3027283 A JP 3027283A JP S59155921 A JPS59155921 A JP S59155921A
Authority
JP
Japan
Prior art keywords
film
resist
resist pattern
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58030272A
Other languages
Japanese (ja)
Inventor
Hiromichi Watanabe
渡辺 広道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58030272A priority Critical patent/JPS59155921A/en
Publication of JPS59155921A publication Critical patent/JPS59155921A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor
    • G03F7/168Finishing the coated layer, e.g. drying, baking, soaking

Abstract

PURPOSE:To improve the performance of semiconductor elements, magnetic bubble memory elements and to forth manufactured using a resist pattern edge by reducing dullness of said edge by the method wherein surface of a substrate for fabricating resist pattern is coated with resist and is blanched by developing solution for a short time, after which exposure and development are performed. CONSTITUTION:Surface of the substrate is coated with soft-magnetic film 11 such as permalloy and further it is coated with positive resist film 12 of about 7,000Angstrom thick by spin-coating or the like. Next, said surface is blanched by developing solution such as alkaline aqueous solution for 30-90sec to generate a deteriorated layer 13 whose sensitivity to light is inferior to that of the resist film, over the whole surface of the film 12. After that, the substrate is subjected to usual exposure and development to offer a resist pattern 14 in which a left part 12' of the film 12 carrying a left part 13' of the deteriorated layer 13. By this method, when an exposed surface layer of the film 11 is removed by ion- milling, pressure resistance of the pattern increases corresponding to a square- cornered edge 14' and the pattern of 0.8mum wide can be obtained.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明はレジストパターンの形成方法、特にレジストパ
ターン・エツジのだれを少なくする方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for forming a resist pattern, and particularly to a method for reducing drooping of resist pattern edges.

(b)  技術の背景 フォトリングラフィ技術によシ各種のパターンを基板上
に形成させる方法は、半導体素子や磁気バブルメモリ素
子及O−混成集積回路等に広く利用さハているが、それ
ら素子等の高集積化及び高性評化に伴って、形成される
パターンが微細化されてきた。例えば、磁気バブルメモ
リ素子において、バブルドメインを発生・転送させる等
のパターンは1μm以下の幅及び間隔が要望されている
。そして、前記微細パターンを形成させるには、そノ1
゜と同じ形状のレジストパターンを露光・現像処理で形
成させなければならないが露光時に光の回折などにより
光の廻シ込みによって、形成されたレジストパターン・
エツジのだf′Lを無視できなくなる。
(b) Background of the technology The method of forming various patterns on a substrate using photolithography technology is widely used for semiconductor devices, magnetic bubble memory devices, O-hybrid integrated circuits, etc. With the increase in integration and performance, the patterns formed have become finer. For example, in a magnetic bubble memory element, patterns for generating and transferring bubble domains are required to have widths and intervals of 1 μm or less. In order to form the fine pattern, step 1
A resist pattern with the same shape as ゜ must be formed by exposure and development, but the resist pattern and
It becomes impossible to ignore the f'L of the edge.

(c)従来技術と問題点 第1図は従来方法で形成したポジ形微細しジストパター
ンの断面形状を、走査形電子顕微鏡で観察した代表例で
あシ、ウェー・・10表面にフォトリソグラフィ技術で
形成したレジストパターン2は、上面のエツジ部分2に
前述しただれが発生してい為。
(c) Prior art and problems Figure 1 is a typical example of the cross-sectional shape of a positive fine resist pattern formed by a conventional method, observed using a scanning electron microscope. The resist pattern 2 formed in 1. has the above-mentioned sagging in the edge portion 2 of the upper surface.

そのため、ウェーハ1の露早表層を例えばイオンミーリ
ング手段で除去したとき、ウェーハ1の&Jeを除去す
るとともにレジストパターン2の表層をも微少に除去す
るイオンミーリングは、ウェーハ1の表面に所望のエツ
チングパターンが形成されないという欠点があった。
Therefore, when the quick dew surface layer of the wafer 1 is removed by, for example, ion milling means, the ion milling that removes the &Je of the wafer 1 and also slightly removes the surface layer of the resist pattern 2 can produce a desired etching pattern on the surface of the wafer 1. It had the disadvantage that it was not formed.

特に、レジストパターン2の幅が1μm以下、例えば0
8μm程度になると、前記欠点は致命的結果をもたらす
ことVこなる。
In particular, the width of the resist pattern 2 is 1 μm or less, for example, 0 μm or less.
When the thickness becomes about 8 μm, the above-mentioned drawback becomes fatal.

(d)  発明の目的 本発明の目的は、上記問題点を除去して導体体素子や磁
気バブルメモリ素子等を高性能化させることである。
(d) Object of the Invention An object of the present invention is to eliminate the above-mentioned problems and improve the performance of conductor elements, magnetic bubble memory elements, and the like.

(eン 発明の4′4°IJ戊 上記目的は、レジストパターン形成用基板の表面1心レ
ジスト膜を被着し、適当な時間だけ前記レジスト膜の表
面を現像液にさらしたのち、露光・現像処理することを
特徴としたレジストバター7の形成方法によシ達成され
る。
(e) 4'4° IJ of the Invention The above object is to deposit a single-core resist film on the surface of a resist pattern forming substrate, expose the surface of the resist film to a developer for an appropriate period of time, and then expose the resist film to a developer. This is achieved by a method for forming the resist butter 7, which is characterized by a development process.

(f)  発明の実施例 以下、図面を用いて本発明の詳細な説明する。(f) Examples of the invention Hereinafter, the present invention will be explained in detail using the drawings.

第2図は、磁気バフルメモリ素子の磁性膜をエツチング
してなるバブルドメイン転送ループパターンの形成用レ
ジストパターンに、本発明方法を適用した一実施例に係
わる主要工程を順次説明するだめの断面図である。
FIG. 2 is a cross-sectional view for sequentially explaining the main steps of an embodiment in which the method of the present invention is applied to a resist pattern for forming a bubble domain transfer loop pattern formed by etching the magnetic film of a magnetic baffle memory element. be.

第2図(イ)において、基板の表面に被着したパーマロ
イ等の軟磁性膜11の表面に、スピンコード手段で厚さ
が約700OAのポジ形レジスト膜12を被着する。
In FIG. 2(a), a positive resist film 12 having a thickness of about 700 OA is deposited on the surface of a soft magnetic film 11 made of permalloy or the like deposited on the surface of the substrate by means of a spin code.

次いで、レジスト膜12の表面を現像液(アルカリ性水
溶液)に30秒〜90秒だけンヤヮー又は浸漬手段でさ
らす。その結果、第2図(ロ)に示す如くレジスト膜1
2の表面全体に、レジスト膜よシも光に対する感度の劣
る変質層13が形成されるO 次いで、通常の露光・す、像処理を行うと第2図(ハ)
に示す如く、レジスト膜12の残存部・12′に変質層
13の残存部13′が搭載されたレジストパターン14
が形成される。ただし、レジストパターン14の断面形
状は走査形電子嶺微鏡で観票しだものを図示してあり、
該形状を第1図に示した従来パターン2と比較したとき
、エツジ14′が角張って形成される。
Next, the surface of the resist film 12 is exposed to a developer (alkaline aqueous solution) for 30 seconds to 90 seconds using an immersion or dipping method. As a result, as shown in FIG. 2(b), the resist film 1
An altered layer 13, which is less sensitive to light than the resist film, is formed on the entire surface of the resist film.Next, when normal exposure and image processing are performed, the resultant layer 13 shown in Fig. 2 (c) is formed.
As shown in FIG. 1, a resist pattern 14 has a remaining portion 13' of the altered layer 13 mounted on the remaining portion 12' of the resist film 12.
is formed. However, the cross-sectional shape of the resist pattern 14 is shown using a scanning electron microscope.
When this shape is compared with the conventional pattern 2 shown in FIG. 1, the edges 14' are formed to be angular.

従って、レジストパターン14が被着してない磁性膜1
1の露呈表層をイオンミーリング手段で除去したとき、
レジストパターン140表層も微少に除去きれるが、エ
ツジ14′が角張っている分だけレジストパターン2よ
シ耐性を有するため、0.8μm幅のエツチングパター
ンが形成り能になった0 (,9)発明の詳細 な説明した如く、本発明方法になるレジストパターンは
、従来方法で形成されたものよシエノチング処理に対す
る剛性が優れるため、エツチングパターンの微細化が可
能となり、半導体素子ヤ・磁気パブルメ七り素子等を面
密度・高性能化し得た効果は極めて大きい。
Therefore, the magnetic film 1 to which the resist pattern 14 is not attached
When the exposed surface layer of No. 1 is removed by ion milling means,
Although the surface layer of the resist pattern 140 can be removed slightly, the angular edge 14' makes it more resistant than the resist pattern 2, making it possible to form an etching pattern with a width of 0.8 μm.0 (,9) Invention As explained in detail, the resist pattern formed by the method of the present invention has superior rigidity to the cyanoching process compared to that formed by the conventional method, so it is possible to miniaturize the etching pattern, and it is possible to improve the structure of semiconductor devices and magnetic bubbles. The effects of increasing the areal density and performance of these materials are extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来方法で形成したレジストツククー7の断面
形状を説明するだめの図、第2図は本発明の一実施例に
係わる主要工程とそれによ)形成されたレジストパター
ンの断面形状′12:説明するための図である。 なお図中において、1はウエーノ・(基板)、2゜14
はレジストパターン、2’、14’はエツジ部、11は
基板上に被着した磁性膜、12はレジスト膜、12′は
レジスト膜の現像による残存部、13はレジス゛ト膜の
変質層、13′はレジスト膜の現像による変質層の残存
部を示す。
FIG. 1 is a diagram for explaining the cross-sectional shape of a resist pattern 7 formed by a conventional method, and FIG. 12: It is a diagram for explanation. In the figure, 1 is Ueno (substrate), 2゜14
1 is a resist pattern, 2' and 14' are edge parts, 11 is a magnetic film deposited on the substrate, 12 is a resist film, 12' is a remaining part of the resist film after development, 13 is a deteriorated layer of the resist film, 13' indicates the remaining portion of the deteriorated layer due to development of the resist film.

Claims (1)

【特許請求の範囲】[Claims] レジストパターン形成用基板の表面にレジスト膜を被着
し、適当な時間だけ前記レジスト膜の表面を現像液にさ
らしたのち、露光・現像処理することを特徴としたレジ
ストパターンの形成方法。
1. A method for forming a resist pattern, which comprises depositing a resist film on the surface of a resist pattern forming substrate, exposing the surface of the resist film to a developer for an appropriate period of time, and then performing exposure and development treatment.
JP58030272A 1983-02-25 1983-02-25 Formation of resist pattern Pending JPS59155921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58030272A JPS59155921A (en) 1983-02-25 1983-02-25 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58030272A JPS59155921A (en) 1983-02-25 1983-02-25 Formation of resist pattern

Publications (1)

Publication Number Publication Date
JPS59155921A true JPS59155921A (en) 1984-09-05

Family

ID=12299061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58030272A Pending JPS59155921A (en) 1983-02-25 1983-02-25 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS59155921A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738910A (en) * 1985-06-12 1988-04-19 Hitachi, Ltd. Method of applying a resist
JPH01219740A (en) * 1988-02-26 1989-09-01 Mitsubishi Electric Corp Pattern forming process
JPH01238659A (en) * 1988-03-18 1989-09-22 Mitsubishi Electric Corp Pattern forming method
JPH028853A (en) * 1988-06-28 1990-01-12 Mitsubishi Electric Corp Pattern forming method
JPH02196241A (en) * 1989-01-25 1990-08-02 Rohm Co Ltd Resist pattern forming method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646530A (en) * 1979-09-25 1981-04-27 Nec Corp Preparation of resist pattern

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646530A (en) * 1979-09-25 1981-04-27 Nec Corp Preparation of resist pattern

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738910A (en) * 1985-06-12 1988-04-19 Hitachi, Ltd. Method of applying a resist
JPH01219740A (en) * 1988-02-26 1989-09-01 Mitsubishi Electric Corp Pattern forming process
JPH01238659A (en) * 1988-03-18 1989-09-22 Mitsubishi Electric Corp Pattern forming method
JPH028853A (en) * 1988-06-28 1990-01-12 Mitsubishi Electric Corp Pattern forming method
JPH02196241A (en) * 1989-01-25 1990-08-02 Rohm Co Ltd Resist pattern forming method
JPH0579982B2 (en) * 1989-01-25 1993-11-05 Rohm Kk

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