JPS59154519A - Power source controller - Google Patents

Power source controller

Info

Publication number
JPS59154519A
JPS59154519A JP58028225A JP2822583A JPS59154519A JP S59154519 A JPS59154519 A JP S59154519A JP 58028225 A JP58028225 A JP 58028225A JP 2822583 A JP2822583 A JP 2822583A JP S59154519 A JPS59154519 A JP S59154519A
Authority
JP
Japan
Prior art keywords
key
signal
power
input
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58028225A
Other languages
Japanese (ja)
Inventor
Takao Morimoto
森本 孝男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Toshiba TEC Corp
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tokyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP58028225A priority Critical patent/JPS59154519A/en
Publication of JPS59154519A publication Critical patent/JPS59154519A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To perform power-on control securely in response to each key input by turning on a power source repeatedly in the rising of the next key input signal when the key input is generated right before the power source is turned off. CONSTITUTION:For example, when key input signals K1 and K2 are inputted successively and a key input signal K3 is inputted with slight delay, key processing is perfored on the basis of the signals K1 and K2. When the signal K2 falls, a falling capacitor 14 is discharged abruptly to stop the output of a signal KEY' from a Schmitt trigger buffer 16 immediately. Then, even when the signal K3 is inputted, it takes a specific time for the level at a point A to reach V1, and a processing circuit 18 outputs an off signal in the falling of the signal KEY' before that, resetting an FF17. Then, the level at the point A attains to V1 to output the signal KEY', the FF17 is set again to turn on a transistor 20, and the circuit 18 is powered on, thereby performing key processing based upon the signal K3.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はキーを1!iffえた′電子機器における電
源制御装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention has a key of 1! This invention relates to a power supply control device for electronic equipment.

〔発明の技術的背景をその問題点〕[Technical background of the invention and its problems]

従来、携帯式電子機器等バッテリー電源にて駆動される
回路に代表されるように省i力指向の電子機器において
は、キー人力待ち中等非動作時電源を回路にてOFF 
L、キー人力特電源を立ち上けて動作開始を行うように
して電源消費の低減化を図かっている。
Conventionally, in power-saving electronic devices, such as portable electronic devices and other circuits driven by battery power, the power supply is turned off by the circuit when the key is not in operation, such as when waiting for human power.
L. The key is to power up the special power source to start the operation, thereby reducing power consumption.

従来、このよりな′電源制御装置としては第1図に示す
ものが知られている。すなわち各キー人力信号に1 、
に2 、・・・Knをオア回路lを介してKEY (m
号として取り出し、そのKEY信号の立ち上が9でD形
フリップ70ツブ2をセットし、そのフリ、ブ′フロッ
プ2のQ出力でPNP形トランジスタ3を付勢し、それ
によって処理回路4へ■。C電源を供給している。また
前記処理回路4には前記各キー人力信号Kl−yKn及
びKEY (q号がそれぞれ入力されている。前記処理
回路4は出方路6子OからOFF化七金山力して1ii
J記フリツゾ70ツブ2をリセットしている。
Conventionally, the one shown in FIG. 1 has been known as this type of power supply control device. i.e. 1 for each key human signal,
2,...Kn through the OR circuit l to KEY (m
The D-type flip 70 block 2 is set at the rising edge 9 of the KEY signal, and the Q output of the flip-flop 2 energizes the PNP transistor 3, thereby sending the signal to the processing circuit 4. . C power is supplied. The processing circuit 4 is also input with the key input signals Kl-yKn and KEY (q) respectively.
I am resetting the J-ki Fritsuzo 70 Tsubu 2.

このようなものにおいて例えば処理回路4がキー処理を
終了すると直ちにOFF信号を出力するように設定する
と、第2図の(a)に示すようにキー人力信号に1 、
に2がある一定の時間をおいて入力される限りは各キー
人力信号に、、K。
In such a device, for example, if the processing circuit 4 is set to output an OFF signal immediately after completing key processing, the key input signal will be 1, as shown in FIG. 2(a).
As long as 2 is inputted after a certain period of time, each key input signal is inputted to K.

の入力釦にソリツブ20ツブ2がセ、1・されてトラン
ジスタ3がオンし、処理回路4に■cC電臨が供給され
てキー処理が行われる。そしてキー処理が終了する毎に
OFF信号によってフリツノフロツノ2がリセットされ
てトランジスタ3がオフし、処理回路4へのvc’c′
中、源の供給が停止される。しかし第2図の(b)に示
すようにキー人力信号Kl の入力中に次のキー人力信
号に2の入力があると最初のキー人力信号に1の立ち上
がり、すなわちKEY信号の立ち上がシに応じてそのキ
ーのキー処理が行われるが、次のキー人力信号に、があ
ってもKEY信号は立ち上がった状態を保持しているた
めフリップフロップ2がキー人力信号に1によるキー処
理が終ってリセットされても次のキー人力信号に2の入
力によってセットされることはなく、このためキー人力
信号Kzにもとづくキー処理が行われなくなる不都合が
あった。
When the input button 20 is set to 1, the transistor 3 is turned on, and the processing circuit 4 is supplied with the ccC signal to perform key processing. Then, each time the key processing is completed, the OFF signal resets the flip-flop 2, turns off the transistor 3, and supplies vc'c' to the processing circuit 4.
During this period, the source supply is cut off. However, as shown in FIG. 2(b), if the next key human input signal is input with a value of 2 while the key human input signal Kl is being input, the first key human input signal will rise to 1, that is, the KEY signal will rise. The key processing for that key is performed according to the key input signal, but even if there is a next key input signal, the KEY signal remains in the raised state, so the flip-flop 2 indicates that the key input signal is 1 and the key processing is completed. Even if the key input signal Kz is reset, it will not be set to the next key input signal by inputting 2, and therefore, there is a problem that key processing based on the key input signal Kz will not be performed.

このため第3図に示すようにKEY信刊が保持されてい
る限シはOFF信号の出力を禁止し、全てのキー人力信
号の入力が無くなってKEY信号が立ち下がったことを
確認してからOFF信号を出力し、キー処理は各キー人
力信号が人力される毎に処理回路4で行うようにすれば
キー人力信号が一部重なってもキー処理を確実に行なう
ことができるようになる。しかしこの方式を使用しても
■Y倍信号立ち下がpを確認してからOFF信号を出力
する壕でには一定の遅延時間tがおるため、第3図に点
線で示すようにこの時間を内において次のキー人力信号
に3の入力があってもそのキー人力で電源がオンされず
、このキー人力信号に3によるキー処理ができなくガる
不都合が生じる。
For this reason, as shown in Figure 3, the output of the OFF signal is prohibited only when the KEY newsletter is held, and only after confirming that all key human input signals have disappeared and the KEY signal has fallen. If the OFF signal is output and key processing is performed by the processing circuit 4 each time each key human signal is input manually, key processing can be performed reliably even if the key human input signals partially overlap. However, even if this method is used, there is a certain delay time t in which the OFF signal is output after the Y-fold signal fall confirms p, so this time is shown by the dotted line in Figure 3. Even if there is an input of 3 in the next key human input signal, the power will not be turned on by that key human input, resulting in the inconvenience that the key 3 cannot be processed for this key human input signal.

〔発明の目的〕[Purpose of the invention]

この発明はこのような問題を解決するために為されたも
ので、各キー人力に対する電源オン制御が確実にできる
電源制御装置を提供することを目的とする。
The present invention has been made to solve such problems, and an object of the present invention is to provide a power supply control device that can reliably perform power-on control for each key manually.

〔発明の概決〕[Summary of the invention]

この発明は最初のキー人力信号の立ち上かりて1柱源を
オン制御するとともに各キー人力信号にもとづいてキー
処理を行い、キー処理後金てのキー人力信号が無くなっ
たことを確認してから′由、源をオフ1lill @す
る′屯d東霜1j偶)装置において、各キー人力信号の
立ち上がりを少なくともキー人力信号が無くなってから
電源がオフ制御される直前に次のキー人力が行われても
そのキー人力イム号の立ち上が9で電源の再オン制御が
できる電源制御装置にある。
This invention controls one pillar source to turn on when the first key human power signal rises, performs key processing based on each key human power signal, and confirms that the key human power signal disappears after key processing. In the device, turn off the power supply at least after the key power signal disappears, and then immediately before the power is turned off, the next key power signal is turned off. The key lies in the power supply control device that can control the power supply to be turned on again at 9 pm when the machine is powered up.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第4図に示すように谷キー人力仏@ K】’ 、 K2
 。
As shown in Figure 4, the valley key human power Buddha @K]', K2
.

・・・Knをオア回路11を介してKEY信号として取
り出し、遅延回路12に供給している。前記遅延回路1
2は抵抗13とコンデンサ14とのCR時定数回路、」
二記抵抗13に並列に接続されたダイオ−トノ5及び上
記コンデンサ14の両端間if圧に応動するシュミット
トリガ′ノN+ 、ファ16で構成されている。前記シ
ーミツトトリガバッファ16の出力KEY’ ヲD形フ
リツノフロップ17のT入力端子に入力するとともに処
理回路18の工。入力端子に入力している。各キー人力
信号KI−Knを前記処理回路J8の11〜In入力端
子に入力している。前記フIJ 、ゾフロップ17の■
)入力端fはvcc端子に接続されている。niJ記フ
リ、ノフロ/f77の4111力g+i八子を抵抗19
を介してPNP形トランジスタ200ベースに接続して
いる。前記トランジスタ20のエミッタを■。、端子に
接続するとともにコレクタを前記処理回路18の■cc
’jIu源入力端子に接続している。前記処理回路18
は前記遅延回路12からのKEY ’信号の立ち下が9
によって全てのキ・−人力終了を確認し、ある時間遅れ
をもって出力端子Oからフリップフロップ17のリセッ
ト端子RにOFF信号を出力する。
. . . Kn is taken out as a KEY signal via the OR circuit 11 and supplied to the delay circuit 12. The delay circuit 1
2 is a CR time constant circuit consisting of a resistor 13 and a capacitor 14.
It is composed of a diode 5 connected in parallel to the second resistor 13, and a Schmitt trigger N+ and F 16 that respond to the IF pressure across the capacitor 14. The output KEY' of the seam trigger buffer 16 is input to the T input terminal of the D-type fritz flop 17 and processed by the processing circuit 18. Input is being made to the input terminal. Each key human input signal KI-Kn is input to input terminals 11 to 11 of the processing circuit J8. Said F IJ, Zoflop 17 ■
) The input terminal f is connected to the vcc terminal. niJki pretend, Nofro/f77's 4111 force g+i Yako resistance 19
It is connected to the base of the PNP transistor 200 via. The emitter of the transistor 20 is (■). , and the collector of the processing circuit 18.
'jIu source input terminal. The processing circuit 18
The falling edge of the KEY ' signal from the delay circuit 12 is 9.
It is confirmed that all key inputs have been completed, and an OFF signal is output from the output terminal O to the reset terminal R of the flip-flop 17 after a certain time delay.

次にこのように構成された不発明実施例の動作について
第5図に基づいて述べる。
Next, the operation of the non-inventive embodiment constructed as described above will be described based on FIG.

例えばキー人力信号に、とに2が連続して人力され、か
つキー人力信号K 3かに2より若干遅れて入力された
とするとオア回路1ノからは図に示すようなKEY信号
が出力され遅延回路12に入力される。遅延回路12で
はKEY信号の入力によってコンデンサ14がF9[定
の時定数をもって充電され、I(EY信ぢの立ち下がり
によってダイオード15を介して急速に放電される。
For example, if the key human input signal K 3 is inputted with a slight delay from 2, the KEY signal as shown in the figure is output from the OR circuit 1 and delayed. It is input to the circuit 12. In the delay circuit 12, the capacitor 14 is charged with a fixed time constant by the input of the KEY signal, and rapidly discharged via the diode 15 by the fall of the I(EY signal).

そしてA点の1/ベルがV、以上になるとシュミットト
リガバッファ16からKEY’信−号が出力され、■2
 (v2くVl )以下になるとシュミノトトリガパ、
ソファ16からのKEY ’信号の出力が停止される。
Then, when 1/bell at point A becomes more than V, the KEY' signal is output from the Schmitt trigger buffer 16, and ■2
When it becomes below (v2kuVl), Shuminotorigapa,
The output of the KEY' signal from the sofa 16 is stopped.

すなわちシュばットトリガパッファI6はV、=V、、
−V2のヒステリシス筆圧をもって動作する。そしてK
EY’信号によってフリツノフロ、flyがセットされ
トランジスタ20がオン感れて処理回路18へのvcc
電温の供給が行われキー人力信号に、、に2にもとづく
キー処理が行われる。ところで岑−人カイij 号K 
2が立ち下7:)(ると■Y倍信号立ち一■・かりコン
テ′ンッ14が急速放電してシュミットトリガバッファ
16からのKEY’信−号の出力が白−ちに停止される
。、その後すぐに次の・V−人力信号に3が入力されて
もA点のL−ベルがvlに達する1でにはBr定の時間
キ要する。しかしてA点のレベルがVlに達する前に処
理回路18はKEY ’ 信号の立ち一トが9によって
OFF信−号を出力しフリノノパフロノフl 7 fリ
セ、]・する。そしてフリツノノロツノ17かリセット
されてからA点のレベルがV、に達してKEY’信号が
出力されフリ、fンロソプ17が杓びセットされてトラ
ンジスタ2θがオンし、処理N路18に■。0′屯4m
が供給されキー人力’lrL @ K 3にもとつくキ
ー処理か実行される3) このように前回のキー人力が終了し1、そ7″l−によ
る電源の供給停止が行われない内に次のキー人力が行わ
れてもそのキー人力が無効になることがなく、そのキー
人力によって確実に′電源の再供給がイ]われてそのキ
ー処理が杓われる。
That is, the Schubat trigger puffer I6 is V, = V, .
- Operates with a hysteresis pen pressure of V2. and K
The fly is set by the EY' signal, the transistor 20 is turned on, and the VCC to the processing circuit 18 is turned on.
Electric temperature is supplied, and key processing is performed based on the key manual signal. By the way, the number K
2 falls 7:) (Then, the Y-fold signal rises to 1), the content 14 is rapidly discharged, and the output of the KEY' signal from the Schmitt trigger buffer 16 is immediately stopped. , even if 3 is input to the next V-human power signal immediately after that, it takes Br constant time for the L-bell at point A to reach vl.However, before the level at point A reaches Vl. Then, the processing circuit 18 outputs an OFF signal when the KEY ' signal goes up to 9, and then the level at point A becomes V. , the KEY' signal is output, the f controller 17 is set, the transistor 2θ is turned on, and the processing N path 18 is turned on.
is supplied and the key processing based on the key human power 'lrL @ K 3 is executed. Even if the next keystroke is performed, the keystroke will not be invalidated, and the power will be resupplied reliably by the keystroke, and the key operation will be canceled.

勿論前回のキー人力が終了しそれによる′亀諒の供給イ
・?止が竹々われだ後に次のキー人力が行われたときに
は従来と同様電源かオンしてそのキー処理が行われる。
Of course, the previous key manpower has ended, and the supply of 'turtles' is due to that? When the next key is pressed after the key is pressed, the power is turned on and the key is processed as before.

〔発明の効果〕〔Effect of the invention〕

以上、この発明によれは各キー人力がどのタイミングで
順次行われても各キー人力に対する′fiJ、dI]t
オン!!il1両オフiiM実にでさる奄綜制御装fi
<<を提供できるものでりる。
As described above, according to the present invention, no matter what timing each key is performed sequentially, 'fiJ, dI]t for each key is
on! ! il1 off iiM real control system fi
It is something that can provide <<.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例Iを示す回路図、第2図(a) 、 (
b)及び第31は従来例における各部の入出力波形図、
第・1図はこの発明の実施例を示う゛回路図、第5崗は
回実施例にお+dる各部の入出力波形図である。 11−21回路、12・・遅延回路、I7・・・フリッ
グフ[+ソゾ、J8・・処理回路、20・PNP形トラ
ンクスタ。 −9′ 第1図 (b) :に1つ友理 : 第3図 第4図
Fig. 1 is a circuit diagram showing conventional example I, Fig. 2(a), (
b) and No. 31 are input/output waveform diagrams of each part in the conventional example,
Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 5 is an input/output waveform diagram of each part in the embodiment. 11-21 circuit, 12...delay circuit, I7...frigf[+Sozo], J8...processing circuit, 20...PNP type trunk star. -9' Figure 1 (b): Niitsu Yuri: Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 最初のキー人力信号の立ち上がυで電源をオン制御する
とともに各キー人力信号にもとづいてキー処理を行い、
キー処理後金てのキー人力信号が無くなったことを確認
してから′電源をオフ制御する電源制御装置において、
各キー人力信号の立ち上が9を少なくともキー人力信号
が無くなってから電源がオン制御jされる壕での時間以
上遅延する遅延回路を設け、肴、源がオフ制御される圓
MiJに次のキー人力が行われてもそのキー人力信号の
立ち上がりで竜のの再オン制御ができることを%徴とす
る電源?tilj御装置。
The power is turned on at the rise of the first key human power signal υ, and key processing is performed based on each key human power signal.
In the power control device that controls the power off after confirming that the key manual signal is no longer present after key processing,
A delay circuit is provided to delay the rise of each key human power signal by at least the time at which the power is turned on after the key human power signal disappears, and the next Even if key human power is performed, is it possible to control the dragon's power on again at the rising edge of the key human power signal? tilj control device.
JP58028225A 1983-02-22 1983-02-22 Power source controller Pending JPS59154519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58028225A JPS59154519A (en) 1983-02-22 1983-02-22 Power source controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58028225A JPS59154519A (en) 1983-02-22 1983-02-22 Power source controller

Publications (1)

Publication Number Publication Date
JPS59154519A true JPS59154519A (en) 1984-09-03

Family

ID=12242664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58028225A Pending JPS59154519A (en) 1983-02-22 1983-02-22 Power source controller

Country Status (1)

Country Link
JP (1) JPS59154519A (en)

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