JPH02189612A - Output interface device - Google Patents

Abstract

PURPOSE:To previously and optionally program the state of an external output terminal immediately after the rise of a power supply or at the time of occurring power failure by providing the output interface with a switching circuit for alternatively outputting an external output signal from a normal output circuit and an external output signal from an emergency external output circuit to an external output terminal. CONSTITUTION:A data latch circuit 17 and an output transistor (TR) 18 constitute the normal output circuit and the circuit 17 latches output data on a data bus synchronously with the rise of a latch circuit 19. A data latch circuit 21 and an output TR 22 constitute the emergency output circuit and the circuit 21 latches the state of an initial output setting part 23 synchronously with the rise of a reset signal 24. When a relay coil 28 is excited, a signal is outputted from the normal output circuit to the external output terminal 31, and when the coil 28 is deexited, a signal is outputted from the emergency output circuit to the terminal 31. Thereby, the state of the external output terminal 31 can be optionally controlled in accordance with set contents of the setting part 23 immediately after the rise of the power supply, at the time of occurring power failure, or at the time of runaway of the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an improvement of an output interface device suitable for a control computer system and the like.

(Prior Art) FIG. 3 is a diagram showing an example of a conventional control computer system.

In this control computer system, -110 processing controllers 1 and a plurality of digital output cards 2 are connected to each other by an M1119 line 3 and an I10 bus 4.

Each digital output card 2 includes an I10 bus interface 21 for connecting with the I10 bus 4, a data latch circuit 22 for latching output data sent from the I10 bus interface 21, and a data latch circuit 22 for latching output data sent from the I10 bus interface 21. An output transistor 23 driven by a signal is provided, and the oven collector output of this output transistor 23 is led out to external output terminals DO+ to Don.

Moreover, FIG. 4 is a diagram showing another example of a conventional control computer system.

This control sieve system is constructed by connecting -110 processing controllers 5 and a plurality of digital output cards 6 to each other via a transmission line 7.

Each digital output card 6 includes a line receiver 10 for receiving serial data taken in from the transmission line 7 and providing it to the transmission control unit 9, and a line receiver 10 for receiving serial data taken in from the transmission line 7 and providing it to the transmission control unit 9, and a line receiver 10 for receiving the serial data taken in from the transmission line 7 and providing it to the transmission control unit 9. A line driver 11 is provided for transmitting the data to.

This digital output card is centrally controlled by a control section including a microprocessor 12 and a memory 13, and the aforementioned transmission control section 9 and data latch circuit 14 are connected to the system bus.

The microprocessor 12 decodes the received data taken in from the transmission control unit 9, reproduces output data, and causes the data latch circuit 14 to latch the output data.

The output transistor 15 is controlled on and off as appropriate by the output data latched by the data latch circuit 14, and its open collector output is connected to the external output terminal DO+-Don.
It is now derived as follows. Note that 16 in the figure is a latch signal.

(Problem to be Solved by the Invention) However, the digital output card 2 shown in FIG.
In this case, immediately after the digital output card 2 is powered on, until the first output data is sent from the I10 processing controller 1, the output data of the data latch circuit 22 is not controlled by the I10 processing controller 1 side. Therefore, a clear pulse is generated in the shell at the same time as the power is turned on, and the data latch circuit 22
By forcibly clearing the external output terminal DO
+~DOn are all set to the off state.

Furthermore, when the power to the digital output card 2 is cut off, the contents of the data latch circuit 22 are not uniquely determined;
For this reason, the output state to the external output terminals Dos to DOn must also become undefined.

Also, in the case of the digital output card 6 shown in FIG. 4, the contents of the data latch circuit 14 are stored in the data latch circuit 14 until the microprocessor 12 writes the first output data to the data latch circuit 14 immediately after the power is turned on.
Therefore, a clear pulse is generated immediately after the power is turned on, and the data latch circuit 1
By forcibly clearing 4, the external output terminal D
It is customary to keep all OI to Don in the off state.

Furthermore, when the power to the digital output card 8 is cut off, the contents of the data latch circuit 14 are not uniquely determined;
Therefore, the states of the external output terminals DO+ to DOn cannot help but become undefined.

Therefore, in the case of FIGS. 3 and 4, if the load connected to the external output terminals DO+ to DOn requests a specific on/off state immediately after power-on or during a power outage, the external output terminals DO1 to Further outside the Don, there is a problem in that a signal state suitable for each load must be forcibly given by inverting the signal as appropriate.

This invention was made in view of the above problems,
The purpose of this is to make it possible to arbitrarily program in advance the state of an external output terminal in this type of output interface device, typified by a digital output card or the like, immediately after power is turned on or during a power outage.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides a common output circuit that generates an external output signal based on output data taken in from a data bus, and a user an emergency output circuit that generates an external output signal based on output data set in advance by a The device is characterized in that it includes a switching circuit that leads to an output terminal.

(Function) According to such a configuration, as long as the user sets the optimal output data for the emergency output circuit in advance, the switching circuit can be activated at power-up or during a power outage, for example. By doing so, the state of the external output signal can be set to the optimum content on a bit-by-bit basis.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a computer interface according to the present invention, and FIG. 2 is a timing chart showing signal states of various parts in the circuit of FIG.

In FIG. 1, data latch circuit 17. The output transistor 18 constitutes a common output circuit of the present invention, and the data latch circuit 17 latches output data on the data bus 20 in synchronization with the rise of the latch signal 19.

The output transistor 18 is connected to the data latch circuit 1.
The on/off control is performed as appropriate based on the output data latched at 7.

Data latch circuit 21. The output transistor 22 constitutes the emergency output circuit of the present invention, and the data latch circuit 21 is configured to latch the state of the initial output setting section 23 in synchronization with the rise of the reset signal 24.

The initial output setting unit 23 sets the contents of each input bit of the data latch circuit 21 to 118 II or "L 11" by connecting the common terminal C to the A side or the B side via a jumper wire, jumper bin, etc. can be set individually.

The output transistor 22 is connected to the data latch circuit 2.
According to the output data of No. 1, on/off control is performed as appropriate.

Furthermore, the data latch circuit 21 can be powered from the voltage vAvcc when the N source is normal, and from the battery 25 during a power outage. Power supply Vcc and battery 2
Power can be supplied from both.

At the rise of the reset signal 19, the D-type flip 70 tube 26 reads the power supply CC, and its Q output is set to H'', and at the fall of the reset signal 24, its Q output is reset to logic LII. It is now possible to do so.

The Q output of this D-type flip 70 tube 26 is “11
'' turns on the relay excitation transistor 27,
A relay coil 28 is driven.

The a contact 29 of this relay coil 28 is connected between the output transistor 18 and the external output terminal 31, and the b contact is connected between the output transistor 22 and the external output terminal 31.

Therefore, when the relay coil 28 is energized, a signal from the normal output circuit is output to the external output terminal 31, whereas when the relay coil 28 is deenergized, the signal from the normal output circuit is output to the external output terminal 31. The signal from the output circuit is output.

Next, the operation of the output interface device having the above configuration will be systematically explained with reference to the timing chart of FIG.

Immediately after the power supply VCC is turned on, a power-on clear circuit (not shown) operates, and the reset signal 24 rises. At the same time, the data latch circuit 21 latches the setting state of the initial output setting section 23. .

In addition, in this state, the D-type flip-flop 26
The Q output of is reset to ''L11, so the transistor 27 is turned off, the relay 28 is deenergized, and the external output terminal 31 is connected to the b contact 30 of the relay 28.
An external output signal corresponding to the latched data of the data latch circuit 21 is sent out via the data latch circuit 21.

Therefore, even after the power is turned on and before the first output data arrives from the data bus 20, the external output terminal 3
The state of 1 is P depending on the output content of the initial output setting section 23.
Ik is controlled to an appropriate state.

Thereafter, when the first output data is sent onto the data bus 20 from a host controller or the like, this output data is latched by the data latch circuit 17 in synchronization with the rise of the latch signal 19.

At the same time, due to the rise of this latch signal 19, the Q output of the D-type flip 70 knob 26 is set to 'H', the transistor 27 is turned on, the relay 28 is energized, and the a
The contact 29 is turned on and the b contact 30 is turned off.

Then, the data latch circuit 17 is connected to the external output terminal 31.
An external output signal corresponding to the output data latched is sent out.

If a power outage etc. occurs after that, the reset signal 2 will be sent immediately after that.
4 falls, and in response to this fall, the Q output of the D-type flip-flop 26 is reset to Ltr.

Then, transistor 27 is turned off, relay 28 is deenergized, its a contact is turned off, and its b contact is turned on.

As a result, during the power outage period, an external output signal corresponding to the latched contents of the data latch circuit 21 is sent to the external output terminal 31.

Furthermore, even when a runaway of the microb 0 setter is detected in the host controller, the same process as in the case of a power outage is performed by the fall of the reset signal 24, and the data latch circuit 21 is connected to the external output terminal 31. An external output signal determined by the latch data is sent.

In this way, according to the device of this embodiment, immediately after the power is turned on,
In the event of a power outage or a runaway microprocessor,
The state of the external output terminal 31 can be arbitrarily controlled according to the settings of the initial output setting section 23, and therefore the optimum signal can be generated for each load connected to the external output terminal 31, taking into account its safe function. can be supplied.

In the above embodiments, the initial output setting section 23 connects the common terminal C to the terminal A or terminal B using wires, Yamba wires, jumper pins, etc., but the configuration of the initial output setting section is as follows. It goes without saying that the memory is not limited to , and may be replaced with FROM, such as a fuse ROM, for example.

[Effects of the Invention] As is clear from the above explanation, according to the output interface device of the present invention, even when the power is turned on, during a power outage, or when the microprocessor runs out of control, the Optimal signals can be sent out.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an output interface according to the present invention, FIG. 2 is a timing chart showing signal states of each part in FIG. 1, and FIGS. 1 is a circuit diagram showing the configuration of a conventional control computer system. 17.21...Data latch circuit 18.22...Output transistor 19...Latch signal 20...Data bus 23...Initial output setting section 24...Reset signal 25...Battery 26...・D-type flip-flop 27 ・Relay excitation transistor 28 ・Relay coil 29 ・A contact 30 ・B contact 31 ・External output terminal Fig. 3

Claims (1)

[Claims] A regular output circuit that generates an external output signal based on output data fetched from the data bus, an emergency output circuit that generates an external output signal based on output data set in advance by the user, and a An output interface device comprising: a switching circuit that selectively outputs an external output signal from the emergency external output circuit and an external output signal from the emergency external output circuit to an external output terminal.