JPS59154487A - Buffer memory writing timing control system for crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a display device using a cathode ray tube (CRT), and particularly relates to a data write timing control method (b) technology for a cathode memory of the display device. Background In a CRT display device, the screen information stored in the memory is refreshed and displayed, but writing information to the memory is generally done by
This is performed by switching the control circuit and data from the control circuit section-panzer memory side to the central processing unit-panzer memory side during the vertical retrace period.

(C) Prior art and problems Conventionally, the switching timing of the address bus and data bus that occurs when writing to the buffer memory is the first
As shown in the figure, this is done by detecting the vertical synchronizing signal (Sv) added to the vertical retrace period (Vr), and during the duration of this signal, both lotuses are switched and writing to the ζ buffer memory is performed. It was done.

However, the duration of the vertical synchronization signal (Sv) is approximately 1
It is about 50m5ec, which is about 1 of the vertical retrace period (Vr).
/10 hours could only be used effectively. For this reason, the amount of data that can be written into the buffer memory at two times is sufficiently large, and as a result, there is a drawback that the data writing/changing speed cannot exceed iFu.

In addition, in order to write the required amount of data, it was necessary to change the lotus frequently, and as a result, the display screen flickered during the eastward return period, resulting in a decrease in the quality of the display. .

In addition, in FIG. 1, llr indicates a horizontal synchronization period.

(d) Object of the Invention The present invention makes it possible to use almost the entire vertical retrace period as a writing period to the buffer memory, thereby making it possible to write the necessary amount of data at crystal speed, and Virtually eliminates the occurrence of flickering
The purpose is to provide a Nofa memory recessed timing control system.

(e) Structure of the invention The non-invention is to detect the start of a vertical blanking period starting from a blanking period signal and switch the address bus and data bus to the central processing unit-buffer memory side, and to It is characterized by detecting the end and returning the address bus and data bus to the control circuit/buffer memory side.It is characterized in that it includes a counter for counting character chronographs and a predetermined value for the contents of the counter. A gate circuit that outputs an on signal when the signal is turned on, and a latch circuit that is latched by the on signal output of the gate I-circuit are installed, and the blanking period signal is turned on during the horizontal synchronization period of the blanking period signal. When the contents of the counter reach a predetermined value during the vertical retrace period, the latch circuit is latched, and the launch circuit output at this time is used as a flag to clear the address bus and the data bus. It is characterized by switching between the central processing unit and the buffer memory side.

(f) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a write control circuit according to the present invention. Similar to a normal C1 side display device, the address bus and data bus for the buffer memory 1 are connected to the central processing unit 2.
and a gate circuit 4 for switching between the control circuit section 3 and the control circuit section 3.
and 5 are provided.

On the other hand, in the present invention, the clock signal generating circuit 6 and the clock signal (CLK) from the clock signal generating circuit 6 are divided into 16 by the control circuit section 3 to generate a character. IJ 7 signal (CII
CL), an AND gate circuit 8 which outputs an on signal when the content of the color/tough reaches a predetermined value, and an AND gate circuit 8 which outputs an ON signal when the content of the color/tough reaches a predetermined value; - A launch circuit 9 that outputs switching signals (flags) for circuits 4 and 5 is installed every month.

Note that the retrace period signal (Di
sp) is input.

The operation of the circuit configured as shown in FIG. 2 will be explained with reference to the timing chart shown in FIG.

FIG. 3(A) is an enlarged view of the horizontal synchronization period (Ib) shown in FIG. The pulse width and period at the second time are, for example, 20 μsec and 40 μsec, respectively.

The counter 7 receives an input gear actuator cross signal (C
IICL) to 1- or retrace period signal (Dis
p) is on, its contents are cleared. −
During the period in which the retrace period signal (Disp) is off, signals Qa, Qb, and Oc (not shown in FIG. 3) are output to the three output digits Oa, Ob, and DC; O
Immediately before all of c are turned on, the retrace period signal (Dis[
1) Since the respective operation timings are set in such a relationship that either is turned on, the contents of the carantuff are cleared.

Therefore, in the horizontal synchronization period (fir), the A
NI) The output (Gout) of the gate circuit 8 never turns on, and as a result, the output (f)L of the latch circuit 9
) is off, ie the flags toggling the goo 1-times M&4; and 5 are not generated.

In addition, Oa, Kano, Qc and retrace period signal (D
The timing setting with Qa is as shown in the figure.
, Qb, and Oc, and the timing at which the fourth Oa is output after the blanking period signal (11i sp ) is turned off is determined by the jM line period signal (1) isp ), or set the most significant digit Qc to Qa,
This can be achieved by selecting a digit in the ``-'' position that is not consecutive with Qb.

On the other hand, the direct return line (Vr) is the horizontal synchronization period (fir)
Since the period in which the retrace period signal (Disp) is off is longer than the off period, when the horizontal synchronization period (Ilr) ends and enters the vertical retrace period (Vr), as shown in the figure (I3), There is a timing when Qa, Qb, and Oc are all turned on.

When Oa, Kano, and Qc all turn on, the output (Gout) of ANI) Lee-1-circuit 8 turns on and becomes dirty. l, the output (91,) of the latch circuit 9 is on, and the flag for switching the circuits 4 and 5 is output.

At the end of the vertical retrace period (V+r), the retrace period signal (
When Disp) is turned on, the latch 1 bit 9 is cleared and the flag is turned off, so the gate circuits 4 and 5 are switched to the control circuit section 3 - buffer memory 1 side, and the contents of the buffer memory 1 are transferred to the control circuit section. 3.

As described above, the central processing unit is operated during substantially the entire vertical retrace period from when the flag 111 is generated during the vertical retrace period until the end of 5.8 of the vertical retrace period. 2
The above operation for the buffer memory 1 is performed from J to J, resulting in a two-point function.

FIG. 4 is a diagram showing another embodiment of the present invention, in which the gate circuits 4 and 5 are switched by a flag outputting the latch circuit 9 in the same manner as in FIG. When directly transferring the write address and data to the buffer memory 1 from the external input/output device II (such as a floppy disk device) under the control of the memory access (11 old) control circuit 10 shows.

This makes it possible to write more display information in a shorter time than in the case of writing to the central processing unit with two interventions as shown in FIG.

(g) Effects of the Invention According to the present invention, the amount of data written in one vertical blanking period is large, and the amount of data written in one vertical blanking period is large. It also reduces the number of cycles in the vertical blanking period used to write a certain amount of data, and substantially eliminates flickering on the display screen during the vertical blanking period. As a result, display quality can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of the retrace period signal 5, Fig. 2 is a circuit block diagram of the Taizo timing control force type according to the present invention for buffer memory, and Fig. 31 is a circuit block diagram of the Taizo timing control force type according to the present invention. FIG. 4 is a diagram showing another embodiment of the present invention. In the figure, 1 is a buffer memory, 2 is a central processing unit,
3 is a control circuit section, 4 and 5 are data 1 circuits, 6 is a clock signal generation circuit, 7 is a counter, 8 is an AND gate circuit, 9 is a latch circuit, i (l is l) M A control circuit, 1
1 is an input/output device. zu'f, tlwa1 skewer? Shi1'! , 3 closed (/l)

Claims (2)

[Claims] (1) Detecting the start of the vertical blanking period of the blanking period signal, switching the address bus and data bus to the central processing unit-panzer memory side, detecting the end of the vertical blanking period, and switching the address bus and data bus to the central processing unit-panzer memory side. A buffer memory write timing control method for a CRT display device, characterized in that the output data is returned to the control circuit--panzer memory side. (2) A counter that counts character clock signals, a data 1-circuit that outputs an on signal when the contents of the counter reach a predetermined value, and a data circuit that outputs an on signal when the content of the counter reaches a predetermined value. During the horizontal synchronization period of the blanking period signal, the counter and the latch circuit are cleared each time the blanking period signal is turned on, and the content of the counter iii becomes a predetermined value in the vertical blanking period. Buffer memory writing in a CRT device according to claim 1, characterized in that the corresponding child circuit is latched and the output of the corresponding child circuit at this time is used as a flag to switch the address bus and the data bus. Timing control method.