JPS59154064A - Metal insulator semiconductor device and manufacture thereof - Google Patents
Metal insulator semiconductor device and manufacture thereofInfo
- Publication number
- JPS59154064A JPS59154064A JP2756883A JP2756883A JPS59154064A JP S59154064 A JPS59154064 A JP S59154064A JP 2756883 A JP2756883 A JP 2756883A JP 2756883 A JP2756883 A JP 2756883A JP S59154064 A JPS59154064 A JP S59154064A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- lift
- source
- drain
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052751 metal Inorganic materials 0.000 title claims description 3
- 239000002184 metal Substances 0.000 title claims description 3
- 239000012212 insulator Substances 0.000 title 1
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000007769 metal material Substances 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
この発明は、高速化に適したＭＩＳ半導体装置およびそ
の製造技術、特に、パンチスルー・ストッパとして、ソ
ース、ドレイン間のチャネル部のみに高濃度不純物層を
有するＭＩＳ半導半導体装製置造する上で有効な技術に
関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a MIS semiconductor device suitable for speeding up and its manufacturing technology, and in particular, to a method of forming a highly concentrated impurity layer only in the channel region between the source and drain as a punch-through stopper. The present invention relates to an effective technique for manufacturing MIS semiconductor devices having the following.
［背景技術］
高集積化が進み、また高周波特性の改善のため、デバイ
スのチャネル長が短縮化されているが、それに伴なって
ソース、ドレインの電気的突き抜け（パンチスルー）の
問題が生じている。[Background Art] With the advancement of higher integration and the improvement of high frequency characteristics, the channel length of devices is being shortened, but this has led to the problem of electrical punch-through of sources and drains. There is.
このパンチスルーの問題は、トレインと基板との間の接
合逆電圧による空乏層の拡がりに起因する。そこで、そ
の問題を解決する方法の一つとして、チャネル部を基板
よりも高濃度化する手法が考えられる。This punch-through problem is caused by the expansion of the depletion layer due to the junction reverse voltage between the train and the substrate. Therefore, one possible method to solve this problem is to make the channel portion higher in concentration than the substrate.
しかし、従来では、半導体基板表面のうち、活性領域の
全域に不純物をイオン打込みし、その後にソース、ドレ
インを形成するという方法が採られている。パンチスル
ーを防止するには、不純物層の深さをソースおよびトレ
インよりも深くすることが有効である。これを従来の手
法によって行なうと、厚いフィールド酸化膜をマスクと
してアクティブエリア全体に不純物をイオン打込みする
ことになり、ドレイン−基板間の静電容量を大きくし高
周波特性を劣化させるという問題を生じてしまう。However, conventionally, a method has been adopted in which impurity ions are implanted into the entire active region of the surface of a semiconductor substrate, and then a source and a drain are formed. To prevent punch-through, it is effective to make the impurity layer deeper than the source and train. If this is done using the conventional method, impurity ions are implanted into the entire active area using a thick field oxide film as a mask, resulting in the problem of increasing the capacitance between the drain and the substrate and deteriorating the high frequency characteristics. Put it away.
このような高周波特性の劣化の問題を解決するには、チ
ャネル部のみを高濃度化する方法が良いと考えられる。In order to solve this problem of deterioration of high frequency characteristics, it is thought that a method of increasing the concentration only in the channel portion is considered to be a good method.
［発明の目的コ
この発明は以上の検討の上になされたもので、その目的
はチャネル部のみを高濃度化する上で有効な技術を提供
することにある。[Purpose of the Invention] The present invention has been made based on the above considerations, and its purpose is to provide an effective technique for increasing the concentration only in the channel portion.
この発明の前記ならびにそのほかの目的と特徴は、この
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
この出願において開示される発明のうち、代表的なもの
の概要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.
すなわち、この発明にあっては、ゲートの形成をリフト
オフ法によって行ない、リフトオフ材料を用いてチャネ
ル部のみに不純物をイオン打込みすることによって、前
記チャネル部の不純物層を自己整合的に形成するもので
ある。That is, in this invention, the gate is formed by a lift-off method, and the impurity layer in the channel part is formed in a self-aligned manner by implanting impurity ions only in the channel part using a lift-off material. be.
［実施例］
以下、この発明の一実施例を添付図面を参照しながら説
明する。[Embodiment] An embodiment of the present invention will be described below with reference to the accompanying drawings.
まず、従来と同様にしてＰ−型のシリコン半導体基板１
の表面に、厚いフィールド酸化膜２およびゲートの絶縁
膜となる薄い熱酸化膜３を形成し、その上に第１図に示
すように、リフトオフ材料４を選択的に形成する。リフ
トオフ材料４は、ゲートを形成すべき部分以外を１μｍ
程度と厚く被う。First, as in the conventional case, a P-type silicon semiconductor substrate 1 is prepared.
A thick field oxide film 2 and a thin thermal oxide film 3 serving as a gate insulating film are formed on the surface of the semiconductor device, and a lift-off material 4 is selectively formed thereon as shown in FIG. The lift-off material 4 has a thickness of 1 μm except for the part where the gate is to be formed.
Cover it fairly thickly.
リフトオフが容易であることおよびリフトオフ時等に絶
縁膜３を傷めないことなどがらすると、リフトオフ材料
４としては、アルミニウム等の無機物よりもホトレジス
ト等の有機物の方が好ましい。Considering that lift-off is easy and that the insulating film 3 is not damaged during lift-off, an organic material such as photoresist is preferable to an inorganic material such as aluminum as the lift-off material 4.
ついで、第１図に示すように、リフトオフ材料４をイオ
ン打込みに対するマスクとして基板１の表面上に選択的
にボロン等のＰ型不純物を打込み、チャネル部相当域に
Ｐ型の不純物層６を形成する。Next, as shown in FIG. 1, using the lift-off material 4 as a mask for ion implantation, P-type impurities such as boron are selectively implanted onto the surface of the substrate 1 to form a P-type impurity layer 6 in a region corresponding to the channel portion. do.
この不純物層６の最終的な拡散深さについては、たとえ
ば０．５〜０．８μｍ程度と、後述するソース７および
ドレイン８の拡散深さくたとえば０．２μｍ）よりも深
くする。The final diffusion depth of this impurity layer 6 is, for example, about 0.5 to 0.8 μm, which is deeper than the diffusion depth of the source 7 and drain 8 (for example, 0.2 μm), which will be described later.
Ｐ型の不純物層６を形成した後、第２図に示すように、
リフトオフ材料４を含む基板１の上面全体にゲート形成
用金属材料５を堆積する。金属材料５としては、ソース
７、ドレイン８の拡散領域を形成する際の熱処理に充分
に酎えうるものを用いるのが良く、モリブデンあるいは
タングステン等のような高融点金属が良い、。またこの
場合、リフトオフを容易にするため、ゲート部のもの５
１とそれ以外のもの５２とが不連続となるよう、金属材
料５の厚さをリフトオフ材料４よりも薄くする。After forming the P-type impurity layer 6, as shown in FIG.
A gate-forming metal material 5 is deposited over the entire upper surface of the substrate 1 including the lift-off material 4 . As the metal material 5, it is preferable to use a material that can be sufficiently processed for heat treatment when forming the diffusion regions of the source 7 and drain 8, and a high melting point metal such as molybdenum or tungsten is preferable. In this case, in order to facilitate lift-off, the gate part 5
The thickness of the metal material 5 is made thinner than the lift-off material 4 so that 1 and the other material 52 are discontinuous.
こうした後、リフトオフ材料４を溶解することによって
、リフトオフ材料４およびその上の金属材料部分５２を
除去する。残った金属材料部分５１がゲートを構成する
ことになる。そこで、第３図に示すように、ゲート部の
金属材料５１をイオン打込みに対するマスクとして公知
の方法によってともにＮ型のソース７およびドレイン８
を形成する。そして、表面をリンシリケートガラス膜等
の層間絶縁膜で覆った後、図示しないソース７、ドレイ
ン８へのアルミニウム配線等を形成することによって、
デバイス（ＭＯＳＦＥＴ）を完成する。After this, the lift-off material 4 and the metal material portion 52 thereon are removed by melting the lift-off material 4. The remaining metal material portion 51 will constitute the gate. Therefore, as shown in FIG. 3, by using the metal material 51 of the gate portion as a mask for ion implantation, both the N-type source 7 and drain 8 are implanted using a known method.
form. Then, after covering the surface with an interlayer insulating film such as a phosphosilicate glass film, aluminum wiring etc. to the source 7 and drain 8 (not shown) are formed.
Complete the device (MOSFET).
［効果］
この発明によれば、チャネル部のみにパンチスルー・ス
トッパとしての高濃度層を形成するようにしているので
、パンチスルーを有効に防止しうるのは勿論のこと、静
電容量増大の問題をも回避することができる。チャネル
部のみに高濃度不純物層を形成する方法としては、ゲー
トの形成前あるいは後においてホトレジストをマスクと
してイオン打込みする方法等も考えられるが、この発明
では特に、ゲートの形成をリフトオフ法によって行ない
、それに用いるリフトオフ材料をマスクとして前記チャ
ネル部の不純物層を形成するようにしているので、その
不純物層を自己整合的し；形成することができる。゛
以上この発明者によってなされた発明を実施例に基づき
具体的に説明したが、この発明は前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。[Effects] According to the present invention, since a high concentration layer is formed as a punch-through stopper only in the channel portion, it is possible to effectively prevent punch-through as well as to prevent an increase in capacitance. Problems can also be avoided. As a method of forming a high concentration impurity layer only in the channel region, there may be a method of implanting ions using a photoresist as a mask before or after forming the gate, but in this invention, in particular, the gate is formed by a lift-off method, Since the impurity layer of the channel portion is formed using the lift-off material used as a mask, the impurity layer can be formed in a self-aligned manner.゛Although the invention made by this inventor has been specifically explained based on examples, it is to be noted that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Not even.
［利用分野］
この発明は、高速メモリ用ＭＯ８ＩＣをはじめ、半導体
基板上の電極によって基板内の電荷を制御する型の半導
体装置に広範に適用することができる。[Field of Application] The present invention can be widely applied to semiconductor devices of a type in which charges within a semiconductor substrate are controlled by electrodes on the semiconductor substrate, including MO8ICs for high-speed memories.
第１項〜第３図はこの発明の一実施例を工程順に示す断
面図である。
１・・・半導体基板（Ｐ−型のシリコン半導体基板）、
２・・・フィールド酸化膜、３・・・絶縁膜（熱酸化膜
）、４・・・リフトオフ材料、５・・・ゲート形成用金
属材料、５１・・・ゲート、６・・・チャネル部の不純
物層（Ｐ型の不純物層）、７・・・ソース、８・・・ド
レイン。
第 １ 図
第 ３ 図Items 1 to 3 are cross-sectional views showing an embodiment of the present invention in the order of steps. 1... semiconductor substrate (P-type silicon semiconductor substrate),
2... Field oxide film, 3... Insulating film (thermal oxide film), 4... Lift-off material, 5... Metal material for gate formation, 51... Gate, 6... Channel portion Impurity layer (P-type impurity layer), 7...source, 8...drain. Figure 1 Figure 3
Claims (1)
ドレインの拡散領域と、ソース、ドレイン間のチャネル
部上に絶縁膜を介して形成されたゲートとを有するＭＩ
Ｓ半導体装置において、前記チャネル部のみに、前記半
導体基板と同一型でその基板よりも高濃度であって、そ
の深さが前記ソース、ドレイン拡散領域と同程度以上の
不純物層が形成されていることを特徴とするＭＩＳ半導
体装置。 ２、半導体基板表面に互いに隔てて形成されたソース、
ドレインの拡散領域と、ソース、ドレイン間のチャネル
部上に絶縁膜を介して形成されたゲートとを有するＭＩ
Ｓ半導体装置の製造方法において、前記チャネル部のみ
に、前記半導体基板と同一型でその基板よりも高濃度の
不純物層を、次の各工程を順次繰て形成することを特徴
とするＭＩＳ半導体装置の製造方法。 （Ａ）半導体基板表面を被う絶縁膜上、ゲートを形成す
べき部分以外をリフトオフ材料で被い、そのリフトオフ
材料をイオン打込みに対するマスクとして前記チャネル
部の不純物層を形成する工程。 （Ｂ）リフトオフ材料を含む半導体基板の上面全体にゲ
ート形成用金属材料を堆積する工程。 （Ｃ）前記リフトオフ材料およびその上の前記金属材料
を除去することによってゲートを形成する工程。 （Ｄ）形成したゲートをイオン打込みに対するマスクと
してソースおよびドレインを形成する工程。 β、前記不純物層の拡散深さは、前記ソース、トレイン
の拡散領域のそれと同程度以上である特許請求の範囲第
２項に記載のＭＩＳ半導体装置の製造方法。 ４、前記ゲート形成用金属材料は、前記ソース、ドレイ
ンの拡散領域を形成する際の熱処理に酎えうる高融点金
属である特許請求の範囲第２項あるいは第３項に記載の
ＭＩＳ半導体装置の製造方法。[Claims] ■. Sources formed on the surface of the semiconductor substrate at a distance from each other;
MI having a drain diffusion region and a gate formed on the channel part between the source and the drain with an insulating film interposed therebetween.
In the S semiconductor device, an impurity layer having the same type as the semiconductor substrate, having a higher concentration than the substrate, and having a depth equal to or more than the source and drain diffusion regions is formed only in the channel portion. A MIS semiconductor device characterized by the following. 2. Sources formed apart from each other on the surface of the semiconductor substrate;
MI having a drain diffusion region and a gate formed on the channel part between the source and the drain with an insulating film interposed therebetween.
S semiconductor device manufacturing method, characterized in that an impurity layer of the same type as the semiconductor substrate and with a higher concentration than the substrate is formed only in the channel portion by sequentially repeating the following steps: manufacturing method. (A) A step of covering the insulating film covering the surface of the semiconductor substrate with a lift-off material other than the portion where the gate is to be formed, and using the lift-off material as a mask for ion implantation to form an impurity layer for the channel portion. (B) Depositing a gate-forming metal material over the entire top surface of the semiconductor substrate including lift-off material. (C) forming a gate by removing the lift-off material and the metal material thereon; (D) A step of forming a source and a drain using the formed gate as a mask for ion implantation. 3. The method of manufacturing an MIS semiconductor device according to claim 2, wherein the diffusion depth of the impurity layer is approximately equal to or greater than that of the source and train diffusion regions. 4. The MIS semiconductor device according to claim 2 or 3, wherein the metal material for forming the gate is a high melting point metal that can be used in heat treatment when forming the source and drain diffusion regions. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2756883A JPS59154064A (en) | 1983-02-23 | 1983-02-23 | Metal insulator semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2756883A JPS59154064A (en) | 1983-02-23 | 1983-02-23 | Metal insulator semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59154064A true JPS59154064A (en) | 1984-09-03 |
Family
ID=12224619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2756883A Pending JPS59154064A (en) | 1983-02-23 | 1983-02-23 | Metal insulator semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154064A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6163057A (en) * | 1994-08-17 | 2000-12-19 | Nec Corporation | Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance |
-
1983
- 1983-02-23 JP JP2756883A patent/JPS59154064A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6163057A (en) * | 1994-08-17 | 2000-12-19 | Nec Corporation | Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance |
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