JPS59154027A - Formation of metal pattern - Google Patents
Formation of metal patternInfo
- Publication number
- JPS59154027A JPS59154027A JP2874283A JP2874283A JPS59154027A JP S59154027 A JPS59154027 A JP S59154027A JP 2874283 A JP2874283 A JP 2874283A JP 2874283 A JP2874283 A JP 2874283A JP S59154027 A JPS59154027 A JP S59154027A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- forming
- metal
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造工程などにおいて、実施さ
れる写真製版技術による金属パターンの形成方法の改良
に関するものである０
以下、半導体装置における電極配線パターンの形成の場
合を例にとって説明する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an improvement in a method for forming metal patterns by photolithography, which is carried out in the manufacturing process of semiconductor devices. An example of forming a pattern will be explained.
半導体装置の電極配線の材料としてはアルミニウムまた
はアルミニウム合金が一般に用いられているが、光の反
射率が高いので、写真製版技術による耐エツチング性ホ
トレジストマスクのノくターン形成が難しがった。第１
図および第２図は従来の電極配線パターン形成方法を説
明するための斜視図で、（１）は表面に段差部を有する
下地基板、（２）はその上面に形成されたアルミニウム
層、（３）は更にその上に形成された耐エツチング性ホ
トレジストマスクである。このホトレジストにポジティ
ブ形を用いると、写真製版技術によるノくターニング時
に、アルミニウム層（２）上面からの光の反射によって
、第１図に示すように特に段差部においてノくターン寸
法が細くなり、このホトレジストマスク（３）を用いて
アルミニウム層（２）にエツチングを施すと、第２図に
示すように電極配線パターン（２ａ）も当然段差部にお
いて寸法が細くなる。Aluminum or aluminum alloy is generally used as a material for electrode wiring in semiconductor devices, but because of its high light reflectance, it has been difficult to form a pattern in an etching-resistant photoresist mask using photolithography. 1st
2 and 2 are perspective views for explaining the conventional electrode wiring pattern forming method, in which (1) is a base substrate having a stepped portion on its surface, (2) is an aluminum layer formed on its upper surface, and (3) is a base substrate having a stepped portion on its surface. ) is an etch-resistant photoresist mask formed thereon. When a positive type photoresist is used, when turning the photoresist using photolithography, the reflection of light from the top surface of the aluminum layer (2) causes the turn dimensions to become narrower, especially at the stepped portions, as shown in Figure 1. When the aluminum layer (2) is etched using this photoresist mask (3), the dimensions of the electrode wiring pattern (2a) will naturally become thinner at the stepped portions, as shown in FIG.
そこで、従来アルミニウム層（２）の表面の反射率を下
げること、およびエツチング時のマスク材の補助として
、低温で形成されることから、プラズマＯＶＤで形成さ
れたシリコン窒化膜が用いられていた。しかし、このシ
リコン窒化膜形成時にアルミニウムにグレインを発生さ
せ、パターン形成や電極配線としての電気特性に悪影響
を与えるという欠点があった。また、シリコン窒化膜に
は導電性がないので、電極配線から、他の電極配線へ、
または外部へ電極を引き出すときには上記アルミニウム
の上のシリコン窒化膜を除去しなければならないなどの
欠点があった。Therefore, conventionally, a silicon nitride film formed by plasma OVD has been used to lower the reflectance of the surface of the aluminum layer (2) and as an auxiliary mask material during etching because it can be formed at a low temperature. However, when forming this silicon nitride film, grains are generated in aluminum, which has a disadvantage in that it adversely affects pattern formation and electrical characteristics as electrode wiring. Also, since silicon nitride film has no conductivity, it is difficult to connect electrode wiring to other electrode wiring.
Another disadvantage is that the silicon nitride film on the aluminum must be removed when the electrodes are drawn out.
この発明は以上のような点に鑑みてなされたもので、ア
ルミニウムまたはその合金などの光反射率の大きい第１
の金属層の上に低反射率の第２の金属膜を形成した上で
面ｊエツチング性ホトレジストマスクのパターンを形成
することによって、このマスクパターンの形成も容易で
、第１の金属層のパターン形成や電気特性に悪影響を与
えない金属パターンの形成方法を提供するものである。This invention was made in view of the above points, and the first material having a high light reflectance, such as aluminum or its alloy,
This mask pattern can be easily formed by forming a second metal film with a low reflectance on the metal layer, and then forming a surface-etchable photoresist mask pattern. The present invention provides a method for forming a metal pattern that does not adversely affect the formation or electrical characteristics.
第３図および第４図はこの発明の一実施例を説明するた
めの斜視図で、第１図および第２図の従来例と同等部分
は同一符号で示す。この実施例では表面に段差部を有す
る下地基板（１）の上面に形成されたアルミニウム層（
２）の上に低反射率の□高融点金属膜（４）が形成され
、耐エツチング性ホトレジストマスク（３）はその高融
点金属膜（４）の上に形成される。この場合、高融点金
属膜（４）はアルミニウムに比して光の反射率が低いの
で、ホトレジストマスク（３）のバターニングは容易で
あり、下地基板ｆｔｌの段差の有無にかかわらず、所望
のパターンが正確に得られ、第１図の従来例のように段
差部で幅が狭くなるようなことがない。従って、このホ
トレジストマスク（３）を用いて高融点金属膜（４）お
よびアルミニウム層（２）に異方性ドライエツテンクを
施すことによって、第４図に示すように７１ｉ望の形状
の高融点金属パターン（４ａ）およびアルミニウムパタ
ーン（２ａ）が得られる。3 and 4 are perspective views for explaining an embodiment of the present invention, and parts equivalent to those of the conventional example shown in FIGS. 1 and 2 are designated by the same reference numerals. In this example, an aluminum layer (
A □ high melting point metal film (4) with low reflectivity is formed on top of 2), and an etching-resistant photoresist mask (3) is formed on the high melting point metal film (4). In this case, since the high melting point metal film (4) has a lower light reflectance than aluminum, patterning of the photoresist mask (3) is easy, and regardless of the presence or absence of a step on the base substrate ftl, the desired pattern can be obtained. The pattern can be accurately obtained, and the width does not become narrow at the stepped portions as in the conventional example shown in FIG. Therefore, by applying anisotropic dry etching to the high melting point metal film (4) and the aluminum layer (2) using this photoresist mask (3), a high melting point metal pattern with a desired shape of 71i is formed as shown in FIG. (4a) and an aluminum pattern (2a) are obtained.
この場合、高融点金属も導電体であるから、除去する８
喪がなく、配線材料の一部として用いることができる。In this case, since the high melting point metal is also a conductor, it is removed.
There is no trace, and it can be used as part of the wiring material.
更に、アルミニウムからのホイスカおよびヒルロックの
発生を抑えることもでき、アルミニウム中のグレインの
発生も抑えることができる。高融点金属としてはモリブ
デン、タングステン、チタン、メンタル、コバルトなど
が用いられる。Furthermore, the generation of whiskers and hillocks from aluminum can be suppressed, and the generation of grains in aluminum can also be suppressed. Molybdenum, tungsten, titanium, mental, cobalt, etc. are used as the high melting point metal.
上記説明では電極配線用主材としてアルミニウムを用い
たが、アルミニウム合金を用いてもよく、更にその上に
形成する低反射率の膜に高融点金属を用いたが、高融点
金属膜の代わりに高融点金属のシリサイド（例えば、モ
リブデンシリサイド。In the above explanation, aluminum was used as the main material for the electrode wiring, but an aluminum alloy may also be used, and a high-melting point metal was used for the low reflectance film formed on it, but instead of the high-melting point metal film. Refractory metal silicides (e.g. molybdenum silicide).
タングステンシリサイド等）膜を用いてもよい。A film (such as tungsten silicide) may also be used.
なお、この発明は半導体装置の電極配線パターンに限ら
ず、金属パターンの形成一般に広く適用できる。Note that the present invention is not limited to electrode wiring patterns of semiconductor devices, but can be widely applied to the formation of metal patterns in general.
以上説明したように、この発明で１は比較的に光反射率
の大きい第１の金属層の上に、低反射率の第２の金属膜
を形成しその上にホトレジストマスクのパターンを形成
するようにしたので、そのパターンは精度よく形成でき
、これをマスクとしてエツチングを施して得られる金属
パターンも精度よく容易に形成できる。As explained above, in the present invention, 1 forms a second metal film with a low reflectance on a first metal layer with a relatively high light reflectance, and forms a photoresist mask pattern thereon. Therefore, the pattern can be formed with high precision, and the metal pattern obtained by etching using this as a mask can also be easily formed with high precision.
第１図および第２図は従来の電極配線パターン（金属パ
ターン）形成方法を説明するための斜視図、第３図およ
び第４図はこの発明の一実施例を説明するための斜視図
である。
図において、（１）は下地基板、（２）はアルミニウム
１−（第１の金属の増）、＋３］はホトレジストマスク
、（４）は高融点金属膜（第２の導電性膜）である。
なお、図中同一符号は同一または相当部分を示す０
代理人 葛 野 信 −（外１名）第１図
第３図1 and 2 are perspective views for explaining a conventional electrode wiring pattern (metal pattern) forming method, and FIGS. 3 and 4 are perspective views for explaining an embodiment of the present invention. . In the figure, (1) is the base substrate, (2) is aluminum 1- (first metal increase), +3] is a photoresist mask, and (4) is a high melting point metal film (second conductive film). . In addition, the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
の第２の導電性膜の上に写真製版技術によって耐エツチ
ング性のホトレジスト膜からなる所望パターンのマスク
を形成し、このマスクを介して上記第２の導電性膜およ
び上記第１の金属の層にドライエツチングを施すことを
特徴とする金属パターンの形成方法。 （２）第１の金属にアルミニウムを用いることを特徴と
する特許請求の範囲第１項記載の金属パターンの形成方
法。 （３） 第１の金属にアルミニウム合金を用いること
を特徴とする特許請求の範囲第１項記載の金属パターン
の形成方法。 （４）第２の導電性膜に高融点金属膜を用いることを特
徴とする特許請求の範囲第１項ないし第３項のいずれか
に記載の金属パターンの形成方法。 （５）第２の導電性膜に高融点金属のシリサイド膜を用
いることを特徴とする特許請求の範囲第１項ないし第３
項のいずれかに記載の金属パターンの形成方法。 （６） 高融点金属にモリブデンを用いることを特徴
とする特許請求の範囲第４項または第５項記載の金属パ
ターンの形成方法。 （７） 高融点金属にタングステンを用いることを特
徴とする特許請求の範囲第４項または第５項記載の金属
パターンの形成方法。 （８） 高融点金属にチタンを用いることを特徴とす
る特許請求の範囲第４項または第５項記載の金属パター
ンの形成方法。 （９） 高融点金属にタンタルを用いることを特徴と
する特許請求の範囲第４項または第５項記載の金属パタ
ーンの形成方法。 （１０）高融点金属にコバルトを用いることを特徴とす
る特許請求の範囲第４項または第５項記載の金属パター
ンの形成方法。[Claims] +l) A mask with a desired pattern made of an etching-resistant photoresist film is formed by photolithography on the second conductive film having a relatively high light reflectance on the base substrate. . A method for forming a metal pattern, comprising performing dry etching on the second conductive film and the first metal layer through this mask. (2) The method for forming a metal pattern according to claim 1, wherein aluminum is used as the first metal. (3) The method for forming a metal pattern according to claim 1, wherein an aluminum alloy is used as the first metal. (4) The method for forming a metal pattern according to any one of claims 1 to 3, characterized in that a high melting point metal film is used as the second conductive film. (5) Claims 1 to 3, characterized in that a silicide film of a high melting point metal is used as the second conductive film.
A method for forming a metal pattern according to any one of paragraphs. (6) The method for forming a metal pattern according to claim 4 or 5, characterized in that molybdenum is used as the high melting point metal. (7) The method for forming a metal pattern according to claim 4 or 5, characterized in that tungsten is used as the high melting point metal. (8) The method for forming a metal pattern according to claim 4 or 5, characterized in that titanium is used as the high melting point metal. (9) The method for forming a metal pattern according to claim 4 or 5, characterized in that tantalum is used as the high melting point metal. (10) The method for forming a metal pattern according to claim 4 or 5, characterized in that cobalt is used as the high melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2874283A JPS59154027A (en) | 1983-02-21 | 1983-02-21 | Formation of metal pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2874283A JPS59154027A (en) | 1983-02-21 | 1983-02-21 | Formation of metal pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59154027A true JPS59154027A (en) | 1984-09-03 |
Family
ID=12256870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2874283A Pending JPS59154027A (en) | 1983-02-21 | 1983-02-21 | Formation of metal pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59154027A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153689A (en) * | 1988-09-14 | 1992-10-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158072A (en) * | 1974-11-18 | 1976-05-21 | Matsushita Electric Ind Co Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5555547A (en) * | 1978-10-17 | 1980-04-23 | Mitsubishi Electric Corp | Method of forming electrode and wiring layer of semiconductor device |
| JPS56133465A (en) * | 1980-03-25 | 1981-10-19 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Working method for aluminum film |
-
1983
- 1983-02-21 JP JP2874283A patent/JPS59154027A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5158072A (en) * | 1974-11-18 | 1976-05-21 | Matsushita Electric Ind Co Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS5555547A (en) * | 1978-10-17 | 1980-04-23 | Mitsubishi Electric Corp | Method of forming electrode and wiring layer of semiconductor device |
| JPS56133465A (en) * | 1980-03-25 | 1981-10-19 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Working method for aluminum film |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153689A (en) * | 1988-09-14 | 1992-10-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines |
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