JPH0951000A - Formation of wiring layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method by which a wiring layer which can suppress the occurrence of disconnection and short circuits can be formed through a simple process. SOLUTION: After a composition-modulated layer is formed on a substrate, a resist layer R13 is formed in a prescribed pattern. When the part of the composition-modulated layer which is not covered with the layer R13 is etched with an etchant, a wiring layer 15 is obtained. When a layer containing copper and chromium in such a state that the coppercontent varies from 100% at the upper surface to 0% at the lower surface and the chromium content varies from 0% at the upper surface to 100% at the lower surface (namely, copper becomes dominant as going toward the upper surface and chromium becomes dominant as going toward the lower surface) is used as the composition- modulated layer and such an etchant that the etch rate to copper is higher than that to chromium is used, the upper surface of the wiring layer 51 can be curved and steps can be smoothed. Therefore, the occurrence of disconnection and short circuits in another wiring layer overpassing the wiring layer 51 can be prevented.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for forming a wiring layer,
In particular, it relates to a method of forming a wiring layer having a three-dimensional cross structure on a substrate.

[0002]

2. Description of the Related Art In a semiconductor device in which a large number of active devices such as MOSFETs and TFTs are arranged in a matrix, it is necessary to form wiring layers such as gate electrodes and source electrodes vertically and horizontally. Such a wiring layer is usually formed in a laminated structure. For example, a large number of gate electrodes are arranged on the substrate so as to extend in the first direction, an insulating layer is formed on the entire surface of the substrate including the gate electrodes, and the insulating layer is extended on the insulating layer in the second direction. When a large number of source electrodes are formed, the gate electrode and the source electrode have a laminated structure with an insulating layer sandwiched therebetween, and the two electrodes intersect each other by a three-dimensional cross structure.

The formation of such a wiring layer is generally performed by an etching process. That is, first, a predetermined conductor layer is formed on the entire surface of the substrate, a resist layer having a predetermined pattern is formed thereon, and an etching process is performed using this resist layer as a mask to expose the exposed portion of the conductor layer. Is removed, the remaining conductor layer becomes a target wiring layer. By repeating such a process while interposing an insulating layer as necessary, a large number of wiring layers having a laminated structure can be formed.

[0004]

However, when the wiring layer is formed by the above-mentioned method, there is a possibility that a partial disconnection or a short circuit may occur at the three-dimensional intersection.
When two wiring layers are three-dimensionally crossed with an insulating layer sandwiched between them, it is unavoidable to adopt a structure in which the wiring layer on the upper layer straddles the stepped portion caused by the wiring layer on the lower layer side. Therefore, there is a possibility that the upper wiring layer may be broken or that the upper and lower wiring layers may be short-circuited in the portion crossing the step. In order to prevent this, a method of forming a smoothing layer using coating glass or a flat material to eliminate the step as much as possible is also used, but it is unnecessary to form such a smoothing layer. This is not preferable because it requires a process.

Therefore, an object of the present invention is to provide a method for forming a wiring layer which can suppress the occurrence of disconnection and short circuit and which has a simple process.

[0006]

[Means for Solving the Problems]

(1) The first aspect of the present invention is that the same etchant as the first material that can be etched with a predetermined etchant can be used, and
A second material having an etching rate slower than that of the first material is prepared, and at least one of the first material and the second material is a conductive material. A composition modulation layer in which the composition ratio of the first material and the second material changes in the thickness direction so that the first material becomes dominant and the second material becomes more dominant toward the lower surface, A resist layer formed on a substrate or a predetermined layer and having a pattern corresponding to the wiring layer to be formed is formed on the upper surface of the composition modulation layer, and an etchant is exposed from the exposed portion of the composition modulation layer not covered by the resist layer. It is made to act and etch, and the wiring layer is formed by the remaining composition modulation layer.

(2) The second aspect of the present invention is the above-mentioned first aspect.
In the method for forming a wiring layer according to the above aspect, a first wiring layer is formed by the remaining composition modulation layer, an insulating layer is formed on a substrate including the first wiring layer, and a first wiring layer is formed on the insulating layer. The second wiring layer that intersects with the wiring layer of 3 is further formed.

(3) A third aspect of the present invention relates to the above-mentioned first aspect.
Alternatively, in the method for forming a wiring layer according to the second aspect, copper is used as the first material and chromium is used as the second material.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described based on illustrated embodiments. First, for convenience of description, an example of a conventional general wiring layer forming method will be described. FIG.
[FIG. 3] is a perspective view of an element in which a plurality of wiring layers having a three-dimensional intersection structure are formed, and a cross section thereof is shown in the front part. In this illustration, an insulating substrate (eg, glass substrate)
Two wiring layers 21 and 22 (for example, a metal layer such as aluminum) are formed on the wiring layer 10, an insulating layer 30 (for example, a SiN layer) is formed on the entire surface thereof, and another wiring layer is formed on the insulating layer 30. A wiring layer 41 (for example, a metal layer such as aluminum) is formed.

Here, the wiring layers 21 and 22 and the wiring layer 41 have a three-dimensional intersection structure with the insulating layer 30 interposed therebetween. The wiring layers 21 and 22 on the lower layer side extend in the first direction (depth direction in the drawing) on the substrate 10, and the wiring layer 41 on the upper layer side.
Extend in the second direction (left-right direction in the drawing) on the substrate 10. In a semiconductor element in which a large number of MOSFETs and TFTs are arranged, a large number of such wiring layers are arranged vertically and horizontally. For example, the lower wiring layer 2 extending in the first direction
A mode in which 1 and 22 are used as the gate electrode layer for each transistor and the upper wiring layer 41 extending in the second direction is used as the source electrode layer for each transistor is generally used. In such a semiconductor element, not only the wiring layer but also layers such as a semiconductor channel layer and an impurity diffusion layer are formed at the same time, but description of each of these layers is omitted here.

Here, a general method for forming a wiring layer having a structure as shown in FIG. 1 will be briefly described below with reference to side sectional views of FIGS. First, as shown in FIG. 2, the conductor layer 20 is formed on the substrate 10, and the resist layer R10 is formed thereon. Subsequently, the resist layer R10 is partially exposed to light using a predetermined photomask and developed to form partial resist layers R11 and R12 as shown in FIG. Then, when the conductor layer 20 is etched using the resist layers R11 and R12 as masks, as shown in FIG. 4, only the portion covered with the resist layers R11 and R12 is the lower wiring layer 21. , 22 will be formed.

Next, after removing the resist layers R11 and R12 by peeling, an insulating layer 30 is deposited and formed on the entire surface of the substrate 10 as shown in FIG. Subsequently, a conductor layer 40 is formed on the entire surface of the insulating layer 30, as shown in FIG. Further, if a resist layer having a predetermined pattern is formed thereon and etching is performed, an upper wiring layer 41 is formed as shown in FIG.

However, the structure shown in FIG.
Since the upper wiring layer 41 has a structure that straddles the stepped portions of the lower wiring layers 21 and 22, if a partial non-uniformity occurs in the various layer forming processes in the above-described steps, the wiring layer may be disconnected or broken. A short circuit may occur. For example, FIG.
In the example shown in, there is a break in the portion indicated by arrow A,
A short circuit occurs at the portion indicated by arrow B. The disconnection of the portion indicated by the arrow A is caused by insufficient deposition on the step structure portion of the insulating layer 30 indicated by the arrow A in the step of depositing and forming the conductor layer 40. The short circuit at the portion indicated by the arrow B is caused by insufficient deposition on the step structure portion of the wiring layer 22 indicated by the arrow B in the step of depositing and forming the insulating layer 30.

As described above, the disconnection or short circuit of the upper wiring layer 41 is caused by the steep step structure of the lower wiring layers 21 and 22. Therefore, in order to eliminate such a steep step structure, a method of forming an extra smoothing layer to improve the yield has been conventionally performed.
However, such a method adds an extra step and is not preferable in itself.

The basic idea of the present invention is to eliminate a steep step structure without adding extra steps by forming a wiring layer with a composition modulation layer. Hereinafter, an example of the embodiment will be described with reference to the side sectional views shown in FIGS.

First, as shown in FIG.
A composition modulation layer 50 is prepared (for example, a glass substrate). Instead of the substrate 10, the composition modulation layer 50 may be formed on an insulating layer formed on the substrate (for example, a SiO ₂ layer formed on a silicon substrate). The composition modulation layer 50 is a layer to be a wiring layer to be finally formed according to the present invention, and has the following features. First of all, it is a layer composed of two kinds of materials, a first material and a second material. The first material is dominant toward the upper surface, and the second material is dominant toward the lower surface. Therefore, the composition ratio of the first material and the second material must be a layer that changes in the thickness direction. The “composition modulation layer” means a layer whose composition ratio changes in the thickness direction as described above. Secondly, at least one of the first material and the second material needs to be a material having conductivity. This is natural considering that the composition modulation layer 50 is finally used as a wiring layer.
However, in practice, it is better to form both the first material and the second material with a conductive material (for example, metal).
This is preferable because a wiring layer having good electrical conductivity can be formed. Furthermore, thirdly, the first material and the second material are materials that can be etched by the same etchant, and the second material by this same etchant.
The condition that the etching rate for the first material is slower than the etching rate for the first material must be satisfied.

Here, a composition modulation layer of copper and chromium is used as a layer having such three characteristics. That is, copper is used as the first material, and chromium is used as the second material. In the composition modulation layer 50, the copper becomes more dominant toward the upper surface and the chromium is more dominant toward the lower surface. Layered. More specifically, the composition ratio of copper is 100% on the upper surface and 0% on the lower surface, and conversely, the composition ratio of chromium is 0% on the upper surface and 100% on the lower surface. Has become. Since both copper and chromium are conductive metals, the entire composition modulation layer 50 also forms a conductive layer. Moreover, copper and chromium are the same etchant (in this example, an etching liquid containing perchloric acid and ceric ammonium nitrate as main components (manufactured by The Inktech Co., Ltd .: trade name “MR-ES”)). ), The etching rate of chromium with this etchant is lower than that of copper.

On such a composition modulation layer 50, as shown in FIG.
A resist layer R13 is formed as shown in FIG. To form such a resist layer R13, after forming a resist layer on the entire surface of the composition modulation layer 50, exposure and development using a predetermined photomask may be performed. The resist layer R13 has a pattern corresponding to the wiring layer to be formed. Here, a resist layer R13 having an elongated rectangular pattern extending in a direction perpendicular to the paper surface of FIG.
The following description will be continued assuming that the above is formed.

Next, from the exposed portion of the composition modulation layer 50 not covered with the resist layer R13, the above-mentioned etching solution (an etching solution containing perchloric acid and ceric ammonium nitrate as main components (The Inktech) is used. Co., Ltd .: Product name "MR-ES")) is applied to perform etching. Then, the resist layer R13 of the composition modulation layer 50 is
The part that is not covered with will be etched away. However, as described above, since the etching rate of this etching solution is higher in copper than in chromium, if the predetermined etching time is secured, the structure shown in the side sectional view of FIG. 11 is obtained. . That is, since the composition ratio of copper becomes higher as it goes upward in the composition modulation layer 50, the etching rate becomes higher as it goes upward.
Erosion progresses laterally as it goes upward. As a result, as shown in FIG. 11, a structure is obtained which is more etched as it goes upward.

Finally, the resist layer R13 is peeled and removed,
If the wiring layer 51 is formed of the remaining composition modulation layer,
The wiring layer 51 is a wiring layer having a curved structure from the upper surface to the side surface. In the example shown in FIG. 11, the wiring layer 51 having a semicircular cross section is formed, and the wiring layer 51 having such a cross section is formed in a state of extending in the direction perpendicular to the paper surface. A so-called "buckwheat type" wiring layer can be obtained. However, in order to form the semicircular wiring layer 51 as shown in FIG. 11, it is necessary to appropriately set the change in the composition ratio of the composition modulation layer 50 in the thickness direction. A simple linear variation of the composition ratio results in a triangular cross section rather than a semi-circular cross section. In order to obtain a curved structure as shown in FIG. 11, it is necessary to set a gentle composition ratio change.

To form the composition-modulating layer 50, in an environment in which chromium and copper can be simultaneously sputtered or vapor-deposited, the chromium supply rate is 100% and the copper supply rate is 100% at the initial stage of formation of the layer. 0%, gradually reduce the chromium supply rate and increase the copper supply rate, so that when the layer formation is completed, the chromium supply rate is 0% and the copper supply rate is 100%. You can do this. By setting the change curve of the supply ratio in an arc shape, finally, as shown in FIG. 11, the wiring layer 51 having a semicircular cross section can be formed.

The wiring layer 51 thus formed is a lower wiring layer. To form an upper wiring layer that intersects with this, as shown in FIG. 12, an insulating layer 35 (for example, a SiN layer) is deposited and formed on the entire surface of the substrate 10 including the wiring layer 51, and the wiring layer 51 is formed thereon. Then, the upper wiring layer 45 may be formed. As shown in FIG. 12, a step is generated due to the presence of the wiring layer 51, and the insulating layer 35 and the upper wiring layer 45 are
Although it is formed so as to straddle this step, the step does not have a steep structure but a gently curved structure.
Therefore, unlike the structure of the wiring layer formed by the conventional method, disconnection or short circuit at the step portion is less likely to occur.

FIG. 13 is a perspective view showing a state in which a structure equivalent to the structure shown in FIG. 1 is formed by the method according to the present invention. Lower wiring layers 52, 53 formed on the substrate 10
Are wiring layers formed from the above-described composition modulation layer 50 of copper and chromium. Wiring layer 51 shown in FIG.
Then, although the cross section was a perfect semi-circle, it is not always necessary to make it a semi-circle. Lower wiring layer 5 shown in FIG.
In Nos. 2 and 53, the shoulder portion has a slightly curved structure, and the upper wiring layer 46 formed with the insulating layer 36 interposed therebetween.
It is possible to straddle a gentle step due to the lower wiring layers 52 and 53 with a gentle undulation. In this way, it is possible to sufficiently prevent disconnection or short circuit of the upper wiring layer 46 by only bending the shoulder portions of the lower wiring layers 52 and 53. Therefore, the conventional step of forming an additional smoothing layer is not necessary.

When the combination of copper and chromium is adopted as the two types of materials constituting the composition modulation layer 50, additional merits are obtained in terms of conductivity and adhesion.
That is, the wiring layer 51 shown in FIG. 12 is composed of copper and chromium, and the upper part is dominated by copper and the lower part is dominated by chrome. Copper is superior to chrome in terms of conductivity, and the wiring layer 5 is better than the wiring layer of chromium alone.
No. 1 has good conductivity. In addition, chrome is superior to copper in terms of adhesion, and the wiring layer 5 is better than the wiring layer of copper alone.
No. 1 has good adhesion. That is, the interface between the substrate 10 and the wiring layer 51 has a composition of almost 100% chromium, and good adhesion can be obtained between the substrate 10 and the wiring layer 51.

Although the present invention has been described above based on the illustrated embodiments, the present invention is not limited to such embodiments and can be widely used in various fields other than this.

[0026]

As described above, according to the method of forming a wiring layer according to the present invention, a composition modulation layer is used for the wiring layer, and processing is performed by utilizing the difference in etching rate of the material contained in the composition modulation layer. Since the wiring layer having the gradual step structure is formed by doing so, it is possible to form the wiring layer in which disconnection or short circuit hardly occurs in a simple process.

[Brief description of drawings]

FIG. 1 is a perspective view of an element in which a plurality of wiring layers having a three-dimensional intersection structure are formed, and a cross section thereof is shown in the front part.

FIG. 2 is a side sectional view showing a first step of a conventional method for forming the wiring layer shown in FIG.

FIG. 3 is a side sectional view showing a second step of the conventional method for forming the wiring layer shown in FIG.

4 is a side sectional view showing a third step of the conventional method for forming the wiring layer shown in FIG.

5 is a side sectional view showing a fourth step of the conventional method for forming the wiring layer shown in FIG.

6 is a side sectional view showing a fifth step of the conventional method for forming the wiring layer shown in FIG. 1. FIG.

7 is a side sectional view showing a sixth step of the conventional method for forming the wiring layer shown in FIG. 1. FIG.

8 is a side sectional view showing a disconnection and a short circuit that occur in the wiring layer shown in FIG.

FIG. 9 is a side sectional view showing a first step of a method for forming a wiring layer according to the present invention.

FIG. 10 is a side sectional view showing a second step of the method for forming a wiring layer according to the present invention.

FIG. 11 is a side sectional view showing a third step of the method for forming a wiring layer according to the present invention.

FIG. 12 is a side sectional view showing a fourth step of the method for forming a wiring layer according to the present invention.

FIG. 13 is a perspective view of an element having a plurality of wiring layers formed by the method according to the present invention, the cross section of which is shown in the front portion.

[Explanation of symbols]

 10 ... Substrate 20 ... Conductor layers 21, 22 ... Lower layer side wiring layers 30, 35, 36 ... Insulating layer 40 ... Conductor layers 41, 45, 46 ... Upper layer side wiring layer 50 ... Composition modulation layers 51, 52, 53 ... Lower wiring layer R10 to R13 ... Resist layer

Claims (3)

[Claims] 1. A first material that can be etched with a predetermined etchant, and a second material that can be etched with the etchant and that has an etching rate slower than that of the first material. In addition, at least one of the first material and the second material is a conductive material, and the first material becomes more dominant toward the upper surface and the lower surface toward the lower surface. A wiring layer to be formed by forming, on a substrate or a predetermined layer, a composition modulation layer in which the composition ratio of the first material and the second material changes in the thickness direction so that the second material becomes dominant. Forming a resist layer having a pattern according to the above, on the upper surface of the composition modulation layer, and performing etching by acting the etchant from the exposed portion of the composition modulation layer not covered by the resist layer,
A method of forming a wiring layer, which comprises forming the wiring layer with the remaining composition modulation layer. 2. The method for forming a wiring layer according to claim 1, wherein the remaining composition modulation layer forms a first wiring layer, and an insulating layer is formed on a substrate including the first wiring layer. A method of forming a wiring layer, further comprising: forming a second wiring layer that intersects with the first wiring layer on the insulating layer. 3. The method for forming a wiring layer according to claim 1, wherein copper is used as the first material and chromium is used as the second material, respectively.