JPS59154017A - Furnace paddle for semiconductor wafer - Google Patents
Furnace paddle for semiconductor waferInfo
- Publication number
- JPS59154017A JPS59154017A JP2983583A JP2983583A JPS59154017A JP S59154017 A JPS59154017 A JP S59154017A JP 2983583 A JP2983583 A JP 2983583A JP 2983583 A JP2983583 A JP 2983583A JP S59154017 A JPS59154017 A JP S59154017A
- Authority
- JP
- Japan
- Prior art keywords
- paddle
- semiconductor wafer
- semiconductor wafers
- grooves
- slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4587—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially vertically
Landscapes
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造工程において使用される半導
体ウェハの加熱炉用パドルに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a paddle for a heating furnace for semiconductor wafers used in the manufacturing process of semiconductor devices.
従来、半導体ウェハを熱処理する場合、炉芯管等の加熱
炉への半導体ウエノ1の出し入れは第1図に示すような
パドル及びボートにより行なわれていた。Conventionally, when heat-treating a semiconductor wafer, the semiconductor wafer 1 was taken in and out of a heating furnace such as a furnace core tube using a paddle and a boat as shown in FIG.
第1図(4)、(B)に示すようにパドル(1)は把手
(2)。As shown in Figures 1 (4) and (B), the paddle (1) is a handle (2).
皿部(3)、コロ(4)からなシ、又、第1図(C)
、 (D)に示すようにボート(5)には複数の溝(6
)が設けられている。Plate part (3), roller (4), and Figure 1 (C)
, As shown in (D), the boat (5) has a plurality of grooves (6
) is provided.
そして、従来は第1図■)、(ト)に示すように、溝・
(6)に半導体ウェハ(7)を載せたボート(5)を
パドル(1)の皿部(3)内にセットし、このようにセ
ットした状態で図示しない炉芯管等の加熱炉に出し入れ
していた。Conventionally, grooves and
The boat (5) carrying the semiconductor wafer (7) is set in the tray (3) of the paddle (1) in (6), and while it is set in this way, it is taken out and put into a heating furnace such as a furnace core tube (not shown). Was.
しかしながら、従来このようなボートを用いたパドルで
は、炉心管に入れたとき又、出したときに、第1図(F
′)に示す半導体ウェハ(7)の頂点(I)と底部(I
I)では温度差を生じるという欠点があった。However, in the conventional paddle using such a boat, when it is inserted into the reactor core tube and when it is taken out, the paddle as shown in Fig. 1 (F
The top (I) and bottom (I) of the semiconductor wafer (7) shown in
I) had the disadvantage of generating a temperature difference.
即ち、頂点(1)では、炉に入れた時は輻射によってた
だちに高温になシ、炉から出した時は放熱により低温に
もどシ易い。一方、底部(II)では入れた時熱容量の
大きなパドル(1)、ボート(5)によって高温になり
に<<、又、出した時元にもどシにくい。That is, at the vertex (1), when it is put into the furnace, it is immediately heated to a high temperature due to radiation, and when it is taken out from the furnace, it is easily returned to a low temperature due to heat radiation. On the other hand, the bottom part (II) becomes hot due to the large heat capacity paddle (1) and boat (5) when it is put in, and is difficult to return to its original state when taken out.
特に問題となるのは炉に入れた時であって、拡散におけ
るデポジションでの不純物の導入、ドライブにおける拡
散深さ、酸化における膜厚、C1V、D、における膜厚
等が半導体ウェハの温度によって左右されるために、半
導体ウェハ上に温度差があると、場所によってシート抵
抗値、拡散深さ及び膜厚が大幅に変化する。又、温度が
大幅に変化すると熱ストレスによる結晶欠陥が発生する
ことがある。Particular problems arise when the semiconductor wafer is placed in a furnace, and the introduction of impurities during deposition during diffusion, the diffusion depth during drive, the film thickness during oxidation, and the film thickness at C1V and D depend on the temperature of the semiconductor wafer. Because of this, temperature differences across a semiconductor wafer will cause sheet resistance, diffusion depth, and film thickness to vary significantly from location to location. Further, if the temperature changes significantly, crystal defects may occur due to thermal stress.
本発明はこのような従来の欠点に鑑みなされたもので、
半導体ウェハの加熱炉への出し入れ時に半導体ウェハの
場所による温度差が生じないようにするため、加熱炉用
パドルに直接半導体ウェハを載せるだめの溝を設けると
ともに、溝を分離するようにスリットを設けることによ
り、熱容量の低減と熱輻射による半導体ウェハ内の温度
差の低減とを計るようにした亀のである。The present invention was made in view of these conventional drawbacks.
In order to prevent temperature differences depending on the location of the semiconductor wafer when loading and unloading the semiconductor wafer into the heating furnace, a groove is provided for placing the semiconductor wafer directly on the heating furnace paddle, and a slit is provided to separate the groove. By doing so, it is possible to reduce the heat capacity and the temperature difference within the semiconductor wafer due to thermal radiation.
次に本発明の一実施例について第2図を用いて説明する
。第2図(A) 、 (B)は本発明のパドルを示して
おシ、円弧状に形成されたパドル0.11自体の底部に
半導体ウェハ(力を載せる溝(6)を長さ方向に直角に
底面が円弧状になるように設け、又、この溝(6)を2
つに分離するように長さ方向に沿つ″て底部にスリット
(17Jを設けている。第2図(C)はパドルIの斜視
図、第2図の)は第2図C)のパドルQl)上に半導体
ウェハ(力を載せた状態を示すd−d断面図である。Next, one embodiment of the present invention will be described using FIG. 2. FIGS. 2(A) and 2(B) show the paddle of the present invention, in which a semiconductor wafer (a groove (6) for applying force) is formed in the bottom of the paddle 0.11 itself formed in an arc shape in the longitudinal direction. The groove (6) is provided at right angles so that the bottom surface has an arc shape.
A slit (17J) is provided at the bottom along the length direction so as to separate the paddle. It is a dd cross-sectional view showing a state in which a force is placed on a semiconductor wafer (Ql).
以上のような構成のパドル(lllでは、従来の第1図
に示したようなボート(5)がないため、その分の熱容
量が減少し、バドル0υ自体も従来のパドル+11に比
ベスリット(1zを設けたため若干熱容量が少なくなっ
ている。又、溝(6)の底面が円弧状であるため、従来
に比ベパドルαDから半導体ウェハ(7)への熱伝導が
良く、かつ、底部にスリット(1zが設けられているた
め、炉からの輻射で半導体ウェハ(力の底部(第2図の
)の(■))での昇温は頂点(I)とほぼ同程度になっ
て、半導体ウェハ(力に温度差を生じない。又、降温時
において熱容量が大きいことが半導体ウェハ(7)に温
度差を起す天き力原因であったが、本発明のパドルαυ
によると降温時においても半導体ウェハ(7)の場所に
よる温度差は小さくなる。Since the paddle (lll) with the above configuration does not have the conventional boat (5) shown in Fig. 1, the heat capacity decreases accordingly, and the paddle itself also has a best slit (1z) compared to the conventional paddle +11. Since the bottom of the groove (6) is arc-shaped, the heat conduction from the paddle αD to the semiconductor wafer (7) is better than in the past. 1z is provided, the temperature rise at the semiconductor wafer ((■) at the bottom of the force (in Figure 2)) due to radiation from the furnace is approximately the same as at the top (I), and the semiconductor wafer ( The paddle αυ of the present invention does not cause a temperature difference in force.Also, the large heat capacity when the temperature drops is the cause of the natural force that causes a temperature difference in the semiconductor wafer (7), but the paddle αυ of the present invention
According to the above, even when the temperature drops, the temperature difference depending on the location of the semiconductor wafer (7) becomes small.
又、熱伝導1強度、熱容量を考慮してパドル(11)の
材質は炭化珪素を用いている。Further, in consideration of heat conduction strength and heat capacity, silicon carbide is used as the material for the paddle (11).
、第3図は本発明の他の実施例を示すパドル圓であって
、スリットα4を2本にして強度及び熱容量を一層改善
したものである。, FIG. 3 shows a paddle circle according to another embodiment of the present invention, in which two slits α4 are used to further improve strength and heat capacity.
又、第4図に示すようにコロ(4)を両端に設けて操作
性を改善することも可能である。It is also possible to improve the operability by providing rollers (4) at both ends as shown in FIG.
以上説明したように本発明によれば、パドルに直接半導
体ウェハを載せる溝を設け、かつ、底部にスリットを設
けたので、熱容量を小さく、熱伝導と熱輻射を大きくで
き、炉内への出し入れに際しての半導体ウェハの場所に
よる温度差が小さくなって、品質の安定した半導体装置
が製造できる効果がある。As explained above, according to the present invention, the paddle is provided with a groove for placing the semiconductor wafer directly on it, and a slit is provided at the bottom, so that the heat capacity can be reduced and heat conduction and heat radiation can be increased, allowing for easy loading and unloading into and out of the furnace. This has the effect of reducing temperature differences depending on the location of the semiconductor wafer during processing, and making it possible to manufacture semiconductor devices with stable quality.
第1図(3)は従来のパドルの平面図、第1図(B)は
パドルの側面図、第1図(C)はボードの平面図、第1
図(9)はボードの側面図、第1図■)はパドルに半導
体ウェハを載せたボードをセットした状態の斜視図、第
1図(ト)は第1図(ト))のf−f断面図、第2図は
本発明の一実施例を示しておシ、第2図(A)はパドル
の平面図、第2図(B)はパドルの側面図、第2図(0
はパドルの斜視図、第2図の)は第2図(C)において
半導体ウェハを載せた状態を示すd−d断面図、第3図
及び第4図は本発明の他の実施例を示すパドルの平面図
である。
+21・・・・把手、(4)・・・・コロ、(6)・・
・・溝、(力・・・・半導体ウェハ、oI)・・・・パ
ドル、az・ψ・・スリット。
代理人 葛 野 信 −Fig. 1(3) is a plan view of a conventional paddle, Fig. 1(B) is a side view of the paddle, Fig. 1(C) is a plan view of the board,
Figure (9) is a side view of the board, Figure 1 (■) is a perspective view of the board with a semiconductor wafer mounted on the paddle, and Figure 1 (G) is f-f of Figure 1 (G)). 2(A) is a plan view of the paddle, FIG. 2(B) is a side view of the paddle, and FIG.
is a perspective view of the paddle, FIG. 2) is a cross-sectional view taken along line dd showing the state in which a semiconductor wafer is placed in FIG. 2(C), and FIGS. 3 and 4 show other embodiments of the present invention. FIG. 3 is a plan view of the paddle. +21...handle, (4)...roller, (6)...
...Groove, (force...semiconductor wafer, oI)...paddle, az/ψ...slit. Agent Shin Kuzuno −
Claims (2)
ェハを載せて出し入れするパドルにおいて、長さ方向に
直角に底面が円弧状になるように半導体ウェハを載せる
溝を設け、この溝を分離するように長さ方向にスリット
を設け、このパドルを保持する少なくとも1組のコロを
設けたことを特徴とする半導体ウェハの加熱炉用パドル
。(1) In order to heat-treat semiconductor wafers in a heating furnace, a paddle for loading and unloading a semiconductor wafer is provided with a groove on which the semiconductor wafer is placed so that the bottom surface is arcuate at right angles to the length direction, and this groove is separated. A paddle for a heating furnace for semiconductor wafers, characterized in that a slit is provided in the length direction of the paddle, and at least one set of rollers for holding the paddle is provided.
徴とする特許請求の範囲第1項記載の半導体ウェハの加
熱炉用パドル。(2) The paddle for a semiconductor wafer heating furnace according to claim 1, wherein the paddle is made of silicon carbide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2983583A JPS59154017A (en) | 1983-02-22 | 1983-02-22 | Furnace paddle for semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2983583A JPS59154017A (en) | 1983-02-22 | 1983-02-22 | Furnace paddle for semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59154017A true JPS59154017A (en) | 1984-09-03 |
Family
ID=12287069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2983583A Pending JPS59154017A (en) | 1983-02-22 | 1983-02-22 | Furnace paddle for semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59154017A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01139426U (en) * | 1988-03-18 | 1989-09-22 | ||
JPH08169500A (en) * | 1995-09-20 | 1996-07-02 | Tokico Ltd | Oil feed system |
JP2012222156A (en) * | 2011-04-08 | 2012-11-12 | Hitachi Kokusai Electric Inc | Substrate processing apparatus and transport apparatus |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53129964A (en) * | 1977-04-20 | 1978-11-13 | Hitachi Ltd | Method and device for inserting and taking out of heat treatment jig |
JPS5599738A (en) * | 1979-01-26 | 1980-07-30 | Hitachi Ltd | Automatic conveying equipment for wafer |
-
1983
- 1983-02-22 JP JP2983583A patent/JPS59154017A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53129964A (en) * | 1977-04-20 | 1978-11-13 | Hitachi Ltd | Method and device for inserting and taking out of heat treatment jig |
JPS5599738A (en) * | 1979-01-26 | 1980-07-30 | Hitachi Ltd | Automatic conveying equipment for wafer |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01139426U (en) * | 1988-03-18 | 1989-09-22 | ||
JPH08169500A (en) * | 1995-09-20 | 1996-07-02 | Tokico Ltd | Oil feed system |
JP2012222156A (en) * | 2011-04-08 | 2012-11-12 | Hitachi Kokusai Electric Inc | Substrate processing apparatus and transport apparatus |
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