JPS59152646A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59152646A JPS59152646A JP2720483A JP2720483A JPS59152646A JP S59152646 A JPS59152646 A JP S59152646A JP 2720483 A JP2720483 A JP 2720483A JP 2720483 A JP2720483 A JP 2720483A JP S59152646 A JPS59152646 A JP S59152646A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- holes
- glass film
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims abstract description 27
- 239000011521 glass Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims description 20
- 239000005360 phosphosilicate glass Substances 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 claims 1
- -1 tungsten halogen Chemical class 0.000 abstract description 4
- 229910052736 halogen Inorganic materials 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 20
- 238000007796 conventional method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910019213 POCl3 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特にコンタクト
ホール部を改良した半導体装置の製造方法に係わる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with improved contact hole portions.
従来、半導体装置は例えば、第１図（ａ） ＃ （ｂ）
に示す方法によシ製造されている。Conventionally, semiconductor devices, for example, are shown in FIGS.
It is manufactured by the method shown in .
まず、例えばｐ型のＳｉ基板１表面に常法によシｎ十型
の拡散層２を形成した後全面に層間 ・絶縁膜３を形
成する。つづいて、例えば反応性イオンエツチング（Ｒ
ＩＥ ）法によシ前記拡散層２の一部に対応する眉間絶
縁膜３部分を選択的にエツチング除去し、コンタクトホ
ール４を形成する（第１図（、）図示）。なお、こうし
た状態ではコンタクトホール４が急峻なため、該コンタ
クトホールに配線を形成したとき断切れを生じやすい。First, an N-type diffusion layer 2 is formed on the surface of a p-type Si substrate 1 by a conventional method, and then an interlayer insulating film 3 is formed on the entire surface. Next, for example, reactive ion etching (R
A contact hole 4 is formed by selectively etching away a portion of the glabella insulating film 3 corresponding to a portion of the diffusion layer 2 using the IE) method (as shown in FIG. 1(a)). Note that in such a state, since the contact hole 4 is steep, disconnection is likely to occur when wiring is formed in the contact hole.
次いで、外部にヒータを備えた拡散炉を用いてＰＯＣｔ
ｓ等の雰囲気で約１０００℃、２０分間熱処理を施して
コンタクトホール４の層間絶縁膜３部分にチーｉ４一部
５を形成して半導体装置を製造する（第１図（ｂ）図示
）。Next, POCt was performed using a diffusion furnace equipped with an external heater.
A heat treatment is performed at about 1000° C. for 20 minutes in an atmosphere such as S, to form a portion 5 of the interlayer insulating film 3 in the contact hole 4, thereby manufacturing a semiconductor device (as shown in FIG. 1(b)).
しかしながら、前述した製造方法によれば以下に示す欠
点を有していた。However, the above-described manufacturing method had the following drawbacks.
（１） ＰＯＣｌｓ等の雰囲気で熱処理を行なうため
、ｐｏｃｔ３中のリンが露出する基板１にコンタクトホ
ール４を介して再拡散し、拡散層２のシート抵抗が変化
する。(1) Since the heat treatment is performed in an atmosphere such as POCls, phosphorus in poct3 is re-diffused into the exposed substrate 1 through the contact hole 4, and the sheet resistance of the diffusion layer 2 changes.
（２）熱処理時間が２０分間と長時間であるため、予め
形成された振散層２が第１図（ｂ）に示す如く基板１の
厚みの方向のみならず、横方向にも再拡散して拡散層２
′となる。また、前記拡散層をソース、ドレイン領域と
して用いるＭＯ８型トランジスタにおいて、前記拡散層
の再拡散はチャネル長の短縮化（ショートチャンネル効
果）を招き、しきい値電圧の変動を生じさせる。(2) Since the heat treatment time is as long as 20 minutes, the pre-formed diffusion layer 2 is re-diffused not only in the thickness direction of the substrate 1 but also in the lateral direction, as shown in FIG. 1(b). diffusion layer 2
'. Further, in an MO8 type transistor using the diffusion layer as a source and drain region, re-diffusion of the diffusion layer causes a shortening of the channel length (short channel effect), causing a fluctuation in the threshold voltage.
（３）上記（１）と同様な理由から、熱処理時Ｋｐｏｃ
ｚＢ中のリンが層間絶縁膜３の露出面に付着するため、
後工程の配線層の信頼性等を考慮して該層間絶縁膜３の
露出面をＮＨ４Ｆ’溶ｇ、咎でエツチングするいわゆる
後処理を必要とする。その結果、層間絶縁Ｍ、 ３の厚
みが形成時より薄くなって絶縁耐圧が低下したシ、コン
タクトホール４の径が広がって索子の微細化が困難にな
る。(3) For the same reason as (1) above, Kpoc during heat treatment
Since phosphorus in zB adheres to the exposed surface of the interlayer insulating film 3,
In consideration of the reliability of the wiring layer in the subsequent process, so-called post-processing is required in which the exposed surface of the interlayer insulating film 3 is etched with NH4F' solution. As a result, the thickness of the interlayer insulation M, 3 becomes thinner than when it was formed, and the dielectric strength voltage decreases, and the diameter of the contact hole 4 increases, making it difficult to miniaturize the cord.
（４） ＰＯＣｌ３中のリンがｎ型の導電性を有する
不純物であるため、ｃＭｏｓの様に基板表面にｐ型とｎ
型の２種の拡散層を有するデバイスの場合、前述した１
回の熱処理で複数のコンタクトホールの眉間絶縁膜部分
にテーノぞ一部を形成できない。(4) Since phosphorus in POCl3 is an impurity with n-type conductivity, p-type and n-type conductivity are formed on the substrate surface like cMoS.
For devices with two types of diffusion layers, the above-mentioned 1.
It is not possible to form a part of the groove in the glabellar insulating film part of the plurality of contact holes by heat treatment.
本発明は上記事情に鑑みてなされたもので、長時間の熱
処理に伴なうシート抵抗の変化、接合深さの変化あるい
＋ｉ ＰＯＣｔｓを用いることによる絶縁耐圧の変動並
びにコンタクト径の広がシ等の種々の問題点を解消した
半導体装置の製造方法を提供することを目的とするもの
である。The present invention has been made in view of the above-mentioned circumstances, and is intended to address changes in sheet resistance due to long-term heat treatment, changes in junction depth, changes in dielectric strength due to the use of +i POCts, and changes in contact diameter expansion. It is an object of the present invention to provide a method for manufacturing a semiconductor device that solves various problems such as the above.
本発明は、表面に拡散層を有する半導体基体上に不純物
を含むガラス膜を形成した後、前記拡散層の一部に対応
するガラス膜を選択的に開孔してコンタクトホールを形
成し、更にランプあるいはヒータによシ基体温度が９０
０〜１２００ Ｃとなるように直接加熱することによっ
て、シート抵抗の変化、接合深さの変化、絶紅耐圧の変
動並びにコンタクト径の広がシ等の種々の問題点の解消
を図ったことを骨子とする。The present invention includes forming a glass film containing impurities on a semiconductor substrate having a diffusion layer on the surface, and then selectively opening a hole in the glass film corresponding to a part of the diffusion layer to form a contact hole; The temperature of the substrate is 90℃ using a lamp or heater.
By heating directly to 0 to 1200 C, various problems such as changes in sheet resistance, changes in bonding depth, fluctuations in breakdown voltage, and widening of the contact diameter have been solved. Make it the gist.
本発明に係る不純物を含むガラス膜としては、リン中ケ
イ酸ガラス（ＰＳＧ ）膜、ホウ素−リンケイ酸ガラス
（ＢＰＳＧ ） Ｍ等が挙げられる。Examples of the glass film containing impurities according to the present invention include a phosphorous silicate glass (PSG) film, a boron-phosphosilicate glass (BPSG) M, and the like.
本発明において加熱処理の温度を上記の範囲に限定した
理由は、基体温度が９００℃未満の場合ハコンタクトホ
ールのガラス膜１部分を溶融して適切々テーパ一部を形
成しに〈＜、逆に１２００℃を越えると半導体基体表面
の拡散層の横方向の広がシを押えきれず、接合深さが深
くなるからである。また、加熱時間については加熱源の
種類によって変動するため一部に限定することはできな
いが、例えば加熱源としてタングステンハロゲンランプ
を用いた場合、５〜３０秒の範囲で熱処理することが好
ましい。ここで、加熱時間が５秒未満の場合、コンタク
トホールのガラス膜部分を溶融して適切なテーパ一部を
形成しに＜＜、逆に３０秒を越えると半導体基体表面の
拡散層の横方向の広がシを押えきれず接合深さが深くな
る。The reason why the temperature of the heat treatment is limited to the above range in the present invention is that when the substrate temperature is less than 900°C, one part of the glass film of the contact hole is melted and a part of the taper is appropriately formed. This is because if the temperature exceeds 1200° C., the lateral spread of the diffusion layer on the surface of the semiconductor substrate cannot be suppressed, and the junction depth becomes deep. Further, the heating time varies depending on the type of heat source and cannot be limited to a certain part, but for example, when a tungsten halogen lamp is used as the heat source, the heat treatment is preferably performed for 5 to 30 seconds. Here, if the heating time is less than 5 seconds, the glass film part of the contact hole is melted to form an appropriate taper. On the other hand, if the heating time exceeds 30 seconds, the lateral direction of the diffusion layer on the surface of the semiconductor substrate is Unable to suppress the spread of the bond, the bond depth becomes deeper.
以下、本発明をＭＯ８型トランジスタの製造に適用した
例について第２図（−）〜（ｄ）を参照して説明する。Hereinafter, an example in which the present invention is applied to manufacturing an MO8 type transistor will be described with reference to FIGS. 2(-) to 2(d).
まず、例えばｐ型のＳｔ基板（半導体基体）１１上に熱
酸化膜１２、多結晶シリコン層１３を形成した（第２図
（、）図示）。つづいて、前記多結晶シリコン層１３を
ノやターニングしてダート電極１４を形成した後、この
ダート電極１４をマスクとして前記熱酸化膜１２を選択
的に除去し、ダート絶縁膜１５を形扉した。次いで、前
記ダート電極１４をマスクとして基板１ノに例えば砒素
をイオン注入し、熱処理を施してれ＋型のソース、ドレ
イン領域１６．１７を形成した。更に１全面にＰＳＧ膜
１８を形成した後、ＲＩＥ法によシ前記ソース、ドレイ
ン領域１６゜１７の一部に対応するＰＳＧｉ１１８を選
択的に除去し、コンタクトホール１９，１９を形成した
（第２図（ｂ）図示）。このζ、例えばタングステンハ
ロゲンランプを用いてランｆ泥度１０００℃（基板温度
約９００℃）、大気中で３０秒間直接加熱を行ない、コ
ンタクトホール１９，１９のＰＳＧ膜１膜部８部分−・
ぐ一部２０を形成した（第２図（ｃ）図示）。ひきつづ
き、全面にＵ蒸着後、パターニングしてコンタクトホー
ル１９゜１９にソース、ドレイン領域１６．１７に接続
するＡｔ配線２１．２１を形成し、ＭＯ８型トランジス
タを製造した（第２図（ｄ）図示）。First, a thermal oxide film 12 and a polycrystalline silicon layer 13 were formed on, for example, a p-type St substrate (semiconductor base) 11 (as shown in FIG. 2(, )). Subsequently, after turning the polycrystalline silicon layer 13 to form a dirt electrode 14, the thermal oxide film 12 was selectively removed using the dirt electrode 14 as a mask, and a dirt insulating film 15 was formed. . Next, using the dirt electrode 14 as a mask, ions of, for example, arsenic were implanted into the substrate 1, and heat treatment was performed to form + type source and drain regions 16 and 17. Further, after forming a PSG film 18 on the entire surface, the PSG film 118 corresponding to a part of the source and drain regions 16 and 17 was selectively removed by RIE method, and contact holes 19, 19 were formed (second Figure (b) shown). This ζ is directly heated for 30 seconds in the air at a run f muddy degree of 1000°C (substrate temperature approximately 900°C) using, for example, a tungsten halogen lamp.
20 (as shown in FIG. 2(c)). Subsequently, after U was deposited on the entire surface, it was patterned to form At wirings 21 and 21 connected to the source and drain regions 16 and 17 in the contact holes 19 and 19, thereby manufacturing an MO8 type transistor (as shown in FIG. 2(d)). ).
しかして、本発明によればタングステンハロダンランプ
を用いて高温（基板温度１０００℃）で加熱す兎ことに
よシ、熱処理時間を短縮できる（３０秒間）。その結果
、コンタクトホール１９０ＰＳＧ脱１８部分のテーパ一
部２０の形成時にソース、ドレイン領域１６．１７の横
方向の広がシを防止できるため、ショートチャネル効果
を抑制でき、しきい値電圧の変動を阻止できる。また、
従来の如＜ ｐｏｃｔ５を用いることに起因するＰＳＧ
膜１８露出面の汚染を回避できるので、ＰＳＧ膜１Ｂの
膜厚が減少して絶縁耐圧が低下することを阻止できると
ともに、コンタクトホール１９の径の広がシを阻止して
素子の微細化を達成できる。According to the present invention, the heat treatment time can be shortened (to 30 seconds) by heating at a high temperature (substrate temperature of 1000° C.) using a tungsten-halodan lamp. As a result, it is possible to prevent the source and drain regions 16 and 17 from spreading in the lateral direction when forming the tapered portion 20 of the contact hole 190 PSG removal 18, thereby suppressing the short channel effect and suppressing fluctuations in the threshold voltage. It can be prevented. Also,
PSG caused by using conventional < poct5
Since contamination of the exposed surface of the film 18 can be avoided, it is possible to prevent the film thickness of the PSG film 1B from decreasing and the dielectric breakdown voltage from decreasing, and also to prevent the diameter of the contact hole 19 from increasing, thereby facilitating miniaturization of the element. It can be achieved.
更に、従来の如くチー・千一部形成時Ｋ ＰＯＣＬｓを
含んだ雰囲気で熱処理することなく大気中・で直接加熱
を行々うため、０ＭＯ８のように基板表面にｐ型とｎ型
の２種の拡散層を有するデバイスでも前述した熱処理を
１回行なうだけで、複数のコンタ２トホールのＰＳＧ膜
部分にチー／や一部を形成できる。Furthermore, since heating is performed directly in the air without heat treatment in an atmosphere containing K POCLs during the formation of Qi-Senichi as in the past, two types, p-type and n-type, are formed on the substrate surface as in 0MO8. Even in a device having a diffusion layer, by performing the above-described heat treatment only once, it is possible to form a portion of a chip in the PSG film portion of a plurality of contour holes.
事実ソース、ドレイン領域形成時の基板へのゾロンのイ
オン注入条件が加速電圧１２〜４゜ｋｅＶ、 ドーズ
量２ Ｘ １０ ｃｒｎ −、かつ熱処理条件（拡
散炉内温度９００℃、２０分）で製造した従来のＭＯ８
型トランジスタ、及びイオン注入条件が従来と同様で熱
処理条件（ヒータ温度１２５０℃、１０秒）で直接加熱
して製造した本発明によるＭＯ８型トランジスタについ
て夫々接合深さとソース、ドレイン領域のシート抵抗と
の関係を調べた゛ところ、第３図に示す特性図が荀られ
た。なお、同図中入は本発明によるＭＯ８型トランジス
タのソース、ドレイン領域Ω特性曲線を、Ｂは従来法に
よるそれの特性曲線を夫々示す。In fact, the conditions for ion implantation of zolon into the substrate when forming the source and drain regions were an acceleration voltage of 12 to 4 degrees keV, a dose of 2 x 10 crn -, and heat treatment conditions (diffusion furnace temperature 900 °C, 20 minutes). Conventional MO8
The relationship between the junction depth and the sheet resistance of the source and drain regions for the MO8 type transistor and the MO8 type transistor according to the present invention manufactured by direct heating under the heat treatment conditions (heater temperature 1250°C, 10 seconds) under the same ion implantation conditions as conventional ones, respectively. When we investigated the relationship, we found the characteristic diagram shown in Figure 3. The middle part of the figure shows the source and drain region Ω characteristic curves of the MO8 type transistor according to the present invention, and B shows the characteristic curve thereof according to the conventional method.
同図よシ明らかの如く、例えば接合深さが０，５゜μｍ
の場合、従来法によるＭＯ８型トランジスタのソース、
ドレイン領域のシート抵抗は約９００／口であるのに対
し、本発明によるＭＯ８型トランジスタによればソース
、ドレイン領域のシート抵抗は°約５５Ω／口である。As is clear from the figure, for example, the bonding depth is 0.5゜μm.
In the case of , the source of MO8 type transistor according to the conventional method,
The sheet resistance of the drain region is approximately 900Ω/portion, whereas the sheet resistance of the source and drain regions of the MO8 type transistor according to the present invention is approximately 55Ω/portion.
これによシ、本発明によるＭＯ８型トランジスタが従来
法によるＭＯ８型トランジスタ上シも優れている確認で
きる。This confirms that the MO8 type transistor according to the present invention is superior to the conventional MO8 type transistor.
なお、上記実施例では基板の加熱手段としてタングステ
ンハロダンランプを用いたが、これに限らず、その他の
ランプでもよいし、あるいはヒータによシ直接基板とを
加熱処理を行なっても同様の効果が期待できる。In the above embodiment, a tungsten-halodan lamp was used as a heating means for the substrate, but the lamp is not limited to this, and other lamps may be used, or the same effect can be obtained by heating the substrate directly using a heater. can be expected.
上記実施例ではｐ型のＳｉ基板の場合について述べたが
、これに限らず、ｎ型のＳｉ基板の場合についても同様
に適用できる。まだ、上記実施例では、拡散層として基
板表面にソース、ドレイン領域を形成する場合について
述べたが、これに限らず、基板表面に拡散配線層を形成
する場合についても同様に適用できる。In the above embodiment, the case of a p-type Si substrate has been described, but the present invention is not limited to this, and can be similarly applied to the case of an n-type Si substrate. In the above embodiments, the case where the source and drain regions are formed on the surface of the substrate as a diffusion layer is described, but the present invention is not limited to this, and can be similarly applied to the case where a diffusion wiring layer is formed on the surface of the substrate.
上記実施例では半導体基体としてＳｉ基板を用いた場合
について述べたが、これに限らず、絶縁性基板上に設け
られた半導体層を用いた場合についても同様に適用でき
る。In the above embodiment, a case was described in which a Si substrate was used as the semiconductor substrate, but the present invention is not limited to this, and the present invention can be similarly applied to a case in which a semiconductor layer provided on an insulating substrate is used.
以上詳述した如く本発明によれば、シート抵抗の変化、
接合深さの変化絶縁耐圧の低下釜ひにコンタクト径の広
がシ等の和ｌ々の問題点を解消した高集積度で高徊頼性
の半導体装置の製造方法を提供できるものである。As detailed above, according to the present invention, changes in sheet resistance,
It is possible to provide a method for manufacturing a semiconductor device with high integration and high reliability, which solves various problems such as changes in junction depth, decrease in dielectric strength voltage, and increase in contact diameter.
第１図（ａ） 、 （ｔｙ）は従来の半導体装置の製造
方法を工程順に示す断面図、第２図（、）〜（ｄ）は本
発明の一実施例であるＭＯ８型トランジスタの製造方法
を工程順に示す断面図、第３図は従来法及び本発明によ
って得られたＭＯ８型トランジスタのソース、ドレイン
領域の接合深さとシート抵抗の関係を示す特性図である
。
１１・・・ｐ型の８１基板（半導体基体）、１２・・・
熱酸化膜、１３・・・多結晶シリコン層、１４・・・ダ
ート電極、１５・・・ダート絶縁膜、１６・・・ｎ生型
のソース領域、１７・・・ｎ生型のドレインｆｌ、１８
・・・ＰＳＧ膜、１９・・・コンタクトホール、２０・
・・テーパ一部、２１・・・Ａｔ配線。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
第３図
七会洋ざFIGS. 1(a) and 1(ty) are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps, and FIGS. 2(,) to (d) are a method for manufacturing an MO8 type transistor, which is an embodiment of the present invention. FIG. 3 is a characteristic diagram showing the relationship between the junction depth of the source and drain regions and the sheet resistance of MO8 type transistors obtained by the conventional method and the present invention. 11... p-type 81 substrate (semiconductor base), 12...
Thermal oxide film, 13... Polycrystalline silicon layer, 14... Dirt electrode, 15... Dirt insulating film, 16... N-type source region, 17... N-type drain fl, 18
...PSG film, 19...contact hole, 20.
...Taper part, 21...At wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Yoza Shichiai
Claims (2)
むガラス膜を形成する工程と、前記拡散層の一部に対応
するガラス膜を選択的に開孔してコンタクトホールを形
成する工程と、ランプあるいはヒータによシ基体温度が
９００〜１２００℃となるように直接加熱する工程とを
具備することを特徴とする半導体装置の製造方法。(1) A step of forming a glass film containing impurities on a semiconductor substrate having a diffusion layer on the surface, and a step of selectively opening a hole in the glass film corresponding to a part of the diffusion layer to form a contact hole. A method of manufacturing a semiconductor device, comprising the steps of: directly heating the substrate using a lamp or heater so that the temperature of the substrate is 900 to 1200°C.
るいはホウ素−リンケイ酸ガラス験であることを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the glass film containing impurities is a phosphorus-silicate glass film or a boron-phosphosilicate glass film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2720483A JPS59152646A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2720483A JPS59152646A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59152646A true JPS59152646A (en) | 1984-08-31 |
Family
ID=12214565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2720483A Pending JPS59152646A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152646A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249769A (en) * | 1975-10-20 | 1977-04-21 | Hitachi Ltd | Process for production of semiconductor device |
-
1983
- 1983-02-21 JP JP2720483A patent/JPS59152646A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249769A (en) * | 1975-10-20 | 1977-04-21 | Hitachi Ltd | Process for production of semiconductor device |
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