JPS59151400A - 半導体記憶装置 - Google Patents
半導体記憶装置Info
- Publication number
- JPS59151400A JPS59151400A JP58026463A JP2646383A JPS59151400A JP S59151400 A JPS59151400 A JP S59151400A JP 58026463 A JP58026463 A JP 58026463A JP 2646383 A JP2646383 A JP 2646383A JP S59151400 A JPS59151400 A JP S59151400A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- latch circuit
- normal memory
- group
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Static Random-Access Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58026463A JPS59151400A (ja) | 1983-02-17 | 1983-02-17 | 半導体記憶装置 |
US06/579,604 US4606013A (en) | 1983-02-17 | 1984-02-13 | Redundancy-secured semiconductor memory |
DE19843405608 DE3405608A1 (de) | 1983-02-17 | 1984-02-16 | Redundanzgesicherter halbleiterspeicher |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58026463A JPS59151400A (ja) | 1983-02-17 | 1983-02-17 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59151400A true JPS59151400A (ja) | 1984-08-29 |
JPS6350799B2 JPS6350799B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1988-10-11 |
Family
ID=12194202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58026463A Granted JPS59151400A (ja) | 1983-02-17 | 1983-02-17 | 半導体記憶装置 |
Country Status (3)
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4829481A (en) * | 1985-08-20 | 1989-05-09 | Sgs-Thomson Microelectronics, Inc. | Defective element disabling circuit having a laser-blown fuse |
JPS6265300A (ja) * | 1985-09-18 | 1987-03-24 | Toshiba Corp | 半導体記憶装置 |
US4714839A (en) * | 1986-03-27 | 1987-12-22 | Advanced Micro Devices, Inc. | Control circuit for disabling or enabling the provision of redundancy |
US4798976A (en) * | 1987-11-13 | 1989-01-17 | International Business Machines Corporation | Logic redundancy circuit scheme |
KR930003553B1 (ko) * | 1990-05-18 | 1993-05-06 | 현대전자산업주식회사 | 집적회로 컬럼수정(Column Repair)의 회로 |
US5327381A (en) * | 1992-06-03 | 1994-07-05 | Mips Computer Systems, Inc. | Redundancy selection apparatus and method for an array |
KR100268882B1 (ko) * | 1998-04-02 | 2000-10-16 | 김영환 | 반도체 메모리 장치의 보안 회로 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3765002A (en) * | 1971-04-20 | 1973-10-09 | Siemens Ag | Accelerated bit-line discharge of a mosfet memory |
US4228528B2 (en) * | 1979-02-09 | 1992-10-06 | Memory with redundant rows and columns | |
US4459685A (en) * | 1982-03-03 | 1984-07-10 | Inmos Corporation | Redundancy system for high speed, wide-word semiconductor memories |
-
1983
- 1983-02-17 JP JP58026463A patent/JPS59151400A/ja active Granted
-
1984
- 1984-02-13 US US06/579,604 patent/US4606013A/en not_active Expired - Lifetime
- 1984-02-16 DE DE19843405608 patent/DE3405608A1/de active Granted
Also Published As
Publication number | Publication date |
---|---|
US4606013A (en) | 1986-08-12 |
DE3405608A1 (de) | 1984-08-23 |
JPS6350799B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1988-10-11 |
DE3405608C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-04-25 |
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