JPS59151156A - Mask designing sheet - Google Patents

Mask designing sheet

Info

Publication number
JPS59151156A
JPS59151156A JP58019086A JP1908683A JPS59151156A JP S59151156 A JPS59151156 A JP S59151156A JP 58019086 A JP58019086 A JP 58019086A JP 1908683 A JP1908683 A JP 1908683A JP S59151156 A JPS59151156 A JP S59151156A
Authority
JP
Japan
Prior art keywords
sheet
conductive material
conductive
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58019086A
Other languages
Japanese (ja)
Inventor
Junichi Miyamoto
順一 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58019086A priority Critical patent/JPS59151156A/en
Publication of JPS59151156A publication Critical patent/JPS59151156A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof

Abstract

PURPOSE:To obtain a mask designing sheet capable of rapid feedback in response to designing of a circuit or pattern and shortening of time for manufacture of a semiconductor device by forming an electrically conductive material layer on the predetermined part for forming a conductive layer on an insulating base. CONSTITUTION:A mask designing sheet 2 is obtained by forming a layer 2 of a conductive material, such as aluminum foil, on the predetermined part for forming a conductive layer, such as wiring parts or diffusion parts, of an insulating base 1 made of a blank sheet having lines for indicating the border line of data drawn on it. In addition, the insulating bases 1, 3 and the conductive material layers 4, 5 may have such an alternate laminated constitution that a part of each conductive material layer is exposed. The presence of disconnection between the 2 points of the conductive line, wiring resistance, capacity between lines, etc. can be electrically confirmed by using said sheet and needles at optional 2 points of the conductive layer, without depending on confirmation by sight, and checking of a drawing, and detection of defective points can be easily and securely achieved.

Description

【発明の詳細な説明】 〔発明の技雨分野〕 本発明は、半導体装置の設計時に用いられるマスク設計
シートに関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a mask design sheet used when designing a semiconductor device.

〔発明の技術的背騎〕[Technical backbone of invention]

周知の如く、半導体装置例えばT、 S Iを製造する
(二はマスク設計シートが一般(二用いられている1、 従来、かかるマスク設計シートは第1図(二示す如く作
製されていた。即ち、まず回路設計を1−だ後、ケ゛−
ト等のパターンを、実際のマスクパターンの100〜1
000倍の大きさの図面l二線引きし、コンピュータに
よる座標取り(ディジタイズ)をした後プロッター(二
よって作画する(・ぐターン設=t )。この作画され
たものがマスク設計シートである。ここで、設計(二修
正や誤りがある場合は再度回路膜diを行なう。つづい
て、このマスク設計シート金目視で検図を行なう。ここ
で、設計(二修正等がある場合は再度回路設計や・ぐタ
ーン設計を行なう。以上より、作られたマスク設計シー
トに栽づいてL S Iのフォトエツチングプロセス(
二使才つれるマスクを製作する(マスクメーキング)。
As is well known, when manufacturing a semiconductor device such as T or SI, a mask design sheet is generally used (1). Conventionally, such a mask design sheet was prepared as shown in FIG. , firstly, after the circuit design,
100 to 1% of the actual mask pattern.
After drawing two lines on a drawing of 1,000 times the size and digitizing the coordinates using a computer, draw the drawing using a plotter (two lines = t). This drawing is the mask design sheet.Here Then, if there are any corrections or errors in the design, perform the circuit design again. Next, visually inspect the mask design sheet.・Carry out turn design. From the above, the LSI photoetching process (
Making masks for the second envoy (mask making).

こうしたマスクin基いてLSIか製造され、LSIの
拝1dliがなされる。そして、その評価に基づいて前
記回路設計やパターン設計へのフィードバックが行な才
つれる。
LSIs are manufactured based on these masks, and the LSI's design is completed. Based on the evaluation, feedback is provided to the circuit design and pattern design.

〔背景技術の問題点〕[Problems with background technology]

しかしながら、前述したマスク設計シート(二よれは、
目視で検図を行なうため、配線等の導電層の結線ミスの
発見、同導電層の寄生抵抗の見積りが十分に出来ないと
いう欠点があった。
However, the mask design sheet mentioned above (the two sides are
Since the drawings are inspected visually, there is a drawback that it is not possible to detect wiring errors in conductive layers such as wiring or to adequately estimate the parasitic resistance of the conductive layers.

これらの対策として、前者C二ついては通常、計算機(
二よって設計ルールのチェック全行なっているが、導電
層が誤って接続さ九ている場合は発見できない。また、
後者(二ついては計算機によってレイアク)k読みとり
導電層から計算する方法もあるが、幅と長さという2次
元の計算は一般に莫大な計算時間がかかる。しかも、導
電層の任意の2点間の抵抗は実質測定できず、従って導
電層抵抗などは実際のテップが出来上がってから測定す
るしかないが、かかる場合チップが小さすき゛るため針
で任意の点をあたることは出来ない。
As a countermeasure for these, for the former two C, we usually use a computer (
Therefore, although we have performed all design rule checks, we cannot detect cases where conductive layers are incorrectly connected. Also,
There is a method for calculating the latter (the latter two are by computer) by calculating from the k-reading conductive layer, but calculating the two dimensions of width and length generally takes an enormous amount of calculation time. Moreover, it is virtually impossible to measure the resistance between any two points on the conductive layer, so the only way to measure the conductive layer resistance is after the actual step is completed. I can't hit it.

前述したことは、近年集積回路の大容量化が進んで導電
層がより複雑となり、導電層がチップサイズの増加と共
(二長くなるC二したがって誤接続、誤配線の可能性が
増大するととから、一層顕著となる。また、大容量化や
素子の微細化に進むにつれ、導電層の抵抗の効果が相対
的に上昇する傾向にある。このことは、回路設計が正確
でかつそれを忠実(ニパターンレイアウト化しても、L
SIが出来上がったとき、最悪の場合動作しない可能性
があることを意味する。
As mentioned above, as the capacity of integrated circuits has increased in recent years, conductive layers have become more complex, and as the chip size increases (2), the possibility of incorrect connections and wiring increases. In addition, as the capacity increases and devices become smaller, the effect of the resistance of the conductive layer tends to increase relatively.This means that the circuit design must be accurate and faithful to it. (Even if it is a two-pattern layout, L
This means that in the worst case, when the SI is completed, it may not work.

なお、前述した事例はパターン設計後目視C二よって発
見された場合であるが、もし発見されなかった場合は長
い時間をかけてLSIの製作や、不良解析を行なった後
発見されるという可能性がある。したがって、回路設計
、〕七ターン設計へのフィードバックに多大な時間を要
する。
Note that the above-mentioned case was discovered by visual inspection after pattern design, but if it were not discovered, there is a possibility that it would be discovered after a long period of time spent manufacturing the LSI or performing defect analysis. There is. Therefore, it takes a lot of time to provide feedback to the circuit design and seven-turn design.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情ζ二鑑みてなされたもので、回路設計
やパターン設計(二速やかにフィードバックして半導体
装置の製作期間を短縮でさるマスク設計シートを提供す
ること全目的とする。
The present invention has been made in view of the above-mentioned circumstances, and its entire purpose is to provide a mask design sheet that can provide quick feedback for circuit design and pattern design (2) to shorten the manufacturing period of semiconductor devices.

〔発明の概要〕[Summary of the invention]

本発明は、絶縁基材上の導電層形成予定部(ニ導電性物
質層を形成すること(二よって、〕9ターン設計後の検
図において、導電層の断続の有無や同導電層の寄生抵抗
を電気的に検知でき、もって回路設計やパターン設計(
二速やかにフィードバック可能とし、半導体装置の製作
期間の短縮できるものである。
The present invention examines the area on which a conductive layer is to be formed (2 conductive material layers are formed) on an insulating base material in an inspection after 9-turn design to determine whether or not there are discontinuities in the conductive layer, and whether or not the conductive layer is parasitic. Resistance can be detected electrically, allowing circuit design and pattern design (
This enables quick feedback and shortens the manufacturing period of semiconductor devices.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第2図(a) 、 Fblを
参照して説明する。
Hereinafter, one embodiment of the present invention will be described with reference to FIG. 2(a) and Fbl.

図中の1は、大きさが100(FAX100偏でかつ白
紙上ζニデータの境界線を示す線がひかれた絶縁基材で
ある。この絶縁基材1上の配線や拡散領域等の導電層形
成予定部C二は、例えば届箔からなる導電性物質層2・
・・が形成されている。なお、導電性物質層2のシート
抵抗は必ずしも実デバイスの値に準する必要はない。
1 in the figure is an insulating base material with a size of 100 (FAX 100 bias) and on which a line indicating the boundary line of ζ data is drawn on a blank sheet of paper. Conductive layers such as wiring and diffusion regions are formed on this insulating base material 1. The planned portion C2 includes a conductive material layer 2 made of, for example, foil.
... is formed. Note that the sheet resistance of the conductive material layer 2 does not necessarily have to conform to the value of the actual device.

しかして、前述した構造のマスク設計シートによれば、
絶縁基材1上の配線や拡散領域等の導電層形成予定部(
二導電性物質層2・・・が形成されているため、導電層
が配線であればその導電層の任意の2点を針なとで接触
すること(二よりその2点間の断続の有無、配線抵抗を
マスク設計シートカ゛5電気的に確認できるとともC二
、導電層が拡散領域であれは前述と同様(ニしてそれら
のコンタクト間の断続の有無や抵抗會庫気的シ二確認で
きる。
However, according to the mask design sheet with the structure described above,
Areas where conductive layers are to be formed, such as wiring and diffusion areas on the insulating base material 1 (
Since two conductive material layers 2... are formed, if the conductive layer is a wiring, it is necessary to touch any two points of the conductive layer with a needle. If the conductive layer is a diffusion region, the wiring resistance can be electrically confirmed using the mask design sheet 5. If the conductive layer is a diffusion region, it is the same as above (and the presence or absence of discontinuity between those contacts and the electrical resistance can be confirmed). can.

なお、本発明に係るマスク設計シートは上記実施例のも
の(二限らず、例えは第3図(al 、 tbl i二
示す如く、絶縁基材1,3と導電物質層4,5と全交互
に各導電物質層4,5が一部露出するよう≦二積層した
構造のものでもよい。こうした構造のマスク設計シート
(=よれは、導電物質層4.5間の容量全測定すること
ができる。
It should be noted that the mask design sheet according to the present invention is not limited to that of the above embodiments (for example, as shown in FIG. It is also possible to have a structure in which ≦2 layers are stacked so that each of the conductive material layers 4 and 5 is partially exposed.A mask design sheet for such a structure (= waviness allows the total capacitance between the conductive material layers 4 and 5 to be measured. .

〔発明の効果〕 以上詳述した如く本発明C二よれは、パターン設計後の
検図C二おいて、導電層の断続の有無や導電層の寄生抵
抗を電気的に検知でき、もって回路設計やパターン設計
に運やかにフィードバック可能とし、半導体装置の製作
期間全短縮できるマスク設計シートラ提供でき7るもの
である。
[Effects of the Invention] As described in detail above, the present invention C2 allows electrical detection of the presence or absence of discontinuities in the conductive layer and the parasitic resistance of the conductive layer in the inspection drawing C2 after pattern design, thereby improving circuit design. It is possible to provide a mask design sheet that can be fed back to the mask pattern design and pattern design, and can shorten the entire manufacturing period of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、L S I製造工程を示すフ[1−チャート
、第2図ta+は本発明の一実施例を示すマスク設計シ
ートの平面図、同図(b)は同図ta+のX−X線ζ二
沿う断面図、第3図(alは本発明の他の実施例を示す
マスク設計シートの平面図、同図telは同図(α)の
Y−Y線C二沿う断面図である。 1.3・・・絶縁基材、2,4.5・・・導電性物質層
。 第1図 L−−、J 第2図 (a) ノ 第3図 (a) (b)
FIG. 1 is a diagram showing the LSI manufacturing process, FIG. 2 (ta+) is a plan view of a mask design sheet showing an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view taken along the X-ray ζ2 (al is a plan view of a mask design sheet showing another embodiment of the present invention, and tel of the same figure is a cross-sectional view taken along the Y-Y line C2 of the same figure (α). 1.3... Insulating base material, 2,4.5... Conductive material layer. Figure 1 L--, J Figure 2 (a) - Figure 3 (a) (b)

Claims (1)

【特許請求の範囲】 (])半導体装置の設計時(二用いられるマスク設計シ
ート(二おいて、絶縁基材上の辱重層形成予定部(二桿
′屯性物實層をJlら成したこと全特徴とするマスク設
計シート。 (2)絶縁基材と導電性物質層とを交互ζ二各導屯性物
看層が一部蕗出するようイニ積層したことを特徴とする
特許14求の範囲第1項記載のマスク設計シート。
[Scope of Claims] (2) When designing a semiconductor device (2) A mask design sheet used (2) A mask design sheet (2) in which a layer on an insulating base material is to be formed (2) (2) Patent No. 14 sought, characterized in that an insulating base material and a conductive material layer are laminated alternately so that each conductive material layer partially protrudes. A mask design sheet according to item 1 of the scope.
JP58019086A 1983-02-08 1983-02-08 Mask designing sheet Pending JPS59151156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58019086A JPS59151156A (en) 1983-02-08 1983-02-08 Mask designing sheet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58019086A JPS59151156A (en) 1983-02-08 1983-02-08 Mask designing sheet

Publications (1)

Publication Number Publication Date
JPS59151156A true JPS59151156A (en) 1984-08-29

Family

ID=11989638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58019086A Pending JPS59151156A (en) 1983-02-08 1983-02-08 Mask designing sheet

Country Status (1)

Country Link
JP (1) JPS59151156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817301A (en) * 1987-05-27 1989-04-04 Belanger, Inc. Apparatus for drying vehicles

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817301A (en) * 1987-05-27 1989-04-04 Belanger, Inc. Apparatus for drying vehicles

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