JP2002057195A - Method for preparing data for defect analysis in examination of electronic device and system for analyzing examination data for electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To narrow down a defect factor caused by the defect of an electronic device for forming the circuit patterns of multiple layers by analyzing the defect to occur in each of layers of the electronic device. SOLUTION: On the basis of the result of a defect examination to be performed each time the layer of a wafer is formed, processing 41 is performed for making correspondent defect coordinates between respective examinations to recognize the defect and further, processing 43 is performed for deciding the size of that defect for each recognized defect to unify the defect sizes different for each examination of the defect. Next, processing 45 is performed for excluding fine defects to narrow down defect data as a target of defect analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection method applied to a production line of an electronic device or the like for forming a multilayer circuit pattern, and an inspection system for utilizing the method. In particular, it is a technique for effectively utilizing defect data detected by defect inspections such as a foreign substance inspection and an appearance inspection to improve the yield.

[0002]

2. Description of the Related Art In general, an electronic device represented by a semiconductor integrated circuit is manufactured by a process in which layers such as circuit patterns are multilayered on a silicon wafer to manufacture a plurality of chips (elements). It can be broadly divided into a post-process of separating and completing the product.

Most of the defects that occur during manufacturing occur in the preceding process, and the improvement of the yield in the preceding process is the key to the business of electronic devices. Here, the yield in the previous process refers to the non-defective rate determined by the result of the electrical function test (probe test), which is the final test in the previous process, that is, the ratio of non-defective chips to the total number of chips in a wafer.

[0004] Defects that cause yield deterioration in the previous process can be roughly classified into functional defects and parametric defects. A functional defect is a defect in which a circuit pattern is disconnected or short-circuited due to foreign matter or a pattern defect (hereinafter, these are collectively referred to as “defects”), and the circuit does not operate normally. On the other hand, a parametric defect is a defect in which the operation timing of a transistor, the capacitance of a capacitor, and the like are not completed according to design specifications due to minute variations in a process such as a circuit size and an oxide film thickness.

For the purpose of discovering the cause of the malfunction at an early stage and taking countermeasures, every time a layer such as a circuit pattern is formed,
A defect inspection is performed using a foreign substance inspection device or a visual inspection device.
In the defect inspection, information such as the position, size, and number of defects is detected. A defect detected by a defect inspection of a certain layer is not always a defect of the layer. For example, when a defect occurs in a certain layer, the film may be raised in a convex shape due to the defect even after the next layer is formed. Therefore, the defect
It is also detected in the next layer defect inspection. Therefore, it is necessary to perform a defect inspection on the same wafer for each layer, and to determine a defect detected at the same position between layers from the result of the defect inspection for each layer as the same defect. Here, the same position refers to the X of the inspection apparatus.
Considering the reproducibility of the Y stage and the alignment error of the wafer, it is a place having an allowable range. Among the defects at the same position, the defect in the layer detected first is called a net defect, and the defect detected in the subsequent layer is called a carry-in defect. Excluding minute defects that cannot be detected by the inspection device, the net defects in each layer become defects generated in each layer. Taking some measure against the process having a large number of net defects and reducing the number of defects is one defect analysis method for improving the yield.

[0006] However, even if there are many net defects in a certain layer, the net defects in that layer do not always cause the yield deterioration. Defects generated in that layer may not cause yield degradation due to the structure of the circuit pattern. Therefore, as a method of measuring the degree of influence on the yield degradation for each layer, there is a technique for calculating the degree of influence of the yield. The yield impact is calculated for each layer, and the layer to be countermeasured is prioritized based on the calculated value.

[0007] As one of the methods for calculating the yield impact, a conventional "Semicon Kansai '97 ULSI Technical Seminar Proceedings" p
A paper by S. Hall et al., p.4 / 42-4 / 47 (1997), "Yield M
onitoring and Analysis in Semiconductor Manufactur
ing "and the like.

FIG. 8 is a diagram showing this fatality rate calculation method. The method uses the coordinates of the net defect and the results of the electrical inspection.

In FIG. 8, a circle indicates a wafer of an electronic device, black circles 121 to 123 indicate a net defect, a white square indicates a non-defective chip, and a hatched square indicates a defective chip. Is shown. A table 125 is created from these pieces of information. That is, first, the number of non-defective non-defective chips GD and the number of non-defective non-defective chips GN
D, the number BD of defective chips with defects, the number BND of defective chips without defects, and the criticality rate KR and the yield impact YI are calculated from the following equations.

[0010]

(Equation 1)

[0011]

(Equation 2)

[0012]

The most important object of the defect inspection apparatus is to detect a defect from a semiconductor integrated circuit in a manufacturing process. Semiconductor integrated circuits are increasingly miniaturized, and the size of defects to be detected is becoming smaller. Defect inspection equipment
In order to detect minute defects, the sensitivity has been increased, and the number of defects detected in the defect inspection is increasing.

Using the above-described method for calculating the fatality rate, the
In order to calculate R and the yield impact YI, Equations 1 and 2 are used.
And need to be calculated. With the increase in the sensitivity of the defect inspection apparatus, the number of detected defects has increased, and it has often been observed that there is no chip having no defect. For this reason, GND + BND of Equation 1 becomes zero or a value as close to zero as possible, and it becomes difficult to calculate Equation 1. Equation 2 cannot be calculated because the calculation result of Equation 1 is used.

[0014] As a solution to this, it is easy to consider using the inspection sensitivity of the defect inspection apparatus with reduced sensitivity, or simply excluding minute defects among the detected defects from analysis targets. However, if this is done, it is impossible to achieve the purpose of quickly narrowing down the process of generating a fatal defect that causes an electrical failure.

For example, it is assumed that a defect is generated by using a highly sensitive defect inspection apparatus, and that the defect can be detected by a defect inspection immediately after the occurrence. At the stage of the inspection, there are many cases of minute defects. As the manufacturing process progresses,
A film is formed on the defect, and the defect becomes large. Therefore, in the subsequent defect inspection, the defect is detected as a large defect and grows into a fatal defect. Here, as described above, if the inspection sensitivity of the defect inspection apparatus is reduced and used, or if a process of simply excluding a minute defect from the detected defects is performed from the analysis target, the defect is still minute. The source of the defect cannot be identified. A defect can be detected only when the defect becomes large, and a process of generating a fatal defect is erroneously recognized. That is, in the process of using the inspection sensitivity of the defect inspection apparatus with reduced sensitivity, or simply excluding minute defects among the detected defects from the analysis target, the advantage of the high-sensitivity defect inspection apparatus is wasted. .

An object of the present invention is to solve the above-mentioned problems by narrowing down a cause of a defect caused by a defect in an electronic device when analyzing a defect occurring in each layer of an electronic device forming a multilayer circuit pattern. To make it possible.

[0017]

SUMMARY OF THE INVENTION The present invention is a method for solving the above-mentioned problems. A computer observes a process in which the small defect grows and becomes large, and determines a defect that grows large and a defect that does not grow. Since a defect that does not grow has a low probability of becoming a fatal defect, it is excluded from the analysis target when calculating the fatality rate and the yield impact.

That is, the present invention is a method of creating data for defect analysis in the inspection of an electronic device manufactured through a plurality of manufacturing processes, and includes a method of manufacturing data generated in each of a plurality of predetermined manufacturing processes. A detection defect map data creation step of detecting a defect on an object and creating detection defect map data including defect position information and defect size information for each manufacturing process; and a plurality of detection defect map data created in the detection defect map data creation step. Based on the defect position information in the detected defect map data, the same defect is recognized, and the detected defect map association data is created by unifying the defect size information for each detected defect map data into one value for the recognized same defect. The detected defect map associating data created in the detected defect map associating data creating process A detection defect map associating division data creating step of creating detection defect map associating division data based on the size information, wherein the detection defect map associating division created in the above detection defect map associating division data creating step The object is achieved by providing data as defect analysis data.

Here, in the detected defect map associating division data process, the detected defect map associating data may be divided according to whether or not the defect size information is equal to or smaller than a predetermined threshold value. it can.

Further, in the process of creating the detected defect map associating data, a defect whose defect position information is within a predetermined error range is recognized as the same defect, and the detected defect map for each manufacturing process of the same defect is recognized. The maximum value of the defect size information in the data can be unified into one value as the defect size information.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

Before describing an embodiment of the present invention, an in-line defect inspection of a semiconductor wafer will be described with reference to FIG.

In general, the manufacturing process of a semiconductor wafer can be divided into several process zones. Then, a defect inspection is performed at the end of each process zone. In the defect inspection, the coordinates and size of the defect are output. Then, an electrical inspection is performed at the end of the wafer manufacturing process, and a good product and a defective product are determined for each chip formed on the wafer.

In the example shown in FIG. 2, the manufacturing process is divided into three process zones, and a defect inspection is performed at the end of each process zone.

In FIG. 2, reference numeral 31 denotes the inspection result of the defect inspection 1, 32 denotes the inspection result of the defect inspection 2, and 33 denotes the inspection result of the defect inspection 3. For example, the inspection result 31 is a defect inspection 1
To detect five defects, and assign defect numbers from 1 to 5, respectively. For defect number 1, the X coordinate is “104” and the Y coordinate is “2”.
53 ", meaning that the size is" 8 ".

In FIG. 2, reference numeral 20 denotes the result of the electrical inspection, which is output so that the positions of the non-defective chips G and the defective chips B in the wafer surface can be recognized.

FIG. 3 is a diagram showing the inspection result 31 of the defect inspection 1 as a map of a wafer.

In FIG. 3, arrows indicate coordinate axes, circles indicate wafers, white squares indicate chips, and 10
Black circles 1 to 105 indicate the positions of the defects. The defect number 1 of the inspection result 31 is a black circle 101, the defect number 2 is a black circle 102, the defect number 3 is a black circle 103, the defect number 4 is a black circle 104, and the defect number 5 is a black circle 105. By looking in this way, the position of the defect can be associated with the chip.

FIG. 1 is an explanatory view showing one embodiment of a semiconductor wafer inspection method according to the present invention.

In this example, a method for analyzing the result of the defect inspection shown in FIG. 2 will be described.

In FIG. 1, reference numeral 31 denotes the inspection result of the defect inspection 1, 32 denotes the inspection result of the defect inspection 2, and 33 denotes the inspection result of the defect inspection 3. These inspection results 31 to 33 correspond to the above-described detected defect map data.

In this embodiment, as shown in FIG. 1, first, a process 41 for associating defect coordinates between inspections based on inspection results 31 to 33 is performed.

This processing 41 is because, for example, the defect detected in the defect inspection 2 is not always the defect generated in the process zone 2. When a defect occurs in the process zone 1, even after the film formation in the process zone 2, the film may bulge in a convex shape due to the influence of the defect. Therefore, the defect
It is also detected in the defect inspection 2 of the process zone 2. Therefore, the same wafer is subjected to defect inspection in each process zone, and defects detected at the same position between inspections are determined to be the same defect. here,
The same position is a place having an allowable range in consideration of the reproducibility of the XY stage of the inspection apparatus and the alignment error of the wafer.

Among the defects at the same position, the first defect detected in a layer is called a net defect, and the defect detected in a subsequent layer is called a carry-in defect. Excluding minute defects that cannot be detected by the inspection device, the net defects in each layer become defects generated in each layer. The defect number 2 of the inspection result 32 is the defect number 1 of the inspection result 31
And the values of X and Y differ by one. This can be determined to be the same position when the allowable range is 1, for example, in the X direction and 1 in the Y direction. Therefore, these defects are determined to be the same defect.

In FIG. 1, reference numeral 42 denotes inspection results 31 to 3
3 is data obtained by comparing the respective defect data and determining the same defect.

In the coordinate association result data 42, the defect data connected by a solid line is the same defect. The defect number 1 of the defect inspection 1 is the same defect as the defect number 2 of the defect inspection 2 and the defect number 2 of the defect inspection 3. The defect number 4 of the defect inspection 1 is the same defect as the defect number 3 of the defect inspection 2. The defect number 5 of the defect inspection 1 is the same defect as the defect number 4 of the defect inspection 3. The defect number 1 of the defect inspection 2 is the same defect as the defect number 1 of the defect inspection 3.

Next, in this embodiment, as shown in FIG. 1, a process 43 for determining the size of each defect is performed on the coordinate association result data 42.

This process 43 is a process for unifying defects which are determined to be the same, since the defect size differs for each defect inspection.

For example, the defect number 1 of the inspection result 31 of the defect inspection 1 is detected as having a defect size of “8” in this inspection. However, the defect coordinate matching result data 4
Looking at 2, defect number 1 of defect inspection 1 is also defect number 2 of defect inspection 2. In the defect inspection 2, the defect size is “31”. This defect is also the defect number 2 of the defect inspection 3. In the defect inspection 3, the defect size is “6”.
4 ". As described above, the defect size differs for each defect inspection even for the same defect.

Therefore, in the present process 43, the maximum value of the defect data determined as the same defect is determined as the size of the defect. The result is 44, which corresponds to the detected defect map association data described above.

Next, in the present embodiment, as shown in FIG.
A process 45 for excluding minute defects is performed.

In the present processing 45, a threshold value is set for the defect size, and a defect whose defect size is equal to or smaller than the threshold value is determined as a minute defect and is excluded.

For example, assume that the threshold value is "10". The defect number 4 of the defect inspection 1 has the defect size “9” and is determined to be a minute defect, and this data and the data of the defect number 3 of the defect inspection 2 which is the same defect are excluded. Defect inspection 1
The defect number 5 is a defect size “6” and is determined to be a minute defect, and this data and the data of the defect number 4 of the defect inspection 3 which is the same defect are excluded. Further, the defect number 3 of the defect inspection 3 is the defect size “3”, which is determined as a minute defect, and this data is excluded. Thus, the result of excluding the minute defect is 46, which corresponds to the above-described detected defect map association divided data.

Although the defect data determined to be minute defects is deleted here, an exclusion flag item may be created and an exclusion mark may be added instead of deleting.

Using the data 46 thus obtained, a defect analysis is performed.

As an example of the defect analysis, an example in which the yield influence is obtained by applying the fatality rate calculation method shown in the prior art will be described with reference to FIG.

In FIG. 4, reference numeral 46 denotes the data (result of removing minute defects) obtained in FIG.
It is the result of the electrical inspection shown by.

In FIG. 4, reference numerals 51, 52, 53
Is a result of drawing a wafer map of a net defect, and is drawn by the method shown in FIG. Open squares indicate good chips, hatched squares indicate defective chips,
These are color-coded based on the result of the electrical test 20 (G / B).

The yield influence by the criticality ratio calculation method is “14%” from the wafer map 51 and the wafer map 52
From the wafer map 53 and “8%” from the wafer map 53.

Reference numeral 55 is a graph of the obtained yield influence degree, which is data output as an analysis result. From this analysis result 55, it is required for the manufacturing line to take the highest priority on the net defect of the defect inspection 1.
That is, it is understood that it is most desirable to improve any of the manufacturing apparatuses and manufacturing processes in the process zone 1.

In the above-described example, in the processing 45 for excluding minute defects, a threshold value is set for the defect size, and a defect whose defect size is equal to or smaller than the threshold value is determined to be a minute defect and is excluded. There is also a method of determining the size (threshold) of a minute defect to be excluded as described below.

FIG. 5 is an explanatory diagram showing an example of a method for determining the size of a minute defect to be excluded.

There is a critical area method as a simulation for determining the probability that a defect becomes defective using design layout data. This is disclosed in JP-A-48-4037.
As shown in FIG. 5, a curve 71 is obtained by taking the defect size on the horizontal axis and the probability that the defect becomes defective on the vertical axis as shown in FIG. is there.

The curve 71 indicates that the larger the defect size, the higher the probability of failure.

In FIG. 5, reference numerals 111 to 114 are examples in which circuit patterns are drawn from design layout data. Here, defect data is generated by Monte Carlo simulation, and the probability of a short circuit or disconnection is determined by the defect data. In a simulation using defect data of a small size such as 81 to 84, no short circuit or disconnection occurs.
On the other hand, in a simulation using defect data having a size larger than 81 to 84, such as 91 to 94, a short circuit occurs as indicated by 93, and a disconnection occurs as indicated by 94. A simulation is performed using the defect data having such various sizes, and a curve 71 is obtained.

Then, from the curve 71, for example, a defect size such that the probability that a defect becomes defective becomes “10%” or less is determined, and this is determined as a threshold. It can be defined as a defect.

In this example, a result of a simulation performed on design layout data of one layer in a multilayer circuit pattern is shown. Curve 71 may be obtained by using design layout data of a layer in which a functional failure is likely to occur, and a threshold value of a minute defect may be obtained.

FIG. 6 is an explanatory diagram showing an example of design layout data used when performing the simulation in FIG.

The design layout data is graphic drawing data used when generating a mask pattern at the time of exposure. Therefore, vector information for graphic drawing is provided. In this example, the example of the structure of the design layout data for drawing the circuit patterns 115 to 118 is shown in FIG.
Indicates the type.

In FIG. 6, (1) describes all the figures by vector information, and (2) describes that the same shape is repeatedly drawn. In both cases, the figures to be drawn are the same, and either data may be used.

Hereinafter, a specific example of a system configuration for realizing the present embodiment will be described.

FIG. 7 is a block diagram showing a configuration example of a system for realizing the present embodiment.

In FIG. 7, reference numeral 61 denotes a defect inspection device;
Is an electrical inspection device, 63 is a CAD system, 64 is a local area network (LAN), and 65 is an analysis station.

The defect data such as the inspection results 31 to 33 described above are obtained by using the defect inspection device 61. The defect data obtained by using the defect inspection device 61 is
The data is stored in the inspection result database 653 from the data collection unit 650 of the analysis station 65 via the LAN 64.

Inspection result data such as the above-described non-defective / defective product map 20 is obtained by using the electric inspection device 62. The inspection result data obtained by using the electrical inspection device 62 is also stored in the inspection result database 653 from the data collection unit 650 of the analysis station 65 via the LAN 64.

On the other hand, the above-described design layout data, C
It is obtained by designing with the AD system 63. C
The design layout data designed and obtained by the AD system 63 is transmitted to the analysis station 65 via the LAN 64.
Is stored in the design layout database 654 from the data collection unit 650.

In the analysis station 65, the defect data 31 to 33 and the non-defective / defective product map 20 are read out from the inspection result database 653 to the data analysis unit 651, and the operation of the present embodiment described above is performed by the data analysis unit 651. Done.

The analysis result by the data analysis unit 651 is provided to the analyst via the result output unit 652.

The design layout data stored in the design layout database 654 is also transmitted to the data analysis unit 6.
The data is read out to 51 and a simulation is performed by the data analysis unit 651 in order to set the threshold value of the minute defect.

FIG. 9 is a block diagram showing a configuration example of a system for realizing the present embodiment.

In the configuration example shown in FIG. 9, the CAD system 63 is omitted from the system configuration shown in FIG. 7, and the design layout database 654 is omitted from the analysis station 65. In the case of this configuration, the threshold value for determining a minute defect is not determined from the design layout data but is determined artificially.

In the above description, as an example of the defect analysis performed by using the data 46 shown in FIG. 1, an example in which the yield influence degree is obtained by applying the fatality rate calculation method shown in the prior art is given. However, the method used for analysis is not limited to the fatal rate calculation method.

For example, instead of the fatal rate calculation method, “Intern
ational Symposium on Semiconductor Manufacturin
g ”, pp.127-130 (1999) by Ono et al.
n-defective area analysis for quantifying yield im
The yield influence may be obtained by applying the method described in “pact”. Such an example will be described with reference to FIG.

This method is called a defect-free area analysis method.

In FIG. 10, reference numeral 46 denotes the data (results obtained by removing minute defects) obtained in FIG. 1, and reference numeral 20 denotes the results of the electrical inspection shown in FIG.

In FIG. 10, reference numeral 56 denotes data 4
6 shows the result of drawing a wafer map of the defect data of the defect inspection 1 in FIG.
And the result of drawing a wafer map of the accumulation of the defect data of the defect inspection 2, that is, the logical sum.
7 shows the result of drawing a wafer map of the accumulated defect data of the defect inspection 1, defect inspection 2, and defect inspection 3 of FIG. Open squares indicate non-defective chips, hatched squares indicate defective chips, and these are 20 (G / B) as a result of the electrical inspection.
Are color-coded based on

From the wafer map 56, the yield of a chip without a defect is “0.778”, from the wafer map 57, the yield of a chip without a defect is “0.875”, and from the wafer map 58, the yield of a chip without a defect is It can be calculated as "1.000".

Therefore, in the defect inspection 1, the yield influence by the defect-free area analysis method is set to 0.77
The quotient divided by 8 can be subtracted from 1 to get 0.14. In the defect inspection 2, a quotient obtained by dividing “0.778” by “0.875” is subtracted from “1” to obtain “0.11”. In the defect inspection 3, a quotient obtained by dividing “0.875” by “1” can be subtracted from “1” to obtain “0.13”.

Reference numeral 59 denotes a graph of this result, which is data output as an analysis result.
From this analysis result 59, it can be seen that it is most desirable to improve any of the manufacturing apparatuses and manufacturing processes in the process zone 1, as in the case of the criticality ratio calculation method. Here, the difference between the analysis result 55 and the analysis result 59 is due to an error generated due to the small number of chips illustrated.

Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment. Further, in the present embodiment, an example in which the defect inspection is performed three times has been described, but the number is not limited to three.

[0081]

As described above, according to the present invention,
When analyzing a defect occurring in each layer of an electronic device forming a multilayer circuit pattern, it is possible to narrow down a cause of a defect due to a defect of the electronic device.

Therefore, it is possible to quantify the degree of influence of a defect generated in the process of manufacturing an electronic device such as a semiconductor, and it is effective to easily and effectively grasp a manufacturing process which needs to be intensively dealt with. It is. In particular, a highly sensitive defect inspection apparatus can be effectively used, and this effectively contributes to defect analysis and yield improvement.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing an embodiment of an electronic device inspection method according to the present invention.

FIG. 2 is an explanatory diagram showing a defect inspection and an electrical inspection in a wafer manufacturing process and data of the results thereof.

FIG. 3 is an explanatory diagram showing correspondence between defect data and a wafer map.

FIG. 4 is an explanatory diagram showing an example of a method for obtaining a yield influence degree.

FIG. 5 is an explanatory view showing a simulation method for measuring a probability that a defect becomes defective.

FIG. 6 is an explanatory diagram showing the structure of design layout data.

FIG. 7 is an exemplary block diagram showing a configuration example of a system for realizing the embodiment;

FIG. 8 is an explanatory diagram showing a method of calculating a fatality rate and a yield influence degree by a fatality rate calculation method.

FIG. 9 is a block diagram showing an example of a configuration of a system for realizing the embodiment.

FIG. 10 is an explanatory diagram showing an example of a method for obtaining a yield influence degree.

[Explanation of symbols]

20: Non-defective / defective map as a result of electrical inspection, 31
Detected defect data of defect inspection 1 32 Detected defect data of defect inspection 2 33 Detected defect data of defect inspection 3
1. Correlation processing of defect coordinates between inspections, 42 ... Result of correlation of detected defect data coordinates of defect inspections 1 to 3, 43 ...
Size determination processing for each defect, 44: Size determination result for each defect, 45: Micro defect exclusion processing, 46: Micro defect exclusion result, 51: Wafer map of net defect of defect inspection 1,
52... Wafer map of the net defect of the defect inspection 2, 53.
Wafer map of the net defect of the defect inspection 3; 55: a graph of the yield influence for each defect inspection; 56: a wafer map of the defect of the defect inspection 1; 57: a wafer map of the accumulated defects of the defect inspection 1 and the defect inspection 2; 58: wafer map of accumulated defects of defect inspection 1, defect inspection 2, and defect inspection 3,
59 ... Graph of the yield influence degree for each defect inspection, 61 ... Defect inspection device, 62 ... Electrical inspection device, 63 ... CAD system, 64 ... Local area network (LAN), 6
5: Analysis station, 650: Data collection unit, 651
.., A data analysis unit, 652, a result output unit, 653, an inspection result database, 654, a design layout database, 71, a curve of the probability of a defect becoming defective, 81, 82,
83: non-fatal small defect, 91, 92: non-fatal large defect, 93: large defect causing short circuit, 94: large defect causing disconnection, 101, 102, 103, 104 ...
Defect data, 111 to 118... Circuit pattern, 121,
122, 123: net defect; 125: chip classification result by the fatal rate calculation method.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Naofumi Iwata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Technology Research Laboratory F-term (reference) 4M106 AA01 BA14 BA20 CA50 DA15 DJ14 DJ20

Claims (9)

[Claims] 1. A method for creating data for defect analysis in an inspection of an electronic device manufactured through a plurality of manufacturing processes, comprising: a defect on a product generated in each of a plurality of predetermined manufacturing processes. Detecting defect map data including defect position information and defect size information for each manufacturing process, and a plurality of detected defect map data generated in the detecting defect map data generating process. A detected defect map for recognizing the same defect based on the defect position information therein, and creating detected defect map association data in which defect size information for each detected defect map data of the recognized defect is unified into one value. The detected defect map associating data created in the associating data creating process and the detecting defect map associating data creating process based on the defect size information. And generating a detected defect map associating divided data. The detecting defect map associating divided data created in the above described detected defect map associating divided data creating process is used for defect analysis. A method for creating data for defect analysis, characterized by providing the data as defect data. 2. The defect analysis data creating method according to claim 1, wherein, in said detected defect map association division data process, whether or not defect size information is equal to or smaller than a predetermined threshold value. And generating the data for defect analysis by dividing the detected defect map association data. 3. The defect analysis data creating method according to claim 2, wherein in the detection defect map correspondence division data process, a probability of a defect becoming defective is determined using design layout data of an electronic device. And setting a threshold based on a relationship between the obtained probability and defect size information. 4. The defect analysis data creating method according to claim 1, 2 or 3, wherein in the step of creating the detected defect map association data, a defect whose defect position information is within a predetermined error range. Defect analysis data characterized by recognizing the same defect and unifying the maximum value of the defect size information in the detected defect map data for each manufacturing process of the same defect as defect size information into one value. How to make. 5. An inspection data analysis system for an electronic device manufactured through a plurality of manufacturing processes, comprising detecting a defect on a product generated in each of a plurality of predetermined manufacturing processes, and Detected defect map data creating means for creating detected defect map data including defect position information and defect size information, based on defect position information in a plurality of detected defect map data created by the detected defect map data creating means, A detection defect map associating data creating means for recognizing the same defect and creating detected defect map associating data in which the defect size information for each detected defect map data of the recognized defect is unified into one value; The detected defect map associating data created by the detected defect map associating data creating means is divided into detected defect map pairs based on defect size information. Detection defect map associating divided data creating means for creating attached divided data; and defect analyzing means for performing defect analysis using the detected defect map associating divided data created by the detected defect map associating divided data creating means. An inspection data analysis system for an electronic device, characterized in that: 6. An inspection data analysis system for an electronic device manufactured through a plurality of manufacturing processes, wherein an electrical inspection is performed on the manufactured electronic device for each element, and whether the electronic device is a non-defective element or a defective element is determined. An electrical inspection map data creating means for creating electrical inspection map data including information indicating whether there is any information, and detecting a defect on a product generated in each of a plurality of predetermined manufacturing processes, and detecting a defect position for each manufacturing process. Detecting defect map data generating means for generating detected defect map data including information and defect size information; and detecting the same defect based on defect position information in a plurality of detected defect map data generated by the detected defect map data generating means. To generate detected defect map association data by unifying defect size information for each detected defect map data of the same recognized defect into one value. A defect map associating data creating / creating means; and a detected defect map associating divided data obtained by dividing the detected defect map associating data created by the detected defect map associating data creating means based on defect size information. A defect using the map association division data creating unit, the electrical inspection map data created by the electrical inspection map data creation unit, and the detected defect map association division data created by the detected defect map association division data creation unit. An inspection data analysis system for an electronic device, comprising: a defect analysis unit for performing an analysis. 7. The inspection data analysis system for an electronic device according to claim 5, wherein said detected defect map correspondence division data creating means is configured to determine whether defect size information is equal to or less than a predetermined threshold value. An inspection data analysis system for an electronic device, wherein the detected defect map association data is divided according to whether or not the inspection defect map is associated. 8. The inspection data analysis system for an electronic device according to claim 5, wherein a simulation is performed to determine a probability that the defect becomes defective by using the design layout data of the electronic device, and the determined probability and the defect are determined. Threshold value setting means for setting a threshold value based on the relationship with the size information; the detected defect map associating divided data creating means; An inspection data analysis system for an electronic device, wherein the detected defect map association data is divided according to whether or not the threshold value is equal to or less than a threshold value. 9. The inspection data analysis system for an electronic device according to claim 5, wherein the detected defect map association data creating means is arranged so that the defect position information falls within a predetermined error range. An electronic device characterized in that a certain defect is recognized as the same defect, and the maximum value of the defect size information in the detected defect map data for each manufacturing process of the recognized same defect is unified into one value as the defect size information. Device inspection data analysis system.