JPS59150430A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59150430A JPS59150430A JP58023700A JP2370083A JPS59150430A JP S59150430 A JPS59150430 A JP S59150430A JP 58023700 A JP58023700 A JP 58023700A JP 2370083 A JP2370083 A JP 2370083A JP S59150430 A JPS59150430 A JP S59150430A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polarizability
- amorphous
- thin film
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Glass Compositions (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は低分極性非晶質薄膜を保護膜とした低漏洩電
流高信頼性半導体デバイスに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a low leakage current, highly reliable semiconductor device using a low polarizability amorphous thin film as a protective film.
従来の技術ではモスデバイスのAl配線に接し、そのA
l配線の上部又は下部にPbO系ガラスを使用していた
。PbO系ガラスは低温で流動化し、平担化するという
利点があるがPb4+のモル分極率が1.56もあり、
これをパッシベイションに使って1<7作されたデバイ
スの特性のC−■カーブが高ゲート電圧側にシフトしだ
し、リーク特性が悪化し/ζりして使用上問題があった
。In the conventional technology, the A
PbO glass was used above or below the l wiring. PbO glass has the advantage of being fluidized and flattened at low temperatures, but the molar polarizability of Pb4+ is as high as 1.56.
Using this for passivation, the characteristic C--curve of a device fabricated with 1<7 began to shift toward the high gate voltage side, and the leakage characteristics deteriorated/ζ, causing problems in use.
本発明はこのような欠点を改良するためになされたもの
であり、その目的とするところは従来のPbO系ガラス
よυもその分極率がはるが低く、作製されたデバイスの
C−■カーブのシフトがなく、かつリーク特性も10−
12〜1O−10A程度のものが得られる非晶質薄膜を
つけた信頼性の高いデバイスを提供するにある。The present invention was made to improve these drawbacks, and its purpose is to reduce the polarizability of the conventional PbO glass, although it is much lower than that of conventional PbO glass, and to improve the C-■ curve of the fabricated device. There is no shift and the leakage characteristics are 10-
The object of the present invention is to provide a highly reliable device equipped with an amorphous thin film capable of obtaining a power of about 12 to 10-10A.
本発明はモスデバイスの一層以上のAl配線の上又は下
にモル分極率が0.007〜1.00の非晶質薄膜を接
して設けることを特徴とするデバイスである。膜のモル
分極率が0.007〜1.00に限定した理由は0.0
7以下では通常の酸化物でガラスが出来ないためであり
、i、oo以上となるとデバイスのC−■カーブが高ゲ
ート電圧側にシフトし、又リーク電流が増加してデバイ
ス特性が著るしく悪化するからである。また非晶質膜の
形成方法はスパッター、電気泳動法、蒸着、懸1だく液
浸漬法、reflow法、その他いずれの非晶質被膜形
成方法でも構わない。The present invention is a MOS device characterized in that an amorphous thin film having a molar polarizability of 0.007 to 1.00 is provided on or below one or more layers of Al wiring. The reason why the molar polarizability of the membrane is limited to 0.007 to 1.00 is 0.0
This is because if it is less than 7, glass cannot be formed with ordinary oxides, and if it is more than i, oo, the C-■ curve of the device will shift to the high gate voltage side, and the leakage current will increase, causing the device characteristics to deteriorate significantly. This is because it will get worse. The amorphous film may be formed by sputtering, electrophoresis, vapor deposition, suspended liquid immersion, reflow, or any other method for forming an amorphous film.
例えばP−channel’A1gateポリシリコン
FETの上にガラスのモル分極率が0.007〜100
の薄膜ガラスをスパッター法で約0.5μの厚さの保護
膜をつけたデバイスを作製し、丹;T特性を調べたとこ
ろそのC−■特性は正常なカーブを示し、デバイス/7
)IJ−り、…1流は、。−11A程度であり、電界効
果正孔移動度は80〜100m/V・seeを示した。For example, if the molar polarizability of the glass is 0.007 to 100 on the P-channel'A1gate polysilicon FET,
A device with a protective film of about 0.5μ thick was fabricated using a thin film of glass using a sputtering method, and the T characteristics were examined. The C-■ characteristics showed a normal curve, indicating that the device/7
)IJ-ri...1st class is... -11A, and the field effect hole mobility was 80 to 100 m/V·see.
〔発明の実施例」
第1図にそのP−channelAg gateポリシ
リコンFETのデバイス断面を示した。1はS+ウェハ
ー ([10) 、2は5i02 It@、Bはポジー
シリコン↓・4はAll、)51[は7・ガリラ社、7
ス・祝膿4膜1、八6 U *1.、lづ−5・7−・
ト、償極、 7、はS、io、2膜1−8は)、イール
ド1醸、化暎、 ニー、91はp型領域である。ガラス
膜はスパッター法により05μの厚さに堆積させた。次
にこれらのデバイスの特性を実施例を参考にしながらの
べることにする。[Embodiments of the Invention] FIG. 1 shows a device cross section of the P-channel Ag gate polysilicon FET. 1 is S+ wafer ([10), 2 is 5i02 It@, B is positive silicon↓・4 is All,) 51[is 7・Galila Inc., 7
4 membranes 1, 86 U *1. , lzu-5・7-・
7, S, io, 2 films 1-8), yield 1, oxidation, knee, 91 is the p-type region. The glass film was deposited to a thickness of 0.5 μm by sputtering. Next, the characteristics of these devices will be described with reference to examples.
(実施例1)
前記P−channelpo1gy−siデバイスの保
護膜としてB2O370mo1% GeO220mo1
%、SiO25mo1%、Mg05 rno1%の組成
のガラス被膜をスパッター法で約0.5μの厚さを堆積
させた。ガラスのモル分極率は0.45であった。まだ
poly−stのグレインの成長としてレーザーアニー
ル又はシンメルティング法を用いた。保護膜をつけたP
−channeeFETのenhancement型の
電界効果正孔移動度は907/v*secリーク電流1
0A、、C−V特性は正常であった。(Example 1) B2O370mo1% GeO220mo1 as a protective film of the P-channel polygy-si device
A glass coating having a composition of 1% SiO2, 1% Mg05mol and 1% Mg05 was deposited to a thickness of about 0.5μ by sputtering. The molar polarizability of the glass was 0.45. Laser annealing or thin melting method was used to grow poly-st grains. P with protective film
-The enhancement type field effect hole mobility of channeleeFET is 907/v*sec leakage current 1
0A, CV characteristics were normal.
(実施例2)
前記P−channelpoly−siデバイスの保護
膜としてB2O365mai1%So0210mO1%
、P2O55molチ、Zn015mo1%、Be05
mod%の組成のガラス被膜をスパッター法で0,5μ
の厚さで堆積させた。(Example 2) As a protective film of the P-channel poly-si device, B2O365mai1%So0210mO1%
, P2O55mol, Zn015mol1%, Be05
A glass film with a composition of mod% is 0.5μ by sputtering.
It was deposited to a thickness of .
このガラスのモル分極率は0.38であった。paly
−siのグレインの成長法としてはゾーンメルト法によ
った。保護膜をつけたF″ETのenhancemer
t型の電界効果正孔移動度は95cn/ v−see
’J−り電流は1O−10A、C−V特性欽正常であっ
た。The molar polarizability of this glass was 0.38. paly
The zone melt method was used to grow the -si grains. F″ET enhancer with protective film
T-type field effect hole mobility is 95cn/v-see
The J-current was 10-10A, and the C-V characteristics were normal.
(実施例3)
B203 70 mar2%、 S i0225 ma
1%、 Ba05rnolチのガラスをスパッター法で
0.5μmの厚さにデバイスの上に保護膜としてつけた
。ガラスのモル分極率は0.46であった。保護膜をっ
けたFETのenhancement型の′電界効果正
孔移動度は80d/v’sec 1 リーク電流は1
o−10A−1c−v特性は正常であった。また各実
施例のデバイスのc−■特性を第2図に於いて曲線1〜
3で示し、比較例としてPbO系ガラスの例(曲線4)
を示した。(Example 3) B203 70 mar2%, Si0225 ma
A glass containing 1% BaO5rnol was sputtered to a thickness of 0.5 μm over the device as a protective film. The molar polarizability of the glass was 0.46. The field effect hole mobility of the enhancement type FET with a protective film is 80 d/v'sec 1 The leakage current is 1
o-10A-1c-v characteristics were normal. In addition, the c-■ characteristics of the devices of each example are shown in curves 1 to 1 in Figure 2.
3, and an example of PbO glass as a comparative example (curve 4)
showed that.
第1図はMO8半導体デバイスの構造を示す断面図、第
2図は本発明によるC−■特性を示す曲線図である。
1−8t ’) xハ(10°Q、)、2−8’102
(3000X) 膜、3− poly=Si(0,7μ
)膜、4−Al膜、5・・ガラス保護膜。
(7317)代理人 弁理士 則 近 憲 佑(、ほか
1名)
第 1 図FIG. 1 is a sectional view showing the structure of an MO8 semiconductor device, and FIG. 2 is a curve diagram showing the C-■ characteristic according to the present invention. 1-8t') xha(10°Q,), 2-8'102
(3000X) membrane, 3-poly=Si(0,7μ
) film, 4-Al film, 5... glass protective film. (7317) Agent Patent attorney Noriyuki Chika (and 1 other person) Figure 1
Claims (1)
層以上の金属配線の上部又は1部に接して設けることを
特徴とする半導体デバイス。The molar polarizability is 0. (A semiconductor device characterized in that an amorphous thin film of JO 7 to 1.00 is provided in contact with the upper part or part of one or more layers of metal wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58023700A JPS59150430A (en) | 1983-02-17 | 1983-02-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58023700A JPS59150430A (en) | 1983-02-17 | 1983-02-17 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59150430A true JPS59150430A (en) | 1984-08-28 |
JPH0458690B2 JPH0458690B2 (en) | 1992-09-18 |
Family
ID=12117659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58023700A Granted JPS59150430A (en) | 1983-02-17 | 1983-02-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59150430A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014107527A (en) * | 2012-11-30 | 2014-06-09 | Ricoh Co Ltd | Field effect transistor, display element, image display device and system |
JP2015111653A (en) * | 2013-10-30 | 2015-06-18 | 株式会社リコー | Field-effect transistor, display element, image display device, and system |
JP2018056596A (en) * | 2018-01-04 | 2018-04-05 | 株式会社リコー | Field effect transistor, display element, image display device, and system |
JP2019054284A (en) * | 2018-12-12 | 2019-04-04 | 株式会社リコー | Field effect transistor, display element, image display device, and system |
-
1983
- 1983-02-17 JP JP58023700A patent/JPS59150430A/en active Granted
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014107527A (en) * | 2012-11-30 | 2014-06-09 | Ricoh Co Ltd | Field effect transistor, display element, image display device and system |
CN104823270A (en) * | 2012-11-30 | 2015-08-05 | 株式会社理光 | Field-effect transistor, display element, image display device, and system |
KR20180010340A (en) * | 2012-11-30 | 2018-01-30 | 가부시키가이샤 리코 | Field-effect transistor, display element, image display device, and system |
CN108807427A (en) * | 2012-11-30 | 2018-11-13 | 株式会社理光 | Field-effect transistor, display element, image display device and system |
US10505046B2 (en) | 2012-11-30 | 2019-12-10 | Ricoh Company, Ltd. | Field-effect transistor including a metal oxide composite protective layer, and display element, image display device, and system including the field-effect transistor |
US11876137B2 (en) | 2012-11-30 | 2024-01-16 | Ricoh Company, Ltd. | Field-effect transistor including a metal oxide composite protective layer, and display element, image display device, and system including the field-effect transistor |
JP2015111653A (en) * | 2013-10-30 | 2015-06-18 | 株式会社リコー | Field-effect transistor, display element, image display device, and system |
JP2018056596A (en) * | 2018-01-04 | 2018-04-05 | 株式会社リコー | Field effect transistor, display element, image display device, and system |
JP2019054284A (en) * | 2018-12-12 | 2019-04-04 | 株式会社リコー | Field effect transistor, display element, image display device, and system |
Also Published As
Publication number | Publication date |
---|---|
JPH0458690B2 (en) | 1992-09-18 |
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