JPS61191026A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61191026A
JPS61191026A JP3175885A JP3175885A JPS61191026A JP S61191026 A JPS61191026 A JP S61191026A JP 3175885 A JP3175885 A JP 3175885A JP 3175885 A JP3175885 A JP 3175885A JP S61191026 A JPS61191026 A JP S61191026A
Authority
JP
Japan
Prior art keywords
polysilicon
film
wiring
titanium
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3175885A
Other languages
Japanese (ja)
Inventor
Akira Ooka
大岡 章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3175885A priority Critical patent/JPS61191026A/en
Publication of JPS61191026A publication Critical patent/JPS61191026A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent precipitation of Si to Al wiring by a method wherein concerning an electrode wiring whose laminated structure is constituted of polysilicon, titanium and Al polysilicon surface layer is oxidated by aqua regina boil. CONSTITUTION:An electrode window is made to an SiO2 film 22 formed on a surface of a semiconductor substrate 21, and an electrode window, whose laminated structure is constituted of polysilicon films 27, 28, a titanium film 29 and an Al film 30, is formed. At that time, the surface of the polysilicon films 27, 28 are oxidated by aqua regina boil, after the polysilicon films 27, 28. Thereby, oxide films are formed on a surface of each grain made of polysilicon. Precipitation of polysilicon is prevented since the oxide film restricts movement of polysilicon grains.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、より詳しくは多結晶シ
リコン(ポリシリコン)表面層をアルミニウム(Al)
成長前に王水ボイルで酸化し、Al配線へのシリコン析
出を防止する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device, in which a polycrystalline silicon (polysilicon) surface layer is made of aluminum (Al).
This invention relates to a method for preventing silicon precipitation on Al wiring by oxidizing it in an aqua regia boil before growth.

〔従来の技術〕[Conventional technology]

半導体基板表面に形成された絶縁膜に電極窓を窓開けし
、この電極窓にポリシリコン膜を成長し、その上にバリ
アメタル膜を形成し、このバリアメタル上にAIt配線
を形成する技術が研究されている。・第2図の断面図を
参照すると、半導体基板21の表面には二酸化シリコン
(5iO2)膜22が、また基板21には、ベース領域
23、エミッタ領域24、コレクタ領域25、ショット
キバリアダイオード(SBD ) 26が形成されてい
る。なお同図において、27はドープされたポリシリコ
ン膜、28はドープされないポリシリコン膜、29はチ
タン(Ti)膜、30は純粋(pure)  A lt
膜、をそれぞれ示し、ドープされたポリシリコン膜27
はエミッタ拡散との関係で設けられたものである。
There is a technology in which an electrode window is opened in an insulating film formed on the surface of a semiconductor substrate, a polysilicon film is grown in the electrode window, a barrier metal film is formed on top of the polysilicon film, and an AIt wiring is formed on this barrier metal. being researched.・Referring to the cross-sectional view of FIG. 2, a silicon dioxide (5iO2) film 22 is formed on the surface of a semiconductor substrate 21, and a base region 23, an emitter region 24, a collector region 25, and a Schottky barrier diode (SBD) are formed on the substrate 21. ) 26 are formed. In the figure, 27 is a doped polysilicon film, 28 is an undoped polysilicon film, 29 is a titanium (Ti) film, and 30 is a pure Alt.
doped polysilicon film 27
is provided in relation to emitter diffusion.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第2図に示した素子に対しては、後の工程で例えば燐・
シリケート・ガラス(PSG)の膜が形成され、そのと
き450℃程度の熱が加えられる。その結果、ポリシリ
コンとAlとが反応し、Aj2配線中にシリコンがかた
まり状に析出する。このように析出したポリシリコンは
ポリシリコン花と呼称されるが、それはドープされたポ
リシリコンに比ベドープされないポリシリコンの場合に
iとより反応し易いことが確認された。
For the device shown in Figure 2, for example, phosphorus and
A film of silicate glass (PSG) is formed, and heat of about 450° C. is applied at that time. As a result, polysilicon and Al react, and silicon is precipitated in a lump shape in the Aj2 wiring. The polysilicon thus deposited is called a polysilicon flower, and it has been confirmed that undoped polysilicon reacts more easily with i than doped polysilicon.

第3図(alの平面図を参照すると、Al配線31の表
面に黒くポリシリコン花31aが現れると、それはシリ
コンであるのでAJ配線31の抵抗が増大する。そして
ポリシリコン花32bがAl配線31を完全に横切って
析出すると、通電しないことになる。
Referring to the plan view of FIG. 3 (Al), when a black polysilicon flower 31a appears on the surface of the Al wiring 31, the resistance of the AJ wiring 31 increases because it is silicon. If it is deposited completely across the area, no current will be applied.

また、表面を観察してポリシリコン花が見られない場合
でも断面を調べると、第3図(clに示されるように表
面にまでは達しないポリシリコン花32cが析出してい
ることもある。
Furthermore, even if no polysilicon flower is observed when observing the surface, if a cross section is examined, a polysilicon flower 32c that does not reach the surface may be deposited as shown in FIG. 3 (cl).

他方、チタン膜29の膜厚はSBDの順方向電圧vF値
を決める要素であると共に1とシリコンの反応を抑える
バリアメタルとしての働きを保障するよう設定しなけれ
ばならないのであるが、ポリシリコン花の析出があるた
めチタン膜の膜厚設定の自由度が小さくなる問題もある
On the other hand, the thickness of the titanium film 29 is a factor that determines the forward voltage vF value of the SBD, and must be set so as to ensure its function as a barrier metal that suppresses the reaction between 1 and silicon. There is also the problem that the degree of freedom in setting the thickness of the titanium film is reduced due to the precipitation of titanium.

〔問題点を解決するための手段〕 本発明は、上記問題点を解消した電極配線の形成方法を
提供するもので、その手段は、半導体基板表面から取り
出す多結晶シリコン膜とアルミニウム膜の積層配線を形
成する方法において、多結晶シリコン膜を形成した後に
その表面層を王水ボイルによって酸化することを特徴と
する半導体装置の製造方法によってなされる。
[Means for Solving the Problems] The present invention provides a method for forming an electrode wiring that eliminates the above problems, and the means includes a laminated wiring of a polycrystalline silicon film and an aluminum film taken out from the surface of a semiconductor substrate. The method for manufacturing a semiconductor device is characterized in that after a polycrystalline silicon film is formed, its surface layer is oxidized by aqua regia boiling.

〔作用〕[Effect]

上記したポリシリコンの王水ボイルによって、ポリシリ
コンの表面層のみでなく、内部のポリシリコンの各グレ
インの表面にも酸化膜(SiO+膜)が形成され、この
酸化膜がポリシリコングレインの運動を拘束するので、
450℃の温度が加えられポリシリコングレインが移動
し易い環境が作られても、ポリシリコングレインの動き
が制限され、ポリシリコン花の析出が防止されるのであ
る。
Due to the aqua regia boiling of the polysilicon described above, an oxide film (SiO+ film) is formed not only on the surface layer of the polysilicon but also on the surface of each grain of the polysilicon inside, and this oxide film controls the movement of the polysilicon grains. Because it restricts
Even if a temperature of 450° C. is applied to create an environment where polysilicon grains can easily move, the movement of polysilicon grains is restricted and precipitation of polysilicon flowers is prevented.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
Embodiments of the present invention will be described in detail below with reference to the drawings.

本発明の方法においては、電極部にポリシリコン膜を形
成した後に、王水ボイル(HCe :  )lNO3−
3:1.液温80±10℃)でポリシリコン表面を酸化
する。そうなると、第1図(a)の模式的断面図に示さ
れるように、王水ボイル前にポリシリコンのグレイン1
1のみが配列していた状態(同図の左に示す)から、グ
レイン相互間に・5i02膜12が同図の右に示される
ように形成された状態に変化し、ポリシリコングレイン
11の動きが抑制される。なお図において矢印は王水ボ
イルをなしたことを示す。
In the method of the present invention, after forming a polysilicon film on the electrode part, aqua regia boiled (HCe: )lNO3-
3:1. The polysilicon surface is oxidized at a liquid temperature of 80±10°C. In this case, as shown in the schematic cross-sectional view of Fig. 1(a), one grain of polysilicon is
The state in which only polysilicon grains 1 are arranged (as shown on the left in the same figure) changes to the state in which the 5i02 film 12 is formed between the grains as shown on the right in the same figure, and the movement of the polysilicon grains 11 changes. is suppressed. In the figure, the arrow indicates that aqua regia has been boiled.

第2図に示す素子の製造においては、王水ボイル後にポ
リシリコンの表面層のみのSiO2膜を除去し、しかる
後にチタン膜を形成する。かくすることにより、ポリシ
リコン膜とチタン膜とは密着性よく密着する一方で、ポ
リシリコン膜内部は第1図(a)に示される状態にあり
、ポリシリコングレインの動きが抑えられ、ポリシリコ
ン花の析出が防止される。
In manufacturing the device shown in FIG. 2, after aqua regia boiling, only the SiO2 film on the surface layer of polysilicon is removed, and then a titanium film is formed. As a result, the polysilicon film and the titanium film are in close contact with each other with good adhesion, while the inside of the polysilicon film is in the state shown in FIG. Precipitation of flowers is prevented.

本願発明者は、王水ボイルの有無と、SBDの外との関
係を求める実験を行ったので、その結果を次頁の次の表
1に示す。
The inventor of the present application conducted an experiment to determine the relationship between the presence or absence of aqua regia boil and the outside of the SBD, and the results are shown in the following Table 1 on the next page.

第2図の素子においてSBDのvF を満足させるには
、チタン膜厚70人、アロイ条件を450℃で20分、
アルゴン(Ar)圧を2011 Torrまたは25m
 Torrにすると最適であるが、いずれの条件でも王
水ボイル無しではポリシリコン花が全体に出た。他方、
王水ボイル有りの場合ポリシリコン花は全く認められな
かった。
In order to satisfy the SBD vF in the device shown in Figure 2, the titanium film thickness should be 70 mm, the alloy conditions should be set at 450°C for 20 minutes,
Argon (Ar) pressure to 2011 Torr or 25 m
Torr is optimal, but under all conditions, polysilicon flowers appeared throughout without aqua regia boiling. On the other hand,
No polysilicon flowers were observed with aqua regia boiling.

表  ■ チタン  Ar圧 アロイ  SVD Vp(mV)ポ
リシリ 王水膜厚(A) (m Torr) (’C/
分ン(10μAの時〕 コン花 ボイル707400/
30300〜3070有707450/20304〜3
120有7015400/30296〜3090無70
15450/20297〜321△無7020400/
30295〜3190無7020450/20311〜
340×無7025400/30310〜3230無7
025450/20303〜333×無807400/
30290〜3200無注:○はポリシリコン花無し、
△はポリシリコン花周辺部に有り、×はポリシリコン花
全体に有り、をそれぞれ示す。
Table ■ Titanium Ar pressure Alloy SVD Vp (mV) Polysilicon Aqua regia film thickness (A) (m Torr) ('C/
minutes (at 10μA) Konhana Boil 707400/
30300-3070 707450/20304-3
120 Yes 7015400/30296-3090 No 70
15450/20297~321△No 7020400/
30295~3190 No 7020450/20311~
340×No 7025400/30310~3230No 7
025450/20303~333×No807400/
30290-3200 No note: ○ means no polysilicon flower,
△ indicates that the polysilicon flower is present around the polysilicon flower, and × indicates that the polysilicon flower is present throughout the flower.

本発明者は、王水ボイルの有無が、SBDのV7−に与
える影響のを無について実験をなし、王水ボイルをなし
たとしてもそれがSBDのVf に与える影響はほとん
どないことを確認した。実験の結果は第1図(b)のグ
ラフ1に示され、同グラフにおいて、Δ印、X印、・印
はある素子についてそれぞれ1m^、 SOOμ^、1
0μへの場合、0印と0印は他の素子についてそれぞれ
1mA、10μAの場合の観測結果を示す。
The present inventor conducted an experiment to determine whether the presence or absence of aqua regia boil had any effect on the V7- of the SBD, and confirmed that even if aqua regia boiled, it had almost no effect on the Vf of the SBD. . The results of the experiment are shown in graph 1 in Figure 1(b), in which the Δ mark,
In the case of 0μ, the 0 mark and the 0 mark indicate the observation results for other elements when the current was 1 mA and 10 μA, respectively.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によると、ポリシリコン、チ
タン、^lの積層構造の電極配線において、ポリシリコ
ン表面層を王水ボイルによって酸化することにより、A
l配線中にシリコンが析出しなくなり、U’配線の信頼
性が向上し、バリアメタルがシリコン析出を考慮せずに
(チタン膜厚が薄すぎると、チタンのバリアメタルとし
ての特性が悪くなり、AlとSiの反応を防止できない
)、同一半導体基板に作られるSBDのvF 値やトラ
ンジスタ特性によって決定できる(自由度が増す)効果
がある。
As explained above, according to the present invention, in an electrode wiring having a laminated structure of polysilicon, titanium, and ^l, A
Silicon no longer precipitates in the l wiring, improving the reliability of the U' wiring, and the barrier metal is formed without considering silicon precipitation (if the titanium film is too thin, the characteristics of titanium as a barrier metal will deteriorate, (The reaction between Al and Si cannot be prevented), but it can be determined by the vF value and transistor characteristics of SBDs fabricated on the same semiconductor substrate (increasing the degree of freedom).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明を説明するための王水ボイルの前
と後におけるポリシリコンのグレインの配列を示す図、
同図(blはSBDのvF の実験値を示すグラフ、第
2図は電極配線を示すための半導体装置の断面図、第3
図(alと(blはAl配線中のシリコン析出を示す平
面図と断面図である。 図中、11はポリシリコングレイン、12は酸化膜(5
iOz膜)、をそれぞれ示す。 図
FIG. 1(a) is a diagram showing the arrangement of polysilicon grains before and after aqua regia boiling for explaining the present invention;
The same figure (bl is a graph showing the experimental value of vF of SBD, Figure 2 is a cross-sectional view of the semiconductor device to show the electrode wiring, Figure 3 is a graph showing the experimental value of vF of SBD,
Figures (al and (bl) are a plan view and a cross-sectional view showing silicon precipitation in Al wiring. In the figure, 11 is a polysilicon grain, 12 is an oxide film (5
iOz film), respectively. figure

Claims (1)

【特許請求の範囲】[Claims]  半導体基板表面から取り出す多結晶シリコン膜とアル
ミニウム膜の積層配線を形成する方法において、多結晶
シリコン膜を形成した後にその表面層を王水ボイルによ
って酸化することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, the method of forming a layered wiring of a polycrystalline silicon film and an aluminum film taken out from the surface of a semiconductor substrate, the method comprising: forming a polycrystalline silicon film and then oxidizing its surface layer by aqua regia boiling.
JP3175885A 1985-02-20 1985-02-20 Manufacture of semiconductor device Pending JPS61191026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3175885A JPS61191026A (en) 1985-02-20 1985-02-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3175885A JPS61191026A (en) 1985-02-20 1985-02-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61191026A true JPS61191026A (en) 1986-08-25

Family

ID=12339921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3175885A Pending JPS61191026A (en) 1985-02-20 1985-02-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61191026A (en)

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