JPS59149742A - Reactive power compensator of power system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reactive power compensator for a power system using a thyristor phase control reactor formed by connecting a reactor and a bidirectional thyristor in series.

[Technical background of the invention and its problems]

When compensating for reactive power in a power system, conventionally, a serial reactor and a bidirectional thyristor are connected in series, and a control reactor is used to make the voltage reference value follow the slow voltage fluctuations in the power system. A voltage reference value variable method (hereinafter referred to as Vref variable method) is used. This Vref o]' variable method will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows a conventional Vref OT transformation type thyristor phase control reactor circuit diagram, in which a power supply system S and a load power system are connected via a bus 1. The thyristor phase control reactor 3 and the capacitance 8, in which the anti-parallel thyristors 5 and 6 and the axle 4 are connected in series, are connected to the bus 1 (2) via circuit breakers 2 and 7, respectively. A control device 10 is provided that controls the thyristor phase control reactor 3 based on the voltage detected from the device 9.
0 is the secondary side of the voltage transformer 9 (-2 adders 11, 1
3. It is constructed by connecting a constant voltage control circuit 15, a phase control circuit 16, and a gate control circuit 17 in series.

The output of the gate control circuit 17 is connected to the gate terminals of the thyristors 5 and 6 of the thyristor phase control reactor. The output is set to the voltage reference value Vre
f, and the voltage reference value Vref is subtracted (-adder 11 (adds two). On the other hand, the bias value from the bias setting circuit 14 is added to the adder 13.

Next ('-1) Operation of the conventional variable Vref type thyristor phase control circuit shown in FIG. 1 (two will be explained below).

The voltage value of the system detected by the voltage transformer 9 is input to the adder 11 and the first-order lag circuit 12.The output voltage value of the first-order lag circuit 12 is set as the voltage reference value Vref, and this voltage reference value In order to subtract Vref (2 adder 11 (- input), the adder 13 adds the bias value of the input C bias setting circuit 14 from the adder 11. Using this added voltage deviation as input, the constant voltage The control circuit 15 operates to maintain the gravity system voltage at the voltage reference value Vref (
= Determine the required current passing through the reactor 40, and calculate the firing phase of the thyristors 5 and 60 from the phase control circuit 16 (2).Based on this calculated value (2), the firing pulse is output from the gate control circuit 17 to the thyristor 5.6. , thyristor 5, 6
is operated, and the required amount of current flows through the four reactors. In other words, the reactive power of the power system is controlled (second, therefore, the magnetic pressure of the power system is also controlled).
Two.

Thus, the first-order delay circuit 12 responds to slow voltage fluctuations in the power system and sets a variable voltage reference value Vref.
It gives

By the way, the characteristics of the above-mentioned thyristor phase control reactor will be explained using two diagrams. Taking V (unit: PU), the voltage on the vertical axis matches the voltage of the power system, and when this voltage is IPU, it has the characteristics shown by a straight line.L1
Point B1 on the line is created by the bias value from the bias setting circuit 14 in FIG.
・Adjust the 1 bias value so that It operates along a straight line L1 (-) with this point B as its center, and suppresses or increases the voltage of the power system by supplying or absorbing delayed reactive power.

Now, the voltage of the power system is slowly rising, and the first-order lag circuit 12 in FIG.
, ef l2. This is discussed in a straight line. At this time, in order to suppress overvoltage on the power system side (-1 delayed reactive power can be supplied), in terms of reactor passing current, it is a current in a range corresponding to point B2 to point X2 on straight line Lt. Here, if the voltage reference value Vref does not follow the gradual voltage rise of the power grid, even if the grid voltage becomes (1+α) PU, the characteristics of the thyristor phase control reactor will remain on the straight line L1. Therefore, the operation at that time is to operate in a straight line, centered on point A above (2).
The range is only from point A to point X above. That is, V
ref variable system: Therefore, the voltage of the power system is
If the voltage is 1'''-, the margin for suppressing overvoltage can be increased.

On the other hand, a slow voltage drop occurs on the power grid side,
Vref variable method (=Therefore, the voltage reference value is (1-α)
Suppose that PU l2 becomes. The characteristic of the thyristor phase control reactor at this time is a straight line L1, and the supply range of delayed reactive power is a straight line from point B to point Xs. Moreover, even though the voltage on the power grid side is decreasing, the bias setting circuit 144 is supplied with delayed reactive power corresponding to points B and l2! It's 1141. In other words, unnecessary delayed reactive power is supplied. In such a case (2. When the load's power system is cut off, for example, assume that the load's power system is a DC transmission system consisting of a conversion transformer and an AC/DC converter. When load shedding is performed, the canopy 8, which has a filter configuration, is connected to the bus 1 (
2 remains, so this causes an increase in the bus voltage (= becomes).And when the bus voltage rises, the thyristor phase control reactor (2 The maximum width is from point B8 to point M on the straight line.There is a problem in that the capacity of the thyristor phase control reactor cannot be utilized to the maximum extent for suppressing overvoltage.

[Purpose of the invention]

The present invention has been made in view of the above points, and its purpose is to eliminate unnecessary delayed reactive power when the slow voltage fluctuation on the power grid side becomes C: below IPU in the Vref variable system. An object of the present invention is to provide a reactive power compensator for a power system that avoids the supply of overvoltage on the power system side and is more effective against the occurrence of overvoltage on the power system side.

[Summary of the invention]

In order to achieve the above object, the present invention connects a thyristor phase control reactor formed by connecting a reactor and a bidirectional thyristor in series to a power system, and a voltage transformer for detecting the voltage of the power system, and connects the voltage transformer to the power system. The output of 1
and to control the energizing current of the thyristor phase control reactor so that the difference between the output of the voltage transformer and the output of the first-order lag circuit becomes zero.
A reactive power compensator for a power system (=) is provided with a voltage setting device and a high value selection circuit, the output of the voltage setting device and the output of the first-order lag circuit are introduced into the high value selection circuit, and the The energizing current of the thyristor phase control reactor is controlled so that the difference between the output of the high value selection circuit and the output of the voltage transformer becomes zero.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a circuit diagram of a reactive power compensator for a power system according to the present invention (2), and the same reference numerals as in FIG. A thyristor phase control reactor 3 and a capacitor 8, each having a reactor 4 connected in series to an antiparallel thyristor 5.6, are connected to the bus 1, and circuit breakers 2 and 7, respectively, The bus 1 (2) is connected to the voltage detected from the voltage transformer 9 (
A control device is provided for controlling the thyristor phase control reactor 3 based on the y. This control device is implemented by connecting two adders 11, 13, a constant voltage control circuit 15, a phase control circuit 16, and a gate control circuit 17 in series on the secondary side of the voltage transformer 9. 11 (Secondly, the output of the voltage transformer 9 that has passed through the first-order delay circuit 12 and the voltage reference value set by the voltage reference value setting device 19 are connected to the high value selection circuit 18
The other adder 13 inputs the input from the adder 11 to the bias setting circuit 14.
C: is configured so that it is added to the bias value set in . The output of the adder 13 is inputted to the phase control circuit 16 via the constant voltage control circuit 15, and the phase control circuit 16 calculates the firing phase of the thyristor 5. 5.6 and this 4': Therefore, the current flowing through the reactor 4C is controlled. Note that the reference value set by the voltage reference value setter 19 is the rated voltage of the power system (
IPU).

Next, the operation of the reactive power compensator according to the present invention will be explained.

Now, if the slow voltage fluctuation on the power system side exceeds the IPU, the output Vref of the first-order delay circuit 12 will exceed the IPU.
exceed. Therefore, the output Vref of the first-order lag circuit 12 is selected in the high value selection circuit 18, and the voltage reference value is set to a value (1+α) PU exceeding IPU, and the transition from straight line L1 to straight line L20 occurs in the characteristic diagram of FIG. In order to suppress overvoltage on the power system side (point B is the range where two-lag reactive power can be supplied)
2 and point X2 (the two functions are the same as before).

On the other hand, slow voltage fluctuations on the power grid side cause IPU
In the following case (-, the output Vref of the first-order lag circuit 12 is (l-α)PU below IPU. Therefore, in the high value selection circuit 18, the IPU set by the voltage reference setter 1 and 2 is selected. Then, in the characteristic diagram of Figure 2, there will be no transition from the straight line L1 to the straight line Lsl2, and the straight line L1 will be maintained as it is.As is clear from the characteristic diagram of Figure 2, the power system side The margin for overvoltage C2 is larger than the range from point B3 to point Xs when moving to straight line L3 from point C to point X1 on a straight line. When the voltage drops (-1), the suppressing effect against the sudden overvoltage (2) is as great as that of the conventional Vref variable method (C2).

FIG. 4 shows another embodiment of the present invention, in which the same parts as in the previous embodiment (2 are given the same reference numerals and will be explained).

The power supply system S and the power system of the load are connected via the bus 1, and this bus 1 (the second is an antiparallel syrisk 5
．． 6 (A thyristor phase control reactor 3 and a capacitor 8 to which a urea handle 4 is connected in series are connected via circuit breakers 2 and 7, respectively.
is provided with a control device 21 that controls the thyristor phase control reactor 3 based on the voltage (2) detected from the voltage transformer 9, and this control device 21 controls the secondary side (secondary side) of the voltage transformer 9. Two adders 11 and 13, a constant voltage control circuit 15, a phase control circuit 16, and a gate control circuit 17 are connected in series (one of the adders 11 (the second is the voltage that has passed through the first-order lag circuit 12). The output of the transformer 9 and the voltage reference value set by the voltage reference value setter 19 are added so as to decrease through the high value selection circuit 18, and the other adder 1
3 (2) is configured so that the output of the adder 11 is added to the bias value set by the bias setting circuit 22. ), this output is IP
If it is greater than or equal to U, the adder 13 (= gives the bias value corresponding to point B1 or point B21 in FIG. 2).

Further, if the output of the first-order lag circuit 12 is less than IPU, the bias value given to the adder 13 is O.

Next (-1) To explain its effect, if the slow voltage change in the power system is greater than or equal to I PU (2), the output of the first-order lag circuit 12 exceeds I PU. Therefore, the high value selection circuit 18 The output of times wr12 is selected,
The voltage reference value exceeds I PU (1 + α) PU (n is set, and in the characteristic diagram of Figure 2, the line L1 to the line Lt1': $
In order to suppress overvoltage on the power system side, the range in which delayed reactive power can be supplied extends from point B to point X, as in the case of the previous embodiment.

On the other hand, if the slow voltage change in the power system causes the IPU to change, the output of the first-order lag circuit 12 also becomes the IPU
If it is less than 2, the bias value given to the adder 13 (2) will be 0, so the thyristor phase control reactor 3 will be on standby at point Y in Figure 2. At the same time, unnecessary delayed reactive power is no longer supplied (overvoltage occurs), and the state in which the maximum delayed reactive power can be supplied is maintained. In terms of passing current, it can be supplied over a wide range C2 from point Y1 to point X in FIG.

In the explanation of each of the above embodiments, the value set by the voltage reference setter was set to IPU, which is the rated voltage value of the power system, but this setting value does not need to be limited to IPU, It goes without saying that strain characteristics C: can be freely selected.

〔Effect of the invention〕

According to the present invention (2), it is possible to increase the suppressing effect on overvoltage that suddenly occurs when the voltage of the power system gradually drops.Furthermore, it is possible to increase the suppressing effect on overvoltage that suddenly occurs when the voltage of the power system gradually drops. It is possible to reduce the loss of the thyristor phase control reactor.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional Vref 0T variable type thyristor phase control reactor, Fig. 2 is a characteristic diagram of the thyristor phase control reactor, and wIs diagram and Fig. 4 are circuit diagrams of different embodiments of the present invention. . S: Power system, L: Load power system 1
... bus bar, 2.7 ... circuit breaker 3 ...
Thyristor phase control reactor 8...Capacitor, °
9... Voltage transformer 10, 20.21... Control device, 11.13... Adder 12... First-order lag circuit, 14.22... Bias value setting circuit 15...
- Constant voltage control circuit, 16... Phase control circuit 17...
Gate control circuit, 18... High value selection circuit 19... Voltage reference value setter (8733) Agent: Patent attorney Yoshiaki Inomata (and 1 others)
name) Figure 1 Figure 2 0
Figure 3

Claims (1)

[Claims] (1) When connecting a thyristor phase control reactor formed by connecting a reactor and a bidirectional thyristor in series to a voltage transformer for detecting the voltage of the power system (2 degrees Celsius), the output of the voltage transformer is A second order lag circuit (second order delay circuit) is introduced, and a second order delay circuit (second order delay circuit) is introduced so that the difference between the output of the voltage transformer and the output of the first order delay circuit is equal to the second order delay circuit (second order delay circuit). In a reactive power compensator for a power system, a voltage setting device and a high value selection circuit are provided, and the output of the voltage setting device and the output of the first-order lag circuit are connected to the high value selection circuit (=hirojin), and the high value selection circuit A method for disabling an electric power system characterized by Power compensator.