JPH07160346A - Stationary reactive power compensator - Google Patents

Stationary reactive power compensator

Info

Publication number
JPH07160346A
JPH07160346A JP5310955A JP31095593A JPH07160346A JP H07160346 A JPH07160346 A JP H07160346A JP 5310955 A JP5310955 A JP 5310955A JP 31095593 A JP31095593 A JP 31095593A JP H07160346 A JPH07160346 A JP H07160346A
Authority
JP
Japan
Prior art keywords
circuit
output signal
thyristor
reactor
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5310955A
Other languages
Japanese (ja)
Other versions
JP3328039B2 (en
Inventor
Hideki Yoshitake
秀樹 吉武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31095593A priority Critical patent/JP3328039B2/en
Publication of JPH07160346A publication Critical patent/JPH07160346A/en
Application granted granted Critical
Publication of JP3328039B2 publication Critical patent/JP3328039B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30Reactive power compensation

Landscapes

  • Control Of Electrical Variables (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Abstract

PURPOSE:To improve the response, improve the control performance, and secure the high reliability of the stationary reactive power compensator. CONSTITUTION:A 1st reactor 1, a 2nd reactor 2 and a capacitor 3 is connected in serves to a three-phase distribution line or power transmission line 6 to form a Y-connection, and a thyristor circuit 4 is connected to the connection point between the 1st reactor 1 and 2nd reactor 2 to form a DELTA-connection to constitute a main circuit; when reactive power is controlled continuously from a lagging state to a leading state by controlling the ignition angle of the thyristor circuit 4, a feedback loop is constituted with an effective value of an inter- phase voltage detected by an effective value detecting circuit 11 connected to a PT 7 to enable voltage constant control even over a distorted wave voltage.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、無効電力の変動を生ず
る負荷が接続された電力系統において、サイリスタ回路
を制御することにより前記負荷の運転にともなって生ず
る無効電力の変動を補償する静止形無効電力補償装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static type system in which a thyristor circuit is controlled in a power system to which a load that causes fluctuations in reactive power is connected to compensate for fluctuations in reactive power that occur when the load is operated. The present invention relates to a reactive power compensator.

【0002】[0002]

【従来の技術】一般に無効電力が大きく変動する負荷が
接続されている電力系統において、その負荷の接続点の
電圧は、負荷に流れる無効電流に応じて変動するので、
同じ電力系統に接続されている他の電力需要家に悪影響
を与える可能性がある。このような電圧変動を抑制する
ために設置されるのが静止形無効電力補償装置である。
2. Description of the Related Art Generally, in a power system to which a load whose reactive power fluctuates greatly is connected, the voltage at the connection point of the load fluctuates according to the reactive current flowing in the load.
It may adversely affect other power consumers connected to the same grid. A static var compensator is installed to suppress such voltage fluctuations.

【0003】図6に従来の静止形無効電力補償装置の接
続図を示す。1は第1のリアクトル、2は第2のリアク
トル、3はコンデンサ、4はサイリスタ一つまたは複数
個の逆並列回路よりなる導通角が調整可能なサイリスタ
回路、5はサイリスタのゲート信号を出力するサイリス
タ駆動回路、6は静止形無効電力補償装置が接続されて
いる配電線または送電線、7は配電線または送電線6の
電圧を検出する変圧器(以下PTと称す)、8は全波整
流回路、9は配電線または送電線6の相間電圧のゼロク
ロスのタイミングを検出するタイミング検出回路、10
は演算回路である。
FIG. 6 shows a connection diagram of a conventional static var compensator. Reference numeral 1 is a first reactor, 2 is a second reactor, 3 is a capacitor, 4 is a thyristor circuit having one or a plurality of anti-parallel circuits with adjustable conduction angles, and 5 is a thyristor gate signal. Thyristor drive circuit, 6 is a distribution line or transmission line to which a static var compensator is connected, 7 is a transformer (hereinafter referred to as PT) that detects the voltage of the distribution line or transmission line 6, and 8 is full-wave rectification Reference numeral 9 denotes a circuit, 9 is a timing detection circuit for detecting the timing of zero crossing of the interphase voltage of the distribution line or the transmission line 6, and 10
Is an arithmetic circuit.

【0004】次に上記構成要素からなる静止形無効電力
補償装置の主回路動作について説明する。図6におい
て、サイリスタ回路4の停止時には主回路はリアクトル
1,2とコンデンサ3の単純な直列回路であるのでコン
デンサ3の端子電圧VC が最大となり、第1のリアクト
ル1の端子電圧VR1および第2のリアクトル2の端子電
圧VR2が最小となるので、進み無効電力は最大となる。
一方、サイリスタ駆動回路5によってサイリスタ回路4
を各相間電圧のゼロクロス点から時間進みの方向のある
制御角で導通させると、その期間だけ第2のリアクトル
2とコンデンサ3が短絡された形となり第1のリアクト
ル1の端子電圧VR1は上昇するので、コンデンサ3の供
給する進み無効電力は小さくなるとともに、第1のリア
クトル1による遅れ無効電力は増大する。また、サイリ
スタ回路4の導通によって、コンデンサ3の電荷は第2
のリアクトル2とサイリスタ回路4を通じて反転充電さ
れるが、この反転電荷は、サイリスタ回路4のオフ後、
遅相電流として配電線または送電線6に流入し、遅れ無
効電力を発生させる。サイリスタ回路4の遅れ制御角を
さらに進めれば、全体として進み無効電力は減少し、遅
れ無効電力は増大する。このように、サイリスタ回路4
を位相制御することにより進み無効電力から遅れ無効電
力まで連続的に制御できることになる。
Next, the main circuit operation of the static var compensator comprising the above components will be described. In FIG. 6, when the thyristor circuit 4 is stopped, the main circuit is a simple series circuit of the reactors 1 and 2 and the capacitor 3, so that the terminal voltage VC of the capacitor 3 becomes maximum, and the terminal voltage VR1 of the first reactor 1 and the second voltage Since the terminal voltage VR2 of the reactor 2 becomes minimum, the advanced reactive power becomes maximum.
On the other hand, the thyristor drive circuit 5 causes the thyristor circuit 4
If the control circuit is turned on from the zero cross point of each interphase voltage at a control angle with a time advance direction, the second reactor 2 and the capacitor 3 are short-circuited for that period, and the terminal voltage VR1 of the first reactor 1 rises. Therefore, the leading reactive power supplied by the capacitor 3 becomes smaller and the delayed reactive power due to the first reactor 1 increases. In addition, due to the conduction of the thyristor circuit 4, the charge of the capacitor 3 becomes the second charge.
Inverted charge is performed through the reactor 2 and the thyristor circuit 4, and this inverted charge is generated after the thyristor circuit 4 is turned off.
It flows into the distribution line or the power transmission line 6 as a lag phase current and generates delayed reactive power. If the delay control angle of the thyristor circuit 4 is further advanced, then the overall reactive power decreases and the delayed reactive power increases. In this way, the thyristor circuit 4
By controlling the phase of, it is possible to continuously control from the advanced reactive power to the delayed reactive power.

【0005】次にこのような主回路を制御することによ
る配電線または送電線の相間電圧一定制御の動作につい
て説明する。配電線または送電線6の相間電圧はPT7
により検出され全波整流回路8で相間電圧のフィードバ
ック信号に変換される。この相間電圧のフィードバック
信号と電圧指令値との誤差信号を演算回路10で処理し
てサイリスタ駆動回路5の点弧タイミング指令値を得
る。サイリスタ駆動回路5では演算回路10の点弧タイ
ミング指令値により、たとえば相間電圧が電圧指令値よ
り高い場合は相間電圧のゼロクロス点から前の方にサイ
リスタの点弧タイミングをずらして静止形無効電力補償
装置の動作点が遅れ側にシフトするように制御し、相間
電圧が下がって電圧指令値に一致するようにフィードバ
ック制御を行う。逆に相間電圧の方が低い場合はサイリ
スタの点弧タイミングを相間電圧のゼロクロス点に近づ
けて静止形無効電力補償装置の動作点が進み側にシフト
するように制御し、相間電圧が上がって電圧指令値に一
致するようにフィードバック制御を行う。
Next, the operation of constant phase-to-phase voltage control of a distribution line or a transmission line by controlling such a main circuit will be described. The interphase voltage of the distribution line or transmission line 6 is PT7.
Is detected by the full-wave rectifier circuit 8 and converted into a feedback signal of interphase voltage. The error signal between the feedback signal of the interphase voltage and the voltage command value is processed by the arithmetic circuit 10 to obtain the firing timing command value of the thyristor drive circuit 5. In the thyristor drive circuit 5, according to the ignition timing command value of the arithmetic circuit 10, for example, when the interphase voltage is higher than the voltage command value, the static var compensating is performed by shifting the ignition timing of the thyristor forward from the zero cross point of the interphase voltage. The operating point of the device is controlled so as to shift to the delay side, and the feedback control is performed so that the interphase voltage decreases and matches the voltage command value. Conversely, when the interphase voltage is lower, the ignition timing of the thyristor is brought closer to the zero crossing point of the interphase voltage, and the operating point of the static var compensator is controlled so as to shift to the advanced side. Feedback control is performed to match the command value.

【0006】以上述べたように、配電線または送電線の
相間電圧をフィードバック信号とし、電圧指令値が相間
電圧のフィードバック信号と一致するようにサイリスタ
回路4を位相制御して静止形無効電力補償装置の無効電
力を遅れから進みまで連続に制御することにより、静止
形無効電力補償装置の設置点の配電線または送電線の相
間電圧を一定に保つことができる。
As described above, the static var compensator for the static var compensator is provided by using the interphase voltage of the distribution line or the transmission line as the feedback signal, and controlling the phase of the thyristor circuit 4 so that the voltage command value matches the interphase voltage feedback signal. By continuously controlling the reactive power of the above from delay to advance, the interphase voltage of the distribution line or transmission line at the installation point of the static var compensator can be kept constant.

【0007】[0007]

【発明が解決しようとする課題】従来の静止形無効電力
補償装置は以上のような構成であり、まず第1に配電線
または送電線の相間電圧を全波整流してフィードバック
信号としているので、相間電圧が歪み波を含んでいる場
合に電圧一定制御に誤差が発生してしまう。
Since the conventional static var compensator has the above-mentioned structure, first of all, since the interphase voltage of the distribution line or the transmission line is full-wave rectified into the feedback signal, When the interphase voltage includes a distorted wave, an error occurs in the constant voltage control.

【0008】第2に従来例の制御回路は相間電圧のフィ
ードバックループしかないので、相間電圧が大きく変動
して電圧の誤差信号が大きくなった場合に大きなサイリ
スタ電流が流れサイリスタを破壊してしまう恐れがあ
る。
Secondly, since the control circuit of the conventional example has only the feedback loop of the interphase voltage, a large thyristor current may flow and destroy the thyristor when the interphase voltage fluctuates greatly and the voltage error signal becomes large. There is.

【0009】第3に従来例では電源が立上がった直後は
制御回路が振り切れている可能性が有り、その場合静止
形無効電力補償装置が進みまたは遅れ100%で立上が
る。そうすると配電線または送電線の相間電圧異常に上
昇または下降してしまう恐れが有る。
Thirdly, in the conventional example, there is a possibility that the control circuit is cut off immediately after the power source is turned on, in which case the static var compensator will be started up with 100% advance or delay. Then, there is a possibility that the interphase voltage of the distribution line or the transmission line may abnormally rise or fall.

【0010】第4に従来例では電圧フィードバック制御
を基本にしているので、相間電圧の急変に対する応答性
に限界がある。本発明は上記それぞれの問題点を解決す
るためになされたもので、応答性を改善でき、制御性能
を向上でき、さらに高信頼性を確保できる静止形無効電
力補償装置を提供することを目的とする。
Fourthly, since the conventional example is basically based on the voltage feedback control, there is a limit in the responsiveness to a sudden change in the interphase voltage. The present invention has been made to solve each of the above problems, and an object thereof is to provide a static var compensator capable of improving responsiveness, improving control performance, and ensuring high reliability. To do.

【0011】[0011]

【課題を解決するための手段】本発明は上記第1の課題
を解決するために、たとえば三相の配電線または送電線
にY結線された第1のリアクトルと第2のリアクトルと
コンデンサの直列回路と、前記第1のリアクトルと第2
のリアクトルの各相3つの接続点にΔ結線された一つま
たは複数個直列のサイリスタの逆並列回路よりなる3つ
のサイリスタ回路とから構成された主回路と、前記配電
線または送電線に取り付けられたPTと、前記PTの出
力の実効値を検出する実効値検出回路と、前記PTの出
力を入力とし前記配電線または送電線の相間電圧のゼロ
クロスのタイミングを検出するタイミング検出回路と、
前記実効値検出回路の出力信号とあらかじめ設定された
電圧指令値との誤差信号を入力とする第1の演算回路
と、前記第1の演算回路の出力信号と前記タイミング検
出回路の出力を入力とし前記サイリスタ回路の導通角を
制御するゲート信号を出力するサイリスタ駆動回路とで
構成される。
In order to solve the above first problem, the present invention provides a series connection of a first reactor, a second reactor and a capacitor, which are Y-connected to a three-phase distribution line or a transmission line, for example. A circuit, the first reactor and the second
Attached to the distribution line or the transmission line, and a main circuit composed of three thyristor circuits consisting of one or more series-connected thyristor anti-parallel circuits, which are Δ-connected to three connection points of each phase of the reactor. PT, an effective value detection circuit that detects the effective value of the output of the PT, and a timing detection circuit that receives the output of the PT and detects the zero-cross timing of the interphase voltage of the distribution line or the transmission line,
A first arithmetic circuit that receives an error signal between the output signal of the effective value detection circuit and a preset voltage command value, and an output signal of the first arithmetic circuit and an output of the timing detection circuit And a thyristor drive circuit that outputs a gate signal for controlling the conduction angle of the thyristor circuit.

【0012】本発明は上記第2の課題を解決するため
に、たとえば三相の配電線または送電線にY結線された
第1のリアクトルと第2のリアクトルとコンデンサの直
列回路と、前記第1のリアクトルと第2のリアクトルの
各相3つの接続点にΔ結線された一つまたは複数個直列
のサイリスタの逆並列回路よりなる3つのサイリスタ回
路とから構成された主回路と、前記配電線または送電線
に取り付けられたPTと、前記PTの出力の実効値を検
出する実効値検出回路と、前記PTの出力を入力とし前
記配電線または送電線の相間電圧のゼロクロスのタイミ
ングを検出するタイミング検出回路と、前記第1のリア
クトルと前記配電線または送電線の間に設置され前記主
回路の入力電流を検出するCTと、前記PTと前記CT
の出力信号を入力とし前記主回路に流れ込む無効電力を
検出する無効電力検出回路と、前記電圧実効値検出回路
の出力信号とあらかじめ設定された電圧指令値との誤差
信号を入力とする第1の演算回路と、前記第1の演算回
路の出力信号を入力とするリミッタと、前記リミッタの
出力と前記無効電力検出回路の出力信号との誤差信号を
入力とする第2の演算回路と、前記第2の演算回路の出
力信号と前記タイミング検出回路の出力信号を入力とし
前記サイリスタ回路の導通角を制御するゲート信号を出
力するサイリスタ駆動回路とで構成される。
In order to solve the above-mentioned second problem, the present invention provides, for example, a series circuit of a first reactor, a second reactor and a capacitor, which are Y-connected to a three-phase distribution line or a power transmission line, and the first circuit. And a main circuit composed of three thyristor circuits each consisting of an anti-parallel circuit of one or more series thyristors Δ-connected to three connection points of each phase of the second reactor, and the distribution line or A PT attached to the power transmission line, an effective value detection circuit for detecting the effective value of the output of the PT, and a timing detection for detecting the zero-cross timing of the interphase voltage of the distribution line or the transmission line with the output of the PT as an input. A circuit, a CT installed between the first reactor and the distribution line or the power transmission line for detecting an input current of the main circuit, the PT and the CT
Of the reactive power detection circuit for detecting the reactive power flowing into the main circuit by inputting the output signal of the above, and the error signal between the output signal of the voltage effective value detection circuit and the preset voltage command value as the input. An arithmetic circuit; a limiter that receives the output signal of the first arithmetic circuit; a second arithmetic circuit that receives the error signal between the output of the limiter and the output signal of the reactive power detection circuit; And a thyristor drive circuit which receives the output signal of the arithmetic circuit and the output signal of the timing detection circuit and outputs a gate signal for controlling the conduction angle of the thyristor circuit.

【0013】また、本発明は上記第2の課題を解決する
ための別の方法として、たとえば三相の配電線または送
電線にY結線された第1のリアクトルと第2のリアクト
ルとコンデンサの直列回路と、前記第1のリアクトルと
第2のリアクトルの各相3つの接続点にΔ結線された一
つまたは複数個直列のサイリスタの逆並列回路よりなる
3つのサイリスタ回路とから構成された主回路と、前記
配電線または送電線に取り付けられたPTと、前記PT
の出力実効値を検出する実効値検出回路と、前記PTの
出力を入力とし前記配電線または送電線の相間電圧のゼ
ロクロスのタイミングを検出するタイミング検出回路
と、前記サイリスタ回路に直列に取り付けられたCT
と、前記CTの出力信号を入力とし前記サイリクスタ回
路に流れる電流値を検出するサイリスタ電流検出回路
と、前記電圧実効値検出回路の出力信号とあらかじめ設
定された電圧指令値との誤差信号を入力とする第1の演
算回路と、前記第1の演算回路の出力信号を入力とする
リミッタと、前記リミッタの出力信号と前記サイリスタ
電流検出回路の出力信号との誤差信号を入力とする第2
の演算回路と、前記第2の演算回路の出力信号と前記タ
イミング検出回路の出力信号を入力とし前記サイリスタ
回路の導通角を制御するゲート信号を出力するサイリス
タ駆動回路とで構成される。
As another method for solving the above-mentioned second problem, the present invention provides, for example, a series connection of a first reactor, a second reactor and a capacitor Y-connected to a three-phase distribution line or a transmission line. A main circuit composed of a circuit and three thyristor circuits consisting of an anti-parallel circuit of one or a plurality of series thyristors Δ-connected to three connection points of each phase of the first reactor and the second reactor A PT attached to the distribution line or the power transmission line;
An effective value detection circuit for detecting an output effective value of the PT, a timing detection circuit for detecting the zero-cross timing of the interphase voltage of the distribution line or the transmission line using the output of the PT as an input, and the thyristor circuit. CT
A thyristor current detection circuit that receives the CT output signal as an input and detects the current value flowing in the thyristor circuit; and an error signal between the output signal of the voltage effective value detection circuit and a preset voltage command value as an input. A first arithmetic circuit, a limiter that receives the output signal of the first arithmetic circuit, and a second signal that receives the error signal between the output signal of the limiter and the output signal of the thyristor current detection circuit.
And the thyristor drive circuit which receives the output signal of the second arithmetic circuit and the output signal of the timing detection circuit and outputs a gate signal for controlling the conduction angle of the thyristor circuit.

【0014】本発明は上記第3の課題を解決するため
に、たとえば三相の配電線または送電線にY結線された
第1のリアクトルと第2のリアクトルとコンデンサの直
列回路と、前記第1のリアクトルと第2のリアクトルの
各相3つの接続点にΔ結線された一つまたは複数個直列
のサイリスタの逆並列回路よりなる3つのサイリスタ回
路とから構成された主回路と、前記配電線または送電線
に取り付けられたPTと、前記PTの出力の実効値を検
出する実効値検出回路と、前記PTの出力を入力とし前
記配電線または送電線の相間電圧のゼロクロスのタイミ
ングを検出するタイミング検出回路と、前記第1のリア
クトルと前記配電線または送電線の間に設置され前記主
回路の入力電流を検出するCTと、前記PTと前記CT
の出力信号を入力とし前記主回路に流れ込む無効電力を
検出する無効電力検出回路と、前記電圧実効値検出回路
の出力信号とあらかじめ設定された電圧指令値との誤差
信号を入力とする第1の演算回路と、前記第1の演算回
路の出力信号と前記無効電力検出回路の出力信号との誤
差信号を入力とする第2の演算回路と、前記第2の演算
回路の出力信号と前記タイミング検出回路の出力信号を
入力とし前記サイリスタ回路の導通角を制御するゲート
信号を出力するサイリスタ駆動回路と、電源立上がり検
出回路と、前記電源立上がり検出回路の出力信号を入力
とし電源立上がり後ある一定時間を一回だけカウントす
るタイマと、前記タイマの出力と前記サイリスタ駆動回
路の入力信号と前記無効電力検出回路の出力信号とを入
力とし前記タイマのタイムアップ後の通常運転状態で無
効電力が0Var近傍のときの前記サイリスタ駆動回路
の入力信号を記憶し電源が切れた状態でも記憶内容を保
持する記憶回路とで構成され、前記第2の演算回路は、
前記第1の演算回路の出力信号と前記無効電力検出回路
の出力信号との前記誤差信号以外にさらに前記記憶装置
の出力信号と前記タイマの出力信号とが入力されて、電
源立上がり後前記タイマのタイムアップまでは前記記憶
回路の記憶内容である無効電力が0Var近傍となる出
力信号を出力し、前記タイマのタイムアップ後は通常の
演算処理を行うように構成し、前記サイリスタ駆動回路
により前記サイリスタ回路の導通角を制御し、前記主回
路に流れる無効電力を連続に制御して前記配電線または
送電線の電圧一定制御を行うようにしたものである。
In order to solve the above-mentioned third problem, the present invention provides, for example, a series circuit of a first reactor, a second reactor and a capacitor, which are Y-connected to a three-phase distribution line or a transmission line, and the first circuit. And a main circuit composed of three thyristor circuits each consisting of an anti-parallel circuit of one or more series thyristors Δ-connected to three connection points of each phase of the second reactor, and the distribution line or A PT attached to the power transmission line, an effective value detection circuit for detecting the effective value of the output of the PT, and a timing detection for detecting the zero-cross timing of the interphase voltage of the distribution line or the transmission line with the output of the PT as an input. A circuit, a CT installed between the first reactor and the distribution line or the power transmission line for detecting an input current of the main circuit, the PT and the CT
Of the reactive power detection circuit for detecting the reactive power flowing into the main circuit by inputting the output signal of the above, and the error signal between the output signal of the voltage effective value detection circuit and the preset voltage command value as the input. An arithmetic circuit, a second arithmetic circuit which receives an error signal between an output signal of the first arithmetic circuit and an output signal of the reactive power detection circuit, an output signal of the second arithmetic circuit and the timing detection A thyristor drive circuit that receives a circuit output signal as an input and outputs a gate signal that controls the conduction angle of the thyristor circuit, a power supply rise detection circuit, and an output signal of the power supply rise detection circuit as an input, and a certain time after the power supply rises. A timer that counts only once, the timer that receives the output of the timer, the input signal of the thyristor drive circuit, and the output signal of the reactive power detection circuit as input A second arithmetic circuit configured to store an input signal of the thyristor drive circuit when the reactive power is near 0 Var in a normal operation state after time-up and to retain the stored content even when the power is off. Is
In addition to the error signal between the output signal of the first arithmetic circuit and the output signal of the reactive power detection circuit, the output signal of the storage device and the output signal of the timer are further input, and after the power is turned on, the timer The thyristor drive circuit is configured to output an output signal in which the reactive power stored in the storage circuit is close to 0 Var until the time is up, and to perform normal arithmetic processing after the timer is up. The conduction angle of the circuit is controlled, and the reactive power flowing in the main circuit is continuously controlled to perform constant voltage control of the distribution line or the transmission line.

【0015】本発明は上記第4の課題を解決するため
に、たとえば三相の配電線または送電線にY結線された
第1のリアクトルと第2のリアクトルとコンデンサの直
列回路と、前記第1のリアクトルと第2のリアクトルの
各相3つの接続点にΔ結線された一つまたは複数個直列
のサイリスタの逆並列回路よりなる3つのサイリスタ回
路とから構成された主回路と、前記配電線または送電線
に取り付けられたPTと、前記PTの出力の実効値を検
出する実効値検出回路と、前記PTの出力を入力とし前
記配電線または送電線の相間電圧のゼロクロスのタイミ
ングを検出するタイミング検出回路と、前記第1のリア
クトルと前記配電線または送電線の間に設置され前記主
回路の入力電流を検出する第1のCTと、前記PTと前
記第1のCTの出力信号を入力とし前記主回路に流れ込
む無効電力を検出する無効電力検出回路と、前記配電線
または送電線に前記CTよりも負荷側に取り付けられた
第2のCTと、前記PTの出力信号と前記第2のCTの
出力信号を入力とし前記配電線または送電線の有効電力
の変化分を検出する有効電力変化分検出回路と、前記P
Tの出力信号と前記第2のCTの出力信号を入力とし前
記配電線または送電線の無効電力の変化分を検出する無
効電力変化分検出回路と、現地点までの前記配電線また
は送電線の線路定数を記憶する線路定数記憶回路と、前
記有効電力変化分検出回路と前記無効電力変化分検出回
路と前記線路定数記憶回路とを入力とする第3の演算回
路と、前記電圧実効値検出回路の出力信号とあらかじめ
設定された電圧指令値との誤差信号を入力とする第1の
演算回路と、前記第3の演算回路の出力信号と前記第1
の演算回路の出力信号を入力とする加算回路と、前記加
算回路の出力信号と前記無効電力検出回路の出力信号と
の誤差信号を入力とする第2の演算回路と、前記第2の
演算回路の出力信号と前記タイミング検出回路の出力信
号を入力とし前記サイリスタ回路の導通角を制御するゲ
ート信号を出力するサイリスタ駆動回路とで構成され
る。
In order to solve the above-mentioned fourth problem, the present invention provides, for example, a series circuit of a first reactor, a second reactor and a capacitor, which are Y-connected to a three-phase distribution line or a transmission line, and the first circuit. And a main circuit composed of three thyristor circuits each consisting of an anti-parallel circuit of one or more series thyristors Δ-connected to three connection points of each phase of the second reactor, and the distribution line or A PT attached to the power transmission line, an effective value detection circuit for detecting the effective value of the output of the PT, and a timing detection for detecting the zero-cross timing of the interphase voltage of the distribution line or the transmission line with the output of the PT as an input. A circuit, a first CT installed between the first reactor and the distribution line or the transmission line to detect an input current of the main circuit, and outputs of the PT and the first CT Signal as an input, a reactive power detection circuit for detecting reactive power flowing into the main circuit, a second CT attached to the distribution line or the transmission line on the load side of the CT, an output signal of the PT, and the An active power change detecting circuit which receives an output signal of the second CT and detects a change in active power of the distribution line or the transmission line;
A reactive power change amount detection circuit that receives the output signal of T and the output signal of the second CT and detects the change amount of the reactive power of the distribution line or the transmission line, and the distribution line or the transmission line of the distribution line to the local point. A line constant storage circuit that stores a line constant, a third arithmetic circuit that receives the active power change detection circuit, the reactive power change detection circuit, and the line constant storage circuit, and the voltage effective value detection circuit. Of the first arithmetic circuit that receives the error signal between the output signal of the second arithmetic circuit and the preset voltage command value, the output signal of the third arithmetic circuit, and the first arithmetic circuit.
An adder circuit that receives the output signal of the calculator circuit as an input; a second calculator circuit that receives the error signal between the output signal of the adder circuit and the output signal of the reactive power detection circuit; and the second calculator circuit. Input signal and the output signal of the timing detection circuit, and outputs a gate signal for controlling the conduction angle of the thyristor circuit.

【0016】[0016]

【作用】本発明は上記した構成により、以下の作用が有
る。第1は配電線または送電線の電圧一定制御が相間電
圧の歪みに関わらず正確に行える。第2にサイリスタ電
流あるいは無効電力のフィードバックループを設け、主
回路の電流に上限値を設定することでサイリスタの破壊
を防止することができる。第3に停電から復電時に0V
arの運転点から静止形無効電力補償装置を起動し、過
渡的な異常電圧を防ぐことができる。第4に配電線また
は送電線の電圧急変時にその電圧急変を抑える無効電力
を発生させて高速に電圧変動を補正することができる。
The present invention has the following functions due to the above-mentioned constitution. First, the voltage constant control of the distribution line or the transmission line can be accurately performed regardless of the distortion of the interphase voltage. Secondly, by providing a feedback loop for the thyristor current or reactive power and setting the upper limit of the current of the main circuit, it is possible to prevent the thyristor from being destroyed. Third, 0V when power is restored after power failure
The static var compensator can be activated from the operating point of ar to prevent transient abnormal voltage. Fourthly, when the voltage of the distribution line or the power transmission line suddenly changes, reactive power that suppresses the sudden voltage change can be generated to quickly correct the voltage variation.

【0017】[0017]

【実施例】以下、本発明の一実施例について図面に基づ
いて説明する。図1は本発明による静止形無効電力補償
装置の第1の実施例の構成を示す接続図である。1は第
1のリアクトル、2は第2のリアクトル、3はコンデン
サであり、それらが直列に接続された直列回路はY形に
結線されて三相の配電線または送電線6に接続されてお
り、第1のリアクトルと第2のリアクトルの接続点にΔ
形に接続された3つのサイリスタ回路4とともに静止形
無効電力補償装置の主回路を構成している。7は配電線
または送電線6の相間電圧を検出する変圧器(以下PT
と称す)、11はPT7出力を入力とし実効値出力を得
る実効値検出回路である。10は電圧指令値と実効値検
出回路の実効値出力との誤差信号を入力としサイリスタ
駆動の指令信号を出力する演算回路、5はサイリスタ駆
動の指令信号を入力とし、9のタイミング検出回路で検
出した各相間電圧のゼロクロス点を基準にしてサイリス
タ回路4の点弧信号を出力するサイリスタ駆動回路であ
る。サイリスタ駆動回路5により、静止形無効電力補償
装置の動作点を遅れ側に移動するときは各相間電圧のゼ
ロクロス点を起点として時間的に前の方にサイリスタ回
路4の点弧信号をシフトし、進み側に移動するときは相
間電圧のゼロクロス点の方に戻す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a connection diagram showing a configuration of a first embodiment of a static var compensator according to the present invention. Reference numeral 1 is a first reactor, 2 is a second reactor, 3 is a capacitor, and a series circuit in which they are connected in series is connected in a Y shape and connected to a three-phase distribution line or a transmission line 6. , Δ at the connection point of the first reactor and the second reactor
Together with the three thyristor circuits 4 connected in series, they constitute the main circuit of the static var compensator. 7 is a transformer (hereinafter PT) for detecting the interphase voltage of the distribution line or the transmission line 6.
, 11 is an effective value detection circuit that receives the PT7 output as an input and obtains an effective value output. 10 is an arithmetic circuit for inputting an error signal between the voltage command value and the effective value output of the effective value detection circuit and outputting a command signal for thyristor drive. 5 is an input circuit for the command signal for thyristor drive, and is detected by the timing detection circuit 9 The thyristor drive circuit outputs an ignition signal of the thyristor circuit 4 with reference to the zero-cross point of the interphase voltage. When the operating point of the static var compensator is moved to the delay side by the thyristor drive circuit 5, the ignition signal of the thyristor circuit 4 is shifted forward with respect to the zero cross point of the interphase voltage as a starting point. When moving to the lead side, return to the zero-cross point of the interphase voltage.

【0018】ところで、変電所または発電所から静止形
無効電力補償装置の設置点までの間には長い配電線また
は送電線6があり、インダクタンス分が存在する。した
がって静止形無効電力補償装置が進み側で動作すると設
置点の電圧は上昇し、逆に遅れ側で動作すると設置点の
電圧は下降する。
By the way, there is a long distribution line or transmission line 6 between the substation or power plant and the installation point of the static var compensator, and there is an inductance component. Therefore, when the static var compensator operates on the lead side, the voltage at the installation point rises, and conversely, when it operates on the delay side, the voltage at the installation point drops.

【0019】そこで、電圧指令値と配電線または送電線
の相間電圧のフィードバック値との誤差信号がゼロにな
るように静止形無効電力補償装置の動作点を制御すれ
ば、設置点の配電線または送電線の相間電圧の一定制御
が可能となる。
Therefore, if the operating point of the static var compensator is controlled so that the error signal between the voltage command value and the feedback value of the interphase voltage of the distribution line or the transmission line becomes zero, the distribution line at the installation point or It is possible to control the phase-to-phase voltage of the transmission line constantly.

【0020】ここで、従来はフィードバック電圧の検出
を全波整流で行っていたが、配電線または送電線の相間
電圧に歪み波が重畳されている場合は電圧一定制御に誤
差が発生していた。しかし、本実施例では実効値電圧を
フィードバックすることにより波形歪みによる誤差を低
減することができた。
Conventionally, the detection of the feedback voltage has been performed by full-wave rectification, but if a distorted wave is superimposed on the interphase voltage of the distribution line or the transmission line, an error occurs in the constant voltage control. . However, in this embodiment, the error due to the waveform distortion could be reduced by feeding back the effective voltage.

【0021】なお、本実施例では信号処理を電子回路で
行った例をブロック図で提示したがフィードバック制御
の信号処理をマイクロコンピュータのソフトウェア処理
で行っても実現できる。
In the present embodiment, the example in which the signal processing is performed by the electronic circuit is presented in the block diagram, but the signal processing of the feedback control can be realized by the software processing of the microcomputer.

【0022】次に本発明の静止形無効電力補償装置の第
2の実施例について図2に基づいて説明する。主回路に
ついては第1の実施例と同様であるので説明は省略す
る。ただし、静止形無効電力補償装置の入力電流検出用
に変流器(以下CTと称す)16を静止形無効電力補償
装置と配電線または送電線6の接続点に設置する。この
CTの出力信号とPT7の出力信号より無効電力検出回
路15で静止形無効電力補償装置の無効電力を検出す
る。一方、電圧指令値と配電線または送電線6の相間電
圧のフィードバック値との誤差信号を第1の演算回路1
3に入力して静止形無効電力補償装置の無効電力指令値
を得る。この無効電力指令値をリミッタ14を通して上
下限値を設定し、無効電力検出回路15からの無効電力
フィードバック信号と比較してその誤差信号を第2の演
算回路12に入力し、その出力信号でサイリスタ駆動回
路5を介してサイリスタ回路4の点弧角の制御を行う。
無効電力指令値にはリミッタ14で上下限値を設定され
ているので結果的には静止形無効電力補償装置の入力電
流やサイリスタ電流も上下限値が設定でき、主回路構成
部品の過電流を防止できる。電圧一定制御の機能につい
ては無効電力フィードバックループの外側に電圧フィー
ドバックループが有るので、第1の実施例と同じ動作原
理で電圧一定制御が実現できる。
Next, a second embodiment of the static var compensator of the present invention will be described with reference to FIG. The main circuit is the same as that of the first embodiment, so its explanation is omitted. However, a current transformer (hereinafter referred to as CT) 16 for detecting the input current of the static var compensator is installed at the connection point between the static var compensator and the distribution line or the transmission line 6. The reactive power detection circuit 15 detects the reactive power of the static var compensator based on the CT output signal and the PT7 output signal. On the other hand, the error signal between the voltage command value and the feedback value of the interphase voltage of the distribution line or the transmission line 6 is used as the first arithmetic circuit 1
3 is input to obtain the reactive power command value of the static var compensator. The upper and lower limit values of this reactive power command value are set through the limiter 14, and the reactive signal is compared with the reactive power feedback signal from the reactive power detection circuit 15, and its error signal is input to the second arithmetic circuit 12, and its output signal is used as a thyristor. The firing angle of the thyristor circuit 4 is controlled via the drive circuit 5.
Since the upper and lower limits are set to the reactive power command value by the limiter 14, the upper and lower limits of the input current and thyristor current of the static var compensator can be set as a result, and the overcurrent of the main circuit components can be reduced. It can be prevented. Regarding the function of the constant voltage control, since the voltage feedback loop is provided outside the reactive power feedback loop, the constant voltage control can be realized by the same operation principle as that of the first embodiment.

【0023】なお、本実施例では信号処理を電子回路で
行った例をブロック図で提示したが、フィードバック制
御の信号処理をマイクロコンピュータのソフトウェア処
理で行っても実現できる。
In the present embodiment, an example in which the signal processing is performed by an electronic circuit is presented in a block diagram, but the signal processing of the feedback control can also be realized by software processing of a microcomputer.

【0024】次に本発明の静止形無効電力補償装置の第
3の実施例について図3に基づいて説明する。これは第
2の実施例とほぼ同じ構成であり、相違点はCT17の
設置箇所をサイリスタ回路4に直列に設置し、このCT
17とサイリスタ電流検出回路18でサイリスタ電流を
検出し、サイリスタ電流のフィードバック値とする。一
方、電圧指令値と配電線または送電線6の相間電圧のフ
ィードバック値との誤差信号を第1の演算回路13に入
力して静止形無効電力補償装置のサイリスタ電流指令値
を得る。このサイリスタ電流指令値をリミッタ14を通
して上下限値を設定し、サイリスタ電流検出回路18か
らのサイリスタ電流フィードバック信号と比較した誤差
信号を第2の演算回路12に入力し、その出力信号でサ
イリスタ駆動回路5を介してサイリスタ回路4の点弧角
の制御を行う。サイリスタ指令値にはリミッタ14で上
下限値を設定されているので結果的には静止形無効電力
補償装置のサイリスタ電流の上下限値が設定でき、間接
的には主回路構成部品の過電流も防止できる。電圧一定
制御の機能についてはサイリスタ電流フィードバックル
ープの外側に電圧フィードバックループが有るので、第
1の実施例と同じ動作原理で電圧一定制御が実現でき
る。
Next, a third embodiment of the static var compensator of the present invention will be described with reference to FIG. This is almost the same configuration as the second embodiment, and the difference is that the installation location of CT17 is installed in series with the thyristor circuit 4, and this CT
The thyristor current is detected by the thyristor current detection circuit 17 and the thyristor current detection circuit 18 and used as a feedback value of the thyristor current. On the other hand, the error signal between the voltage command value and the feedback value of the interphase voltage of the distribution line or the transmission line 6 is input to the first arithmetic circuit 13 to obtain the thyristor current command value of the static var compensator. The upper and lower limit values of this thyristor current command value are set through the limiter 14, and the error signal compared with the thyristor current feedback signal from the thyristor current detection circuit 18 is input to the second arithmetic circuit 12, and the output signal thereof is used as the thyristor drive circuit. The firing angle of the thyristor circuit 4 is controlled via 5. Since the limiter 14 sets the upper and lower limit values to the thyristor command value, as a result, the upper and lower limit values of the thyristor current of the static var compensator can be set, and indirectly the overcurrent of the main circuit component parts can be set. It can be prevented. Regarding the function of the constant voltage control, since the voltage feedback loop is provided outside the thyristor current feedback loop, the constant voltage control can be realized by the same operation principle as that of the first embodiment.

【0025】なお、本実施例では信号処理を電子回路て
行った例をブロック図で提示したが、フィードバック制
御の信号処理をマイクロコンピュータのソフトウェア処
理で行っても実現できる。
In the present embodiment, the example in which the signal processing is performed by the electronic circuit is presented in the block diagram, but the signal processing of the feedback control can be realized by the software processing of the microcomputer.

【0026】次に本発明の静止形無効電力補償装置の第
4の実施例について図4に基づいて説明する。これは第
2の実施例とほぼ同じ構成であり、相違点は電源の立ち
上がり検出回路21と、電源立ち上がり後からある時間
を計時するタイマ20と、無効電力検出回路15の出力
信号、タイマ20の出力信号、第2の演算回路12の出
力信号を入力とし第2の演算回路に出力信号を送る記憶
回路19とが新構成要素としてあることである。タイマ
20は電源立ち上がりからある時間経過したか否かを判
断するものである。すなわち静止形無効電力補償装置の
制御回路が電源立ち上がり直後の過渡状態にあるのか、
定常状態にあるのか判断し、定常状態であるときに記憶
回路19は無効電力が0Var時のサイリスタ駆動回路
5への指令信号レベルを記憶しておく。記憶回路19は
不揮発性メモリを採用するかバッテリバックアップを行
って電源がOFF状態でも記憶内容が失われないように
する。そして電源復電直後の静止形無効電力補償装置の
制御回路が過渡状態にあるときは記憶回路19にあらか
じめ記憶している静止形無効電力補償装置の運転点が0
Varとなるようなサイリスタ駆動回路への指令値を第
2の演算回路12を通して出力し、静止形無効電力補償
装置が振り切れずに0Var運転をするようにする。そ
の後静止形無効電力補償装置の制御回路が定常状態にな
ったら通常のフィードバック制御に切り替える。定常状
態での無効電力フィードバックループおよび電圧フィー
ドバックループについては第1、第2の実施例の説明と
全く同じなので省略する。
Next, a fourth embodiment of the static var compensator of the present invention will be described with reference to FIG. This is almost the same configuration as that of the second embodiment. The difference is that the power supply rise detection circuit 21, the timer 20 that measures a certain time after the power supply rises, the output signal of the reactive power detection circuit 15, and the timer 20. The storage circuit 19 that receives the output signal and the output signal of the second arithmetic circuit 12 as an input and sends the output signal to the second arithmetic circuit is a new component. The timer 20 determines whether or not a certain time has passed since the power was turned on. In other words, is the control circuit of the static var compensator in the transient state immediately after the power is turned on?
When it is in the steady state, the storage circuit 19 stores the command signal level to the thyristor drive circuit 5 when the reactive power is 0 Var. The storage circuit 19 uses a non-volatile memory or performs battery backup so that the stored contents are not lost even when the power is off. When the control circuit of the static var compensator immediately after the power is restored is in a transient state, the operating point of the static var compensator previously stored in the memory circuit 19 is 0.
A command value to the thyristor drive circuit that results in Var is output through the second arithmetic circuit 12 so that the static var compensator performs 0Var operation without swinging. After that, when the control circuit of the static var compensator is in a steady state, it is switched to normal feedback control. Since the reactive power feedback loop and the voltage feedback loop in the steady state are exactly the same as those described in the first and second embodiments, the description thereof will be omitted.

【0027】なお、本実施例では信号処理を電子回路で
行った場合を想定してブロック図で提示したが、各制御
の信号処理をマイクロコンピュータのソフトウェア処理
で行っても実現できる。
Although the present embodiment is shown in the block diagram on the assumption that the signal processing is performed by the electronic circuit, the signal processing for each control can be realized by the software processing of the microcomputer.

【0028】次に本発明の静止形無効電力補償装置の第
5の実施例について図5に基づいて説明する。これは第
2の実施例とほぼ同じ構成であり、相違点は配電線また
は送電線電源の負荷側に設置された第2のCT22と、
負荷の有効電力と無効電力の変化分をそれぞれ検出する
有効電力変化分検出回路23と無効電力変化分検出回路
24と、線路定数記憶回路25と、第3の演算回路26
と、加算回路27を追加したことである。第2のCT2
2とPT7の出力から有効電力変化分検出回路23と無
効電力変化分検出回路24とで検出された有効電力と無
効電力の変化分をそれぞれΔP,ΔQとし配電線または
送電線6の抵抗分とインダクタンス分をそれぞれR,L
とすると、静止形無効電力補償装置の設置点の相間電圧
の変動を抑えるための静止形無効電力補償装置の無効電
力Qsは式(1)で与えられる。
Next, a fifth embodiment of the static var compensator of the present invention will be described with reference to FIG. This is almost the same configuration as the second embodiment, the difference is that the second CT22 installed on the load side of the distribution line or transmission line power supply,
Active power change detection circuit 23, reactive power change detection circuit 24, line constant storage circuit 25, and third arithmetic circuit 26, which detect changes in active power and reactive power of the load, respectively.
And the addition circuit 27 is added. Second CT2
2 and ΔQ are the changes in the active power and the reactive power detected by the active power change detection circuit 23 and the reactive power change detection circuit 24 from the outputs of PT7 and PT7, respectively, and the resistance of the distribution line or the transmission line 6 and Inductance components are R and L respectively
Then, the reactive power Qs of the static var compensator for suppressing the fluctuation of the interphase voltage at the installation point of the static var compensator is given by the equation (1).

【0029】 Qs=ΔQ+ΔP×(R/L) (1) したがって、変電所または発電所から現地点までの配電
線または送電線6の抵抗分とインダクタンス分を線路定
数記憶回路25に記憶して置き、第3の演算回路26で
式(1)の演算を行い、負荷の急変による静止形無効電
力補償装置の設置点の相間電圧の変動を補償する無効電
力の指令値を演算し、加算回路27で第1の演算回路1
3からの無効電力指令値とQs との加算を行うことによ
り、負荷の急変にも対応できる無効電力指令信号を得
る。このように本実施例によると負荷の急変を検知し、
配電線または送電線の定数を考慮して電圧変動を補償す
るのに必要な静止形無効電力補償装置の出力を演算で求
めてオープンループ的な制御を行うので、より高速に電
圧変動を抑えることができる。定常状態での無効電力フ
ィードバックループおよび電圧フィードバックループに
ついては第1、第2の実施例の説明と全く同じなので省
略する。
Qs = ΔQ + ΔP × (R / L) (1) Therefore, the resistance component and the inductance component of the distribution line or the transmission line 6 from the substation or power plant to the local point are stored in the line constant storage circuit 25 and stored. The third arithmetic circuit 26 calculates the equation (1) to calculate the reactive power command value for compensating the fluctuation of the interphase voltage at the installation point of the static var compensator due to the sudden change of the load, and the adding circuit 27 And the first arithmetic circuit 1
By adding the reactive power command value from 3 and Qs, a reactive power command signal that can cope with a sudden change in load is obtained. Thus, according to this embodiment, a sudden change in load is detected,
The open-loop control is performed by calculating the output of the static var compensator required to compensate for voltage fluctuations in consideration of the distribution line or transmission line constants, so voltage fluctuations can be suppressed faster. You can Since the reactive power feedback loop and the voltage feedback loop in the steady state are exactly the same as those described in the first and second embodiments, the description thereof will be omitted.

【0030】なお、本実施例では信号処理を電子回路で
行った場合を想定しブロック図で提示したが、各制御の
信号処理をマイクロコンピュータのソフトウェア処理で
行っても実現できる。
In the present embodiment, the case where the signal processing is performed by the electronic circuit is assumed and presented in the block diagram, but the signal processing for each control can be realized by the software processing of the microcomputer.

【0031】また、各実施例の説明において、静止形無
効電力補償装置の主回路の第2のリアクトル2とコンデ
ンサ3はY形結線の例で説明してきたが、このリアクト
ルとコンデンサはΔ結線にしても構わない。また、本実
施例は三相回路にて説明してきたが単相回路に適用でき
ることは言うまでもない。
Further, in the description of each embodiment, the second reactor 2 and the capacitor 3 of the main circuit of the static var compensator have been described as an example of Y-type connection, but the reactor and the capacitor are Δ-connection. It doesn't matter. Further, although the present embodiment has been described with respect to the three-phase circuit, it goes without saying that it can be applied to the single-phase circuit.

【0032】[0032]

【発明の効果】以上の説明から明らかなように、本発明
によれば、次のような効果を得ることができる。まず、
第1は配電線または送電線の電圧一定制御が相間電圧の
歪みに関わらず正確に行える。したがって今日のように
配電線または送電線の高調波が増加し、電圧歪みが無視
できない状況にあって、電圧安定化に非常に効果的であ
る。第2にサイリスタ電流或いは無効電力のフィードバ
ックループを設け、主回路の電流に上限値を設定するこ
とでサイリスタの破壊を防止することができる。これに
より配電系統または送電系統の設備機器として要求され
る高信頼性を確保できる。第3に停電から復電時に0V
arの運転点から静止形無効電力補償装置を起動し、過
渡的な異常電圧を防ぐことができる。第4に配電線また
は送電線の電圧急変時にその電圧急変を抑える無効電力
を発生させて高速に電圧変動を補正することができる。
As is apparent from the above description, according to the present invention, the following effects can be obtained. First,
First, the voltage constant control of the distribution line or the transmission line can be accurately performed regardless of the distortion of the interphase voltage. Therefore, it is very effective for voltage stabilization in the situation where harmonics of distribution lines or transmission lines increase and voltage distortion cannot be ignored like today. Secondly, a thyristor current or reactive power feedback loop is provided, and the upper limit of the current of the main circuit is set to prevent destruction of the thyristor. As a result, it is possible to ensure the high reliability required for equipment of the distribution system or the transmission system. Third, 0V when power is restored after power failure
The static var compensator can be activated from the operating point of ar to prevent transient abnormal voltage. Fourthly, when the voltage of the distribution line or the power transmission line suddenly changes, reactive power that suppresses the sudden voltage change can be generated to quickly correct the voltage variation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の静止形無効電力補償装
置の接続図
FIG. 1 is a connection diagram of a static var compensator according to a first embodiment of the present invention.

【図2】本発明の第2の実施例の静止形無効電力補償装
置の接続図
FIG. 2 is a connection diagram of a static var compensator according to a second embodiment of the present invention.

【図3】本発明の第3の実施例の静止形無効電力補償装
置の接続図
FIG. 3 is a connection diagram of a static var compensator according to a third embodiment of the present invention.

【図4】本発明の第4の実施例の静止形無効電力補償装
置の接続図
FIG. 4 is a connection diagram of a static var compensator according to a fourth embodiment of the present invention.

【図5】本発明の第5の実施例の静止形無効電力補償装
置の接続図
FIG. 5 is a connection diagram of a static var compensator according to a fifth embodiment of the present invention.

【図6】従来例の静止形無効電力補償装置の接続図FIG. 6 is a connection diagram of a conventional static var compensator.

【符号の説明】[Explanation of symbols]

1 第1のリアクトル 2 第2のリアクトル 3 コンデンサ 4 サイリスタ回路 5 サイリスタ駆動回路 6 配電線または送電線 7 計器用変圧器 8 全波整流回路 9 タイミング検出回路 10 演算回路 11 実効値検出回路 12 第2の演算回路 13 第1の演算回路 14 リミッタ 15 無効電力検出回路 16,17 変流器 18 サイリスタ電流検出回路 19 記憶回路 20 タイマ 21 電源立ち上がり検出回路 22 第2の変流器 23 有効電力変化分検出回路 24 無効電力変化分検出回路 25 線路定数記憶回路 26 第3の演算回路 27 加算回路 1 1st reactor 2 2nd reactor 3 Capacitor 4 Thyristor circuit 5 Thyristor drive circuit 6 Distribution line or transmission line 7 Instrument transformer 8 Full-wave rectifier circuit 9 Timing detection circuit 10 Arithmetic circuit 11 Effective value detection circuit 12 2nd Operation circuit 13 First operation circuit 14 Limiter 15 Reactive power detection circuit 16, 17 Current transformer 18 Thyristor current detection circuit 19 Memory circuit 20 Timer 21 Power supply rise detection circuit 22 Second current transformer 23 Active current change detection Circuit 24 Reactive power change detection circuit 25 Line constant memory circuit 26 Third arithmetic circuit 27 Adder circuit

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 配電線または送電線に結線された第1の
リアクトルと、第2のリアクトルとコンデンサの直列回
路と、前記第1のリアクトルと第2のリアクトルの接続
点に結線された一つまたは複数個直列のサイリスタの逆
並列回路よりなるサイリスタ回路とから構成された主回
路と、前記配電線または送電線に取り付けられた変圧器
(以下PTと称す)と、前記PTの出力の実効値を検出
する実効値検出回路と、前記PTの出力を入力とし前記
配電線または送電線の相間電圧のゼロクロスのタイミン
グを検出するタイミング検出回路と、前記実効値検出回
路の出力信号とあらかじめ設定された電圧指令値との誤
差信号を入力とする第1の演算回路と、前記第1の演算
回路の出力信号と前記タイミング検出回路の出力を入力
とし前記サイリスタ回路の導通角を制御するゲート信号
を出力するサイリスタ駆動回路とを備え、前記サイリス
タ回路の導通角を制御し前記主回路に流れる無効電力を
連続に制御して前記配電線または送電線の電圧一定制御
を行うようにした静止形無効電力補償装置。
1. A first reactor connected to a distribution line or a transmission line, a series circuit of a second reactor and a capacitor, and one connected to a connection point of the first reactor and the second reactor. Alternatively, a main circuit composed of a thyristor circuit composed of an antiparallel circuit of a plurality of thyristors in series, a transformer (hereinafter referred to as PT) attached to the distribution line or the transmission line, and an effective value of the output of the PT. , A timing detection circuit for detecting the zero-crossing timing of the phase-to-phase voltage of the distribution line or the transmission line using the output of the PT as an input, and an output signal of the RMS value detection circuit set in advance. A first arithmetic circuit that receives an error signal from a voltage command value, and an output signal of the first arithmetic circuit and an output of the timing detection circuit that are input to the thyristor. A thyristor drive circuit that outputs a gate signal that controls the conduction angle of the circuit, and controls the conduction angle of the thyristor circuit to continuously control the reactive power that flows in the main circuit to keep the voltage of the distribution line or the transmission line constant. A static var compensator designed to perform control.
【請求項2】 配電線または送電線に結線された第1の
リアクトルと、第2のリアクトルとコンデンサの直列回
路と、前記第1のリアクトルと第2のリアクトルの接続
点に結線された一つまたは複数個直列のサイリスタの逆
並列回路よりなるサイリスタ回路とから構成された主回
路と、前記配電線または送電線に取り付けられたPT
と、前記PTの出力の実効値を検出する実効値検出回路
と、前記PTの出力を入力とし前記配電線または送電線
の相間電圧のゼロクロスのタイミングを検出するタイミ
ング検出回路と、前記第1のリアクトルと前記配電線ま
たは送電線の間に設置され前記主回路の入力電流を検出
する変流器(以下CTと称す)と、前記PTと前記CT
の出力信号を入力とし前記主回路に流れ込む無効電力を
検出する無効電力検出回路と、前記電圧実効値検出回路
の出力信号とあらかじめ設定された電圧指令値との誤差
信号を入力とする第1の演算回路と、前記第1の演算回
路の出力信号を入力とするリミッタと、前記リミッタの
出力と前記無効電力検出回路の出力信号との誤差信号を
入力とする第2の演算回路と、前記第2の演算回路の出
力信号と前記タイミング検出回路の出力信号を入力とし
前記サイリスタ回路の導通角を制御するゲート信号を出
力するサイリスタ駆動回路とを備え、前記サイリスタ回
路の導通角を制御し前記主回路に流れる無効電力を連続
に制御して前記配電線または送電線の電圧一定制御を行
うようにした静止形無効電力補償装置。
2. A first reactor connected to a distribution line or a transmission line, a series circuit of a second reactor and a capacitor, and one connected to a connection point of the first reactor and the second reactor. Alternatively, a main circuit composed of a thyristor circuit composed of an anti-parallel circuit of a plurality of serial thyristors, and a PT attached to the distribution line or transmission line.
An effective value detection circuit that detects an effective value of the PT output; a timing detection circuit that receives the output of the PT and detects a zero-cross timing of the interphase voltage of the distribution line or the transmission line; A current transformer (hereinafter referred to as CT) that is installed between a reactor and the distribution line or the transmission line and detects an input current of the main circuit, the PT and the CT.
Of the reactive power detection circuit for detecting the reactive power flowing into the main circuit by inputting the output signal of the above, and the error signal between the output signal of the voltage effective value detection circuit and the preset voltage command value as the input. An arithmetic circuit; a limiter that receives the output signal of the first arithmetic circuit; a second arithmetic circuit that receives the error signal between the output of the limiter and the output signal of the reactive power detection circuit; And a thyristor drive circuit that outputs a gate signal that controls the conduction angle of the thyristor circuit by using the output signal of the second arithmetic circuit and the output signal of the timing detection circuit as input, and controls the conduction angle of the thyristor circuit. A static var compensator for continuously controlling reactive power flowing in a circuit to perform constant voltage control of the distribution line or the transmission line.
【請求項3】 配電線または送電線に結線された第1の
リアクトルと、第2のリアクトルとコンデンサの直列回
路と、前記第1のリアクトルと第2のリアクトルの接続
点に結線された一つまたは複数個直列のサイリスタの逆
並列回路よりなるサイリスタ回路とから構成された主回
路と、前記配電線または送電線に取り付けられたPT
と、前記PTの出力の実効値を検出する実効値検出回路
と、前記PTの出力を入力とし前記配電線または送電線
の相間電圧のゼロクロスのタイミングを検出するタイミ
ング検出回路と、前記サイリスタ回路に直列に取り付け
られたCTと、前記CTの出力信号を入力とし前記サイ
リスタ回路に流れる電流値を検出するサイリスタ電流検
出回路と、前記電圧実効値検出回路の出力信号とあらか
じめ設定された電圧指令値との誤差信号を入力とする第
1の演算回路と、前記第1の演算回路の出力信号を入力
とするリミッタと、前記リミッタの出力信号と前記サイ
リスタ電流検出回路の出力信号との誤差信号を入力とす
る第2の演算回路と、前記第2の演算回路の出力信号と
前記タイミング検出回路の出力信号を入力とし前記サイ
リスタ回路の導通角を制御するゲート信号を出力するサ
イリスタ駆動回路とを備え、前記サイリスタ回路の導通
角を制御し前記主回路に流れる無効電力を連続に制御し
て前記配電線または送電線の電圧一定制御を行うように
した静止形無効電力補償装置。
3. A first reactor connected to a distribution line or a transmission line, a series circuit of a second reactor and a capacitor, and one connected to a connection point of the first reactor and the second reactor. Alternatively, a main circuit composed of a thyristor circuit composed of an anti-parallel circuit of a plurality of serial thyristors, and a PT attached to the distribution line or transmission line.
An effective value detection circuit for detecting the effective value of the output of the PT, a timing detection circuit for detecting the zero-cross timing of the interphase voltage of the distribution line or the transmission line using the output of the PT as an input, and the thyristor circuit. A CT mounted in series, a thyristor current detection circuit that receives an output signal of the CT and detects a current value flowing in the thyristor circuit, an output signal of the voltage effective value detection circuit, and a preset voltage command value. Of the error signal of the first thyristor current detecting circuit and the output signal of the first arithmetic circuit, the limiter receiving the output signal of the first arithmetic circuit, and the output signal of the thyristor current detection circuit And an output signal of the second arithmetic circuit and an output signal of the timing detection circuit as input, and conduction of the thyristor circuit. A thyristor drive circuit that outputs a gate signal that controls the voltage of the thyristor circuit, and controls the conduction angle of the thyristor circuit to continuously control the reactive power flowing in the main circuit to perform constant voltage control of the distribution line or the transmission line. Static var compensator.
【請求項4】 配電線または送電線に結線された第1の
リアクトルと、第2のリアクトルとコンデンサの直列回
路と、前記第1のリアクトルと第2のリアクトルの接続
点に結線された一つまたは複数個直列のサイリスタの逆
並列回路よりなるサイリスタ回路とから構成された主回
路と、前記配電線または送電線に取り付けられたPT
と、前記PTの出力の実効値を検出する実効値検出回路
と、前記PTの出力を入力とし前記配電線または送電線
の相間電圧のゼロクロスのタイミングを検出するタイミ
ング検出回路と、前記第1のリアクトルと前記配電線ま
たは送電線の間に設置され前記主回路の入力電流を検出
するCTと、前記PTと前記CTの出力信号を入力とし
前記主回路に流れ込む無効電力を検出する無効電力検出
回路と、前記電圧実効値検出回路の出力信号とあらかじ
め設定された電圧指令値との誤差信号を入力とする第1
の演算回路と、前記第1の演算回路の出力信号と前記無
効電力検出回路の出力信号との誤差信号を入力とする第
2の演算回路と、前記第2の演算回路の出力信号と前記
タイミング検出回路の出力信号を入力とし前記サイリス
タ回路の導通角を制御するゲート信号を出力するサイリ
スタ駆動回路と、電源立上がり検出回路と、前記電源立
上がり検出回路の出力信号を入力とし電源立上がり後あ
る一定時間を一回だけカウントするタイマと、前記タイ
マの出力と前記サイリスタ駆動回路の入力信号と前記無
効電力検出回路の出力信号とを入力とし前記タイマのタ
イムアップ後の通常運転状態で無効電力が0Var近傍
のときの前記サイリスタ駆動回路の入力信号を記憶し電
源が切れた状態でも記憶内容を保持する記憶回路とを備
え、前記第2の演算回路は、前記第1の演算回路の出力
信号と前記無効電力検出回路の出力信号との前記誤差信
号以外に前記記憶装置の出力信号と前記タイマの出力信
号とが入力されて、電源立上がり後前記タイマのタイム
アップまでは前記記憶回路の記憶内容である無効電力が
0Var近傍となる出力信号を出力し、前記タイマのタ
イムアップ後は通常の演算処理を行うように構成し、前
記サイリスタ駆動回路により前記サイリスタ回路の導通
角を制御し、前記主回路に流れる無効電力を連続に制御
して前記配電線または送電線の電圧一定制御を行うよう
にした静止形無効電力補償装置。
4. A first reactor connected to a distribution line or a transmission line, a series circuit of a second reactor and a capacitor, and one connected to a connection point of the first reactor and the second reactor. Alternatively, a main circuit composed of a thyristor circuit composed of an anti-parallel circuit of a plurality of serial thyristors, and a PT attached to the distribution line or transmission line.
An effective value detection circuit that detects an effective value of the PT output; a timing detection circuit that receives the output of the PT and detects a zero-cross timing of the interphase voltage of the distribution line or the transmission line; A CT installed between the reactor and the distribution line or the transmission line to detect the input current of the main circuit, and a reactive power detection circuit to detect the reactive power flowing into the main circuit by using the output signals of the PT and the CT as inputs. And an error signal between the output signal of the voltage effective value detection circuit and a preset voltage command value as input
Arithmetic circuit, a second arithmetic circuit that receives an error signal between the output signal of the first arithmetic circuit and the output signal of the reactive power detection circuit, the output signal of the second arithmetic circuit, and the timing. A thyristor drive circuit that receives the output signal of the detection circuit as an input and outputs a gate signal that controls the conduction angle of the thyristor circuit, a power supply rise detection circuit, and an output signal of the power supply rise detection circuit as an input and a certain time after the power supply rises. For inputting the output of the timer, the input signal of the thyristor drive circuit, and the output signal of the reactive power detection circuit as the input, and the reactive power is near 0 Var in the normal operating state after the timer times out. And a storage circuit that stores the input signal of the thyristor drive circuit at the time of, and retains the stored content even when the power is off. The circuit receives the output signal of the storage device and the output signal of the timer in addition to the error signal between the output signal of the first arithmetic circuit and the output signal of the reactive power detection circuit, and after the power supply rises, the circuit The thyristor drive circuit is configured to output an output signal in which the reactive power stored in the memory circuit is close to 0 Var until the timer times out, and to perform normal arithmetic processing after the timer times up. A static var compensator for controlling a conduction angle of the thyristor circuit and continuously controlling reactive power flowing in the main circuit to perform constant voltage control of the distribution line or the transmission line.
【請求項5】 配電線または送電線に結線された第1の
リアクトルと、第2のリアクトルとコンデンサの直列回
路と、前記第1のリアクトルと第2のリアクトルの接続
点に結線された一つまたは複数個直列のサイリスタの逆
並列回路よりなるサイリスタ回路とから構成された主回
路と、前記配電線または送電線に取り付けられたPT
と、前記PTの出力の実効値を検出する実効値検出回路
と、前記PTの出力を入力とし前記配電線または送電線
の相間電圧のゼロクロスのタイミングを検出するタイミ
ング検出回路と、前記第1のリアクトルと前記配電線ま
たは送電線の間に設置され前記主回路の入力電流を検出
する第1のCTと、前記PTと前記第1のCTの出力信
号を入力とし前記主回路に流れ込む無効電力を検出する
無効電力検出回路と、前記配電線または送電線に前記C
Tよりも負荷側に取り付けられた第2のCTと、前記P
Tの出力信号と前記第2のCTの出力信号を入力とし前
記配電線または送電線に流れる有効電力の変化分を検出
する有効電力変化分検出回路と、前記PTの出力信号と
前記第2のCTの出力信号を入力とし前記配電線または
送電線に流れる無効電力の変化分を検出する無効電力変
化分検出回路と、現地点までの前記配電線または送電線
の線路定数を記憶する線路定数記憶回路と、前記有効電
力変化分検出回路と前記無効電力変化分検出回路と前記
線路定数記憶回路とを入力とする第3の演算回路と、前
記電圧実効値検出回路の出力信号とあらかじめ設定され
た電圧指令値との誤差信号を入力とする第1の演算回路
と、前記第3の演算回路の出力信号と前記第1の演算回
路の出力信号を入力とする加算回路と、前記加算回路の
出力信号と前記無効電力検出回路の出力信号との誤差信
号を入力とする第2の演算回路と、前記第2の演算回路
の出力信号と前記タイミング検出回路の出力信号を入力
とし前記サイリスタ回路の導通角を制御するゲート信号
を出力するサイリスタ駆動回路とを備え、前記サイリス
タ回路の導通角を制御し前記主回路に流れる無効電力を
連続に制御して前記配電線または送電線の電圧一定制御
を行うようにした静止形無効電力補償装置。
5. A first reactor connected to a distribution line or a transmission line, a series circuit of a second reactor and a capacitor, and one connected to a connection point of the first reactor and the second reactor. Alternatively, a main circuit composed of a thyristor circuit composed of an anti-parallel circuit of a plurality of serial thyristors, and a PT attached to the distribution line or transmission line.
An effective value detection circuit that detects an effective value of the PT output; a timing detection circuit that receives the output of the PT and detects a zero-cross timing of the interphase voltage of the distribution line or the transmission line; A first CT that is installed between the reactor and the distribution line or the transmission line and detects an input current of the main circuit, and a reactive power that flows into the main circuit by using the output signals of the PT and the first CT as input. The reactive power detection circuit for detecting, and the C in the distribution line or the transmission line.
The second CT attached to the load side of T and the P
An active power change amount detection circuit which receives an output signal of T and an output signal of the second CT and detects a change amount of active power flowing in the distribution line or the power transmission line, an output signal of the PT and the second A reactive power change detection circuit that receives a CT output signal as an input and detects a change in the reactive power that flows in the distribution line or the transmission line, and a line constant memory that stores the line constant of the distribution line or the transmission line up to the local point A circuit, a third arithmetic circuit having the active power change detection circuit, the reactive power change detection circuit, and the line constant storage circuit as inputs, and an output signal of the voltage effective value detection circuit, which are set in advance. A first arithmetic circuit that receives an error signal with respect to a voltage command value, an adder circuit that receives the output signal of the third arithmetic circuit and an output signal of the first arithmetic circuit, and an output of the adder circuit. Signal and the above A second arithmetic circuit that receives an error signal from the output signal of the power detection circuit and an output signal of the second arithmetic circuit and an output signal of the timing detection circuit that control the conduction angle of the thyristor circuit. A thyristor drive circuit for outputting a gate signal, which controls the conduction angle of the thyristor circuit to continuously control the reactive power flowing in the main circuit to perform constant voltage control of the distribution line or the transmission line. Type reactive power compensator.
JP31095593A 1993-12-13 1993-12-13 Static var compensator Expired - Fee Related JP3328039B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31095593A JP3328039B2 (en) 1993-12-13 1993-12-13 Static var compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31095593A JP3328039B2 (en) 1993-12-13 1993-12-13 Static var compensator

Publications (2)

Publication Number Publication Date
JPH07160346A true JPH07160346A (en) 1995-06-23
JP3328039B2 JP3328039B2 (en) 2002-09-24

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ID=18011416

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Application Number Title Priority Date Filing Date
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101245169B1 (en) * 2011-02-25 2013-03-19 (주)파워닉스 Static var compensator and control method of the static var compensator
US9912230B2 (en) 2015-09-08 2018-03-06 Lsis Co., Ltd. Static VAR compensator apparatus and operating method thereof
US9948176B2 (en) 2015-08-19 2018-04-17 Lsis Co., Ltd. Static VAR compensator apparatus and operating method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101245169B1 (en) * 2011-02-25 2013-03-19 (주)파워닉스 Static var compensator and control method of the static var compensator
US9948176B2 (en) 2015-08-19 2018-04-17 Lsis Co., Ltd. Static VAR compensator apparatus and operating method thereof
US9912230B2 (en) 2015-09-08 2018-03-06 Lsis Co., Ltd. Static VAR compensator apparatus and operating method thereof

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