JPS59148951A - Decoding system of instruction - Google Patents

Abstract

PURPOSE:To shorten and uniform instruction decoding time by outputting a flag indicating whether an address of an instruction to be branched is valied or invalid by using a mapping ROM on the basis of an instruction code indicated by interpreter type language and outputting the flag data. CONSTITUTION:Output data from mapping ROMs 13-15 are inputted to a multiplexer 16 through data lines Ld1-Ld3 and a part of the output data is inputted as a mapping effectiveness discriminating part 17 as a mapping effectiveness discriminating flag through flag lines Lf1-Lf3. The mapping ROMs 13-15 discriminates whether an instruction code applied from an instruction register 12 is valid or invalid and outputs flag information. The mapping effectiveness discriminating part 17 discriminates whether the data from the mapping ROM are valid or invalid by using the discrimination flag and outputs a switching signal to the multiplexer 16 through a line Lx, so that only the output of the prescribed mapping ROM is sent to a bus 11. Thus, the instruction decoding time can be shortened and uniformed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction decoding method for interpreted languages.

In general, in control systems, various application field-oriented languages, namely problem-oriented languages (POL), are often used.
This is often performed using an interpreted method. FIG. 1 is a schematic diagram showing a configuration example of a control system using POL commands, and FIG. 2 is a 70-chart for explaining its operation.

In FIG. 1, 1 is a memory that stores the above-mentioned POL command, 2 is an arithmetic processing unit (MPU) that performs predetermined arithmetic processing based on the instruction, and 3 is an input/output bag ff1 ( Ilo), 4 is a common bus,
The control operation of the MPU 2 is performed as shown in FIG. 2, for example. That is, the MPU 2 first fetches the POL instruction from the memory 1 (2), temporarily stores it in a register (not shown), and decodes the instruction (0). Instruction decoding in this case means calculating the preceding ring address of the machine language subroutine from the instruction code.
(AND) The start address (instruction branch destination address) of the subroutine corresponding to the instruction is calculated, and as a result, the AND instruction is executed (O).

When that instruction is executed, the program counter is incremented (O) and the next instruction is fetched from the memory (■).Then, by repeating the same operation as above, the next OR (OR) instruction is executed. (2), and further executes a write command (@). In other words, in the interpreter method, each instruction code corresponds to one subroutine made of machine code, and it is necessary to decode the branch destination address of the subroutine for each instruction, which takes a long time to decode. It has the disadvantage of becoming. Therefore, the conventional method was (a) to calculate the instruction branch destination address by software.

A method of branching using a so-called mapping ROM, in which an instruction branch destination address table is created in a ROM (read-only memory) and an instruction branch destination address is output when an instruction code is applied to the address line of the ROM. method or simply matuping).

Two methods are known, but the method (original) is generally used because it takes less time to decode an instruction.

On the other hand, in the POL command for control systems,
Processing must be fast.

Ex) Sequence control commands must be 1-word commands.

c) The operand part of the sequence control instruction must be multi-bit long because it requires a large number of input/output points.

2) There is a wide variety of commands.

etc. are generally required. Therefore, in order to meet this requirement, the POL command format is stripped down to a configuration as shown in FIG. 3. Note that FIG. 3 is an explanatory diagram illustrating the instruction format of the POL instruction.

Figure 3 shows an example of a POL instruction with 1 word (16 bits), where (g) is a sequence control instruction, (b) is an arithmetic operation instruction, and (c) is a 2-word long instruction. In a sequence control command such as 0 times diagram (a), which shows each case, the 12 to 15 bits indicating the instruction operation part (operation code, abbreviated as op code) are expressed in hexadecimal numbers from '0 to Assigned when E'',
The operand length can be 12 bits. In addition, 15 types of instructions can be defined.
If bits up to (P) are hexadecimal "F" and bits 8 to 11 are other than 6F#, that is, '0 to E', they are assigned to instructions that require relatively high speed, such as arithmetic operation instructions. Therefore, 15 (0 to Fli) x 16 = 240 types of instructions can be defined. Also, as shown in the same figure (c), when bits 8 to 15 of the instruction code are expressed in hexadecimal as FF'',
It is assigned to instructions other than those mentioned above (for example, 2-word length instructions), and 16×16=256 types of instructions can be defined. Based on the POL command name that takes such an instruction form, the address line is smaller than the instruction word length, for example, 11. For mapping using OM, for example, as shown in Figure 4,
8 to 15 bits of the instruction code are field 4 to 1.
It is necessary to perform mapping up to three times by dividing up to 1 bit into a ■ field and 0 to 7 bits into a ■ field. Note that FIG. 4 is an explanatory diagram for explaining an example of dividing a command word. In other words, a 1-sequence control instruction can determine the branch destination address by mapping only the ■ field, but an arithmetic operation instruction requires mapping between the ■ field and ■ field, and a 2-word instruction, etc.
All O and @ fields need to be mapped.

FIG. 5 is a block diagram showing a conventional example of an instruction decoding method for such an instruction format, and FIG. 6 is a flowchart illustrating its operation. In FIG. 5, 11 is a data bus, 12 is a first
Inserts (action registers, 13 to 15) that temporarily store instruction words read from the memory indicated by reference numeral 1 in the figure
is a mapping ROM that outputs branch destination address information by referring to fields 1 to 0 of the instruction word.

The operation will be explained based on the chart 70 in FIG.

When the instruction code is set in the instruction register 12 shown in FIG. 5 (0), the program first branches to the start routine for field mapping (@), and performs field mapping (0) 0. To judge whether the upper 4 bits of
If the result is NO (N, 0), the program branches to the sequence control command (2), and if the result is YES, the program branches to the field mapping start routine (2). When branching to θ, ■field mapping is performed in the same way as above (
■), ■Determine whether the upper 4 bits of the field are F” (■), If NO, branch to an arithmetic operation instruction, etc.■), If YES, ■Branch to the field mapping startup routine (■ ).

When the routine branches to the routine ■, it then performs mapping of the ■fields (■), and branches to instructions other than the above (■).
). In addition, in FIG. 6, @, θ.

(2) is processed by software. In other words, in the conventional method, a subroutine is prepared to map each field, and if the instruction branch destination address cannot be determined by mapping a field or O field, control is returned to the software each time a new field is created. Mapping, that is, mapping is performed in stages according to the instruction format. therefore,
When mapping the ■field or ■field, there is a disadvantage that the instruction decoding time becomes longer because software processing is involved.

In other words, not only does the instruction decoding time become longer depending on the type of instruction (in the example in Figure 3, the instruction decoding time increases in the order of (a), (b), and (c)), but also the software processing becomes more complex. It has the disadvantage of becoming.

This invention has been made in view of the above, and aims to shorten and equalize the instruction decoding time when decoding an instruction branch destination address using a multi-stage mapping method, and to simplify the software related thereto. It is something.

The feature is that when a mapping TtOM is used to decode a branch destination address from an instruction code expressed in an interpreted language, the mapping ROM determines whether the output instruction branch destination address information is valid or invalid. By providing the function of outputting flag information indicating whether the instruction exists, a multi-step mapping operation is realized in hardware, thereby shortening and making the instruction decoding time uniform.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a configuration diagram showing an embodiment of the present invention.

The feature of this embodiment is that it is provided with a multiplexer 16, a mapping validity determination section 17, flag information outputs ILfx to Lf3, and a multiplexer switching line Lx compared to the one shown in FIG.

The output data (branch destination address information) of the mapping ROMs 13 to 15 are input to the multiplexer 16 via data 11Ldt to Ld3, respectively, while a part of the output data is inputted to the mapping validity determination 7 lag by 7 lag ML.
The data is input to the mapping validity determination unit 17 via f1 to Lf3. Note that the mapping operations M13 to M15 store in advance what kind of instruction code is given to enable or disable the output, so when an instruction code is given via the instruction register 12, the corresponding instruction is Information indicating validity or invalidity depending on the code, that is, determination flag information can be output.

The mapping determination unit 17 uses the determination flag to determine whether or not data output from which mapping ROM is valid, and outputs a predetermined switching signal to the multiplexer 16 via mLx. The multiplexer 16 selects only the output of a predetermined mapping ROM and sends it to the data bus 11. In addition, the mapping validity determination unit 17 assigns the priority of the determination flags in the order of, for example, ROMI 3 determination flag>ROM14 determination flag>ROMI5 determination flag, and if the determination flag 7 of ROMI 3 indicates "6 Valid" , the multiplexer 16 is switched to the mapping R, 0M13 channel regardless of the contents of the determination flag in the ROM14°ROM15.
If the determination flag of M13 indicates "1 invalid" and the determination flag of ROMI 4 indicates "valid", the multiplexer 16 is switched to the output of mapping R, 0M14, regardless of the contents of the determination flag of ROM15. R
Both judgment flags of OM13.14 indicate "invalid".
The multiplexer 16 is switched to the field of the mapping ROM 15 only when the determination flag of the ROM 15 indicates "valid". Although the determination unit 17 is not necessarily required, by providing it, the ROM 13
．． It is possible to detect the case in which all the determination flags in 14.15 indicate 1 invalid, and it is possible to determine the abnormality of the ROM by kneading, which brings about effects such as being able to stop the mapping operation, for example. .For that purpose, the judgment flag of ROMI 5 must always be set to 6.
It is necessary to store data to that effect in the ROM 15 in advance so as to output it.

In the above configuration, in order to decode the POL instruction shown in FIG. 3, for example, it is necessary to: Mapping RO
Store it in M13 in advance. Similarly, if the upper 4 bits of the 0 field are 'F', data to that effect is stored in the mapping ROM 14 so that the determination flag of the ROM 14 outputs '9 invalid'. Also, ROM1
In order to output "valid" for the flag No. 5, data to that effect may be stored in the mapping R, 0M15. In this way, for example, when an instruction code of 'F O00' in hexadecimal notation is set in the instruction register, the judgment flag of ROM13 is set to '6 invalid', while It, 0M
Both judgment flags in 14.15 indicate “valid”, so
The mapping validity determining unit 17 cuts the output of the mapping ROM 14 from the multiplexer 16, thereby providing the output, that is, the branch destination address, as valid to the MPU 2 of FIG. 1 via the data bus 11.

As described above, according to the present invention, the multi-step mapping operation of an interpreted language is controlled only by hardware without performing software processing in the middle by using a part of the mapping ROM output data as a mapping validity determination flag. By providing a 0-or-1 mapping validity determination unit, the time spent on decoding instructions can be significantly reduced, and the interpreter-based language processing can be speeded up. This has the effect of making it possible to monitor abnormalities in the mapping ROM.

In addition to the multi-stage mapping method described above, this invention is not only applicable to general control devices using a microprogram control method, but also applicable to P.
It can be used as an instruction decoding method not only for OL instructions but also for all interpreted languages.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing a general configuration example of a control system using POL commands, Fig. 2 is a flowchart explaining the execution procedure of POL commands, and Fig. 3 is an explanatory diagram explaining the command format of POL commands. , FIG. 4 is an explanatory diagram for explaining divided sequences of instruction codes. FIG. 5 is a block diagram showing the conventional side of the POL instruction decoding system, and FIG. The chart and FIG. 7 are configuration diagrams showing an embodiment of the present invention. Input/output device (Ilo
), 4... common lotus, 11... data bus, 12... instruction register,
13-15...Matsuping ROM, 16...
...Multiplexer, 17...Mapping validity determination section, La1 to La3...Address line, L
dl~Ld3...Data ltL Lft-Lf
a...Flag line, Lx...Multiplexer switching line Agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki 1@1 Figure 2 Figure 3-E θ~E Figure 4 Figure 6 Figure 5 Figure 1

Claims (1)

[Claims] Instruction registers are provided for reading instruction codes written in an interpreted language from a predetermined memory and temporarily storing them, and for instruction codes that are divided into a predetermined number of mutually overlapping areas. It has a predetermined number of mapping ROMs that output branch addresses according to the divided instruction codes, and decodes the branch destination address of the instruction by sequentially mapping each of the mapping ROMs according to the divided instruction codes. In the instruction decoding method, each of the mapping ROMs has the mapping RO
A flag information output means is provided for outputting flag information indicating whether or not the instruction branch destination address information output from M is valid, and each mapping operation is determined to be valid based on the flag information. An instruction decoding method characterized by comprising a selection means for determining invalidity and selecting and outputting only valid mapping ROM outputs.