JP2000357087A - Device and method for processing operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease a cycle not to execute a branching instruction by storing two branch destinations in the same instruction field. SOLUTION: Corresponding to an operation control signal S16 outputted from an instruction decoding part 2, an operation processing part 3 executes operation and updates a condition flag S13. The condition flag S13 and a condition code S12 from the instruction decoding part 2 are inputted to a branch destination discriminating part 4 and when the condition flag S13 and the condition code S12 are matched, corresponding to a branch address switching signal S22, a first branch destination address S11a is selected by an address switching part 6 but when the condition flag S13 and the condition code S12 are not matched, corresponding to the branch address switching signal S22, a second branch destination address S11b is selected by the address switching part 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method and an arithmetic processing device for executing an instruction conditionally.

[0002]

2. Description of the Related Art As a general architecture of a computer, there is a von Neumann type architecture. In accordance with a program storage method, such a computer stores a program to be executed by the computer in a storage device as well as data to be processed. Things. Generally, in a general-purpose computer system, in order to realize an arithmetic processing device that executes a program for performing arithmetic processing as an instruction, it is necessary that an instruction format, which is a format of the instruction, is defined.

FIG. 3 is a block diagram showing the configuration of a conventional arithmetic processing unit, and FIG. 4 is a conceptual diagram showing the configuration of an instruction format at the time of a branch instruction executed in the conventional arithmetic processing unit. In many cases, a condition for executing an instruction is specified, and a branch instruction is executed conditionally as in this example.

In FIG. 3, 1 is an instruction memory, 2 is an instruction decoding unit, 3 is an operation processing unit, 4 is a branch destination determination unit, 5 is an instruction address generation unit, S10 is an instruction, S11 is a branch destination address, S12 is a condition code, S13 is a condition flag,
S14 is an instruction memory address, S15 is a branch determination, S1
Reference numeral 6 denotes operation control, S17 denotes a branch instruction, and S18 denotes signals output from the instruction address generator.

In the instruction format shown in FIG. 4, an instruction field is composed of a condition code S12 indicating a condition determination, a branch instruction S100 executed according to the condition determination, and a branch destination address S11 designating an address of the instruction memory 1. are doing.

In the conventional arithmetic processing unit, when such an instruction is executed, the condition code S12 is changed to a condition flag S1 updated by the operation result of the operation processing unit 3.
3, the branch instruction S100 is executed when they match, and when they do not match, the branch instruction S100 is executed.
Do not execute.

An example of a program executed as an instruction having such an instruction format is shown by the following equations (Equation 1), (Equation 2), and (Equation 3). In this example, when the subtraction result is zero, the process branches to an address represented by G01, and when the subtraction result is not zero, the process branches to an address represented by G02.

[0008]

SUB-CC X1 Y1 Z1

[0009]

[Equation 2] JMP (EQ) G01

[0010]

## EQU3 ## JMP (NE) G02 In the equation (Equation 1) of this program, SUB means to indicate a subtraction instruction, and -CC means to update a condition flag with the operation result of the instruction. In the equations (Equation 2) and (Equation 3), JMP indicates a branch instruction, EQ in parentheses indicates that branching is performed when the condition flag is zero, and NE indicates that the condition flag is not changed. This means branching when it is not zero. Therefore, the expression of (Equation 1) is obtained as “value (X1−Y1), and that value is Z1
Equation (2) is executed when the condition flag updated from the subtraction result of Equation (1) is zero. ,
Expression (3) means "branch to the branch destination address represented by G01", and is expressed by G02 when the condition flag updated from the subtraction result of expression (1) is not zero. Branch to branch destination address ".

[0011]

As described above, in the conventional arithmetic processing, when the condition flag is zero, the operation branches to a certain address, and when the condition flag is not zero, the operation branches to an address different from the above address. Therefore, the program must be divided into two steps as in the equations (Equation 2) and (Equation 3). Then, when the condition flag and the condition code do not match, a cycle in which the branch instruction is not executed occurs, and there is a problem that the instruction cycle becomes longer.

The present invention solves the above-mentioned problem of the prior art, and stores two branch destinations in the same instruction field to reduce the number of cycles in which a branch instruction is not executed. The purpose is to provide.

[0013]

According to an aspect of the present invention, there is provided an arithmetic processing unit for executing a conditional branch instruction, comprising: a condition code indicating a condition determination; Branch instruction to be executed,
Switching means for switching a branch destination address is provided for a signal configuration including two branch destination addresses indicating a branch destination of the branch instruction based on the condition code and a condition flag determined according to a result of the arithmetic processing. Things.

According to another aspect of the present invention, in the arithmetic processing method for executing a conditional branch instruction, a condition code indicating a condition determination, a branch instruction to be executed in accordance with the condition determination, and a branch destination of the branch instruction Is selected based on the condition code and a condition flag determined according to the result of the arithmetic processing, and a branch instruction is executed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an arithmetic processing unit for explaining an embodiment of the present invention. The arithmetic processing unit comprises an instruction memory 1, an instruction decoding unit 2, and an arithmetic processing unit 3. Branch destination determining unit 4 and instruction address generating unit 5
And an address switching unit 6 for switching a branch destination address. The instruction memory 1 holds an instruction group to be executed by the arithmetic processing unit, and outputs an instruction S10 to the instruction decoding unit 2. .

In accordance with the operation control signal S16 output from the instruction decoding unit 2, the operation processing unit 3 executes the operation and updates the condition flag S13. The branch destination determination unit 4 includes the condition flag S13 and the condition code S12 from the instruction decoding unit 2.
When the condition flag S13 and the condition code S12 match, the first branch destination address S by the address switching unit 6 according to the branch address switching signal S22.
11a, and if the condition flag S13 does not match the condition code S12, the branch address switching signal S
At 22, the address switching unit 6 selects the second branch destination address S11b.

The branch destination determining unit 4 inputs a branch instruction signal S17 indicating whether or not the instruction is a branch instruction from the instruction decoding unit 2,
In the case of a branch instruction, the first branch destination address S11a or the second branch destination address S
11b is transferred to the instruction memory address S14.
And When the instruction is not a branch instruction, the branch destination determining unit 4 selects the instruction memory address generator output signal S18 as the instruction memory address S14 according to the branch determination signal S15.

FIG. 2 is a conceptual diagram showing a configuration of an instruction format for a branch instruction executed in the arithmetic processing unit according to the present embodiment. As shown, the instruction format used in the present embodiment includes a branch instruction S100, a condition code S12, a first branch destination address S11a, and a second branch destination address S11b.

Next, the operation of the arithmetic processing unit according to the present embodiment when processing an instruction having the instruction format shown in FIG. 2 will be described with reference to a program example.

An example of a program executed as an instruction having the above-mentioned instruction format is the equation shown in (Equation 4) and (Equation 5). In this example, when the subtraction result is zero, the process branches to an address represented by G01, and when the subtraction result is not zero, the process branches to an address represented by G02.

[0022]

SUB-CC X1 Y1 Z1

[0023]

## EQU5 ## JMP (EQ) G01 G02 In the equation (Equation 4) of this program, SUB means to instruct a subtraction instruction, -CC means to update a condition flag with the operation result of the instruction, In the equation (Equation 5), JMP indicates a branch instruction, and EQ in parentheses means that the branch to the branch destination address represented by GO1 is performed when the condition flag is zero. This means that when the flag is not zero, branch to the branch destination address represented by GO2.

Therefore, the expression of (Equation 4) is expressed as "value (X1-
Y1) is obtained, the subtraction with the value of Z1 is performed, and the condition flag representing the operation result is updated. " When the condition flag updated from is zero, the program branches to the branch destination address represented by GO1, and when the condition flag is not zero, G
Branch to the branch destination address represented by O2 ".

As described above, by including two branch destination addresses in the instruction field, that is, by adding one branch destination address as compared with the conventional case, the word length of the instruction field becomes longer by the instruction address. Regardless of the value of the flag, branching can be performed in one step, the number of unused cycles can be reduced, and the instruction execution cycle can be shorter than in the related art.

When the word length of the instruction field is set to the same length as the conventional one, the number of bits representing the branch destination address becomes half that of the conventional one, and the range of addresses that can be branched is narrowed, but regardless of the value of the condition flag. , Branching can be performed in one step, the number of unused cycles can be reduced, and the instruction execution cycle can be shorter than in the prior art.

[0027]

As described above, according to the arithmetic processing apparatus and the arithmetic processing method of the present invention, since the branch instruction is executed in one step, the number of cycles which are not executed is reduced, and the execution of the instruction is smaller than in the prior art. The cycle can be shortened, and the program size can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processing unit for describing an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a configuration of an instruction format for a branch instruction used in the arithmetic processing device of the embodiment;

FIG. 3 is a block diagram showing a configuration of a conventional arithmetic processing device.

FIG. 4 is a conceptual diagram showing a configuration of an instruction format for a branch instruction used in a conventional arithmetic processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction memory 2 Instruction decoding part 3 Operation processing part 4 Branch destination judgment part 5 Instruction address generation part 6 Address switching part

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tadashi Shibata 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B033 AA02 BA03 BE00 CA07 DA15

Claims (2)

[Claims] In an arithmetic processing unit for executing a conditional branch instruction, a condition code indicating a condition determination, a branch instruction to be executed in accordance with the condition determination, and two branch destination addresses indicating a branch destination of the branch instruction are stored. An arithmetic processing apparatus comprising: a switching unit that switches a branch destination address based on a condition flag determined according to the condition code and a result of the arithmetic processing for a signal configuration that includes the arithmetic processing unit. 2. An arithmetic processing method for executing a conditional branch instruction, comprising: a condition code indicating a condition determination; a branch instruction executed according to the condition determination; and two branch destination addresses indicating a branch destination of the branch instruction. An arithmetic processing method for selecting a branch destination address and executing a branch instruction based on the condition code and a condition flag determined in accordance with a result of the arithmetic processing with respect to a signal configuration including the instruction.