JPH01309129A - Microprocessor - Google Patents

Abstract

PURPOSE:To always secure the same meaning for the conditional flags and to always decide these flags with the same conditional branch instructions, etc., by outputting the conditional flags based on the deciding information received from a decoding circuit and the information on the arithmetic result received from a computing element. CONSTITUTION:It is decided whether the data which carries out the arithmetic and tries to deliver the result has a code or not by deciding an arithmetic instruction via a decoding circuit 6. If said arithmetic subject data has a code, a flag generating circuit 7 can output the conditional flags 8 showing the difference of values, the coincidence, etc., and including the plus/minus codes based on the information of the arithmetic result received from a computing element 2 which carries out the arithmetic. While the flags 8 including no code can be outputted if said data has no code. Thus the handling data can be shown by the same flags 8 as long as the arithmetic result values are equal to each other and regardless of the presence of absence of the code of said data. Then the flags can be decided with the same conditional branch instructions, etc.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a microprocessor that has the function of performing calculations between multiple pieces of data, and in particular, the present invention relates to a microprocessor that has the function of executing calculations between multiple pieces of data. Regarding the improvement of the condition flag output mechanism.

(Prior Art) A microprocessor having a function of calculating data between a plurality of pieces of data is generally provided with a condition flag indicating whether the result of the calculation is positive, negative, or zero. Then, this condition flag is changed by reflecting the calculation result. A processing program or the like that uses a microprocessor is configured to make a judgment based on this condition flag and perform branching or the like.

Examples of such conventional condition flags include those shown in FIGS. 3 and 4, for example.

FIG. 3 is a block diagram showing a schematic configuration of the arithmetic unit 2 and its peripheral parts. 2 where the calculation is performed by the calculation unit 2
There are two operand data registers 1, 1a and 1b, holding data of .

There is also a computation result register 3 in which numerical data as a result of computation is stored. Then, N (negative > 9a, Z (zero) 9b, C (-I
Three condition flags 9, 9c and 9c, are provided.

FIG. 4 is a diagram showing a comparison between the combination of the internal states of the three condition flags 9, N9a, Z9b, and C9c, and the magnitude relationship of the calculation results.

When the Z flag 9b is 1, it indicates that the data held in the two operand data registers 1a and 1b (respective values are A and B) are equal once. Further, when the Z flag 9b is 0, it can be seen that the two data A and B are not equal.

However, when trying to judge the magnitude of two data A and B, as shown in Figure 4, the method of judgment changes depending on whether these data have a sign or not.
For example, if you want to determine whether A is smaller than B, you must determine whether or not the N flag 9a is 1 if it is signed, and by the C flag 9c if it is unsigned. It won't happen.

In the case of signed data, for example, the leftmost 1 bit is used as a positive (0) or negative (1) sign, and in the case of unsigned data, on the contrary, all Bits are treated as representing numeric data. On the other hand, during an operation, the operation is performed on all bits in exactly the same way, regardless of whether this leftmost bit is used as a sign or not. Then, regarding the result data of the operation, it is determined whether the leftmost 1 bit is treated as a sign or as data.

In other words, even if the result data is exactly the same, whether the operation result is zero, positive, or negative depends on whether it is treated as signed data or unsigned data. There are cases.

Therefore, in a conventional microprocessor, as a result of an operation regardless of the presence or absence of a sign, for example, if the leftmost bit is on, the N flag is set, if a carry occurs, the C flag is set, and if the result data is zero. If there was, I would have set the C flag.

A processing program or the like that judges the result of this calculation changes the type of condition flag to be judged depending on the presence or absence of a sign.

(Problem to be Solved by the Invention) However, with such conventional microprocessors, different condition flags must be used to determine the same magnitude relationship between signed data and unsigned data. Therefore, for example, even if one were to use a conditional branch instruction, a different conditional branch instruction had to be used depending on the presence or absence of a sign. Moreover, due to such a complicated and confusing method of use, programming errors were likely to occur. In addition, in the conventional example described above, three types of condition flags are not used for judgment, but one of these two flags, for example, negative (N) and carry (C), is based on the data to be collected. It became meaningless depending on the type (signed or not), making the hardware redundant.

The present invention has been made in view of the above-mentioned conventional circumstances, and its purpose is to perform calculations under the same conditions, regardless of whether or not the data to be handled has a sign. It is an object of the present invention to provide a microprocessor that can express conditions using the same condition flags and make decisions using the same conditional branch instructions.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve such an object, the microprocessor according to the present invention has an instruction to execute an operation on signed data having a positive or negative sign. Two types of operation instruction groups are provided: a signed operation instruction group and an unsigned operation instruction group that is an instruction for executing operations on unsigned data that does not have a positive or negative sign. A decoding circuit that determines which instruction group of arithmetic instruction groups the instruction belongs to and outputs determination information, the determination information from this decoding circuit, and information on the operation results from the arithmetic unit that executes the operation, The present invention is characterized by comprising a flag generation circuit that outputs condition flags such as size and match, including positive and negative signs, if the data is signed data, and outputs the condition flags that do not include the sign, if the data is unsigned data. It is something to do.

(Function) If a microprocessor has such a configuration,
Whether the data for which an operation is to be executed and a result is to be produced is signed or unsigned is determined by determining the operation instruction in the decoding circuit. Once it is clear whether the data to be operated on has a sign or not, the flag generation circuit uses the information on the operation result from the arithmetic unit that executes the operation to determine whether the data is large or small, including the positive or negative sign, and whether it matches. It becomes possible to output the condition flag of , and, if the data is unsigned data, it becomes possible to output the condition flag that does not include a sign.

In this way, regardless of the presence or absence of the sign of the data to be handled, if the magnitude of the operation result is the same, it will be represented by the same condition flag, and it will be possible to make a decision using the same conditional branch instruction or the like. Furthermore, the types of condition flags can be kept to a minimum, making it possible to eliminate redundancy in hardware.

(Embodiment) FIG. 1 is a block diagram of main parts of a microprocessor according to an embodiment to which the present invention is applied.

In the microprocessor of this example, a total of two condition flags are provided as final condition flags: Z (zero) indicating equality, and Z (res) indicating magnitude relationship.

an arithmetic unit 2 that executes operations on two pieces of data; and 1 that holds two pieces of data that are operated on by this arithmetic unit 2;
There are two operand data registers 1, a and 1b.

There is also an operation result register 3 in which numerical data as a result of the operation is stored, and an intermediate flag 4 for the operation result.

Reference numeral 5 is an instruction register in which signed or unsigned operation instructions for executing operations are stored. Reference numeral 6 denotes a decoding circuit, which determines whether an arithmetic instruction, etc. stored in the instruction register 5 belongs to a signed instruction group or an unsigned instruction group.

The above discrimination information by this decoding circuit and the intermediate flag 4
A flag generation circuit 7 is provided which generates a final condition flag from the flag condition of the operation result held in the flag condition and the operation result data. Two condition flags 8 are provided, which are output from the flag generating circuit 7 and include a response (Res) 8b indicating a magnitude relationship and a Z (zero) 8a indicating that the operand data are equal.

FIG. 2 is an explanatory diagram showing a comparison between two condition flags 8, Z (zero) 8a and L (less) 8b, and the magnitude relationship of the calculation results in this embodiment.

When the 2 flag 8a is 1, it indicates that the data held in the two operand data registers 1a and 1b (their respective values are A and B) are equal once. Further, when the 2 flag 9b is 0, it can be seen that the two data A and B are not equal.

Furthermore, the magnitude relationship between these two data A and B is always as shown in FIG. 2, regardless of whether the data has a sign or not.
This can be determined by looking at the L flag.

In this way, regardless of whether the data being handled is signed or unsigned, the meaning of the condition flag is always the same.
Appropriate flag changes are generated according to the type of operation instruction. Furthermore, the types of condition flags have been reduced from the conventional three types to only two types in this example. Therefore,
This not only reduces the amount of hardware surrounding the flag, but also makes it possible to more carefully select the types of instructions, such as branch instructions, related to the condition flag.

Note that the internal configuration of the flag generation circuit 7 is as follows, for example:
By storing the same condition flags as the conventional N1, Z, and C in the intermediate flag 4, the condition flags shown on the left and right of the combination of condition flags in Fig. It may also be configured by a gate or the like that executes the judgment. Alternatively, it is also possible to directly extract the N flag etc. from the calculation result data. Of course, it is not necessary to construct the gates according to the logic shown in FIG. 4, and it can be easily realized by combining gates of simpler forms.

In addition, although the above-mentioned embodiment configuration shows an application example of the present invention in the simplest form, it is not limited to the configuration as in the above example. Of course, the present invention can also be applied to numerical data such as real number format.

[Effects of the Invention] As described above in detail, according to the microprocessor according to the present invention, the meanings of condition flags can always be the same regardless of whether a signed operation or an unsigned operation is performed. It becomes like this.

Therefore, even when determining the calculation result and executing instructions such as conditional branching, it is possible to always use the same conditional branching instruction, etc., regardless of the presence or absence of the sign of the target data. It becomes possible to make it difficult for f< etc. to occur and to improve the efficiency of development, etc.

Further, the types of condition flags can be reduced by applying the present invention, and it is also possible to reduce the amount of hardware related to flags and to carefully select the types of condition judgment instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a microprocessor according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of condition flags in the same embodiment, FIG. 3 is a block diagram of main parts of a conventional microprocessor, and FIG. The figure is an explanatory diagram of a conventional condition flag.

Claims (1)

[Claims] (1) A microprocessor that executes operations between multiple pieces of data that may or may not have signs using an arithmetic unit, and outputs condition flags such as size and match, which are the comparison results between the multiple pieces of data, along with the operation result data. A processor, which includes a group of signed operation instructions that are instructions for executing operations on signed data that has a positive or negative sign, a group of unsigned operation instructions that are instructions for executing operations on unsigned data that does not have a positive or negative sign, and an operation instruction. a decoding circuit that determines whether an instruction belongs to a signed arithmetic instruction group or an unsigned arithmetic instruction group and outputs determination information, and an arithmetic unit that executes the determination information from this decoding circuit and the operation. A flag generation circuit that outputs condition flags such as size and match, including positive and negative signs, based on the information on the calculation result if the data is signed data, and outputs the condition flags that do not include the sign if it is unsigned data. A microprocessor characterized by comprising: