JPS59148432A - Counter device - Google Patents

Abstract

PURPOSE:To reduce the number of wirings and elements by detecting all outputs of a unit stage to be reduced to logical 1 and an output of the unit stage closer to the MSB in the unit stages to be reduced to logical 0 in binary outputs detected by a binary up-counter. CONSTITUTION:Assuming that a level of a set terminal is logical H before a time t0 and a preset data (111000) is set to each unit stage; then an output level of an NAND gate 15 goes also to H. When the level of the set signal moves to L at the time t0, the binary up-counter counts a clock signal. When the binary output of the counter goes to (001011), the detected gate output goes to L and further, when the binary output goes to (001100), the detected gate output goes to H and the detection is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a counter device that can be used to detect a predetermined combination of binary outputs of a binary counter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Conventional Structure and Problems The conventional counter device will be described below with reference to the drawings. FIG. 1 is a block diagram of a conventional counter device, in which unit stages 1.2, 3, 4.degree. 6.6 are connected in cascade to form a binary up counter. terminal 7,
Reference numerals 8, 9, 10, 11 and 12 are program terminals to which the program values of each bit are applied, terminal 13 is a clock signal input terminal, terminal 14 is a cent terminal, and terminal 15 is a count value detection output terminal. The gate 16 is a NAND gate that detects that the binary outputs of the counters have become a predetermined combination, and the outputs of each unit stage are connected as gate inputs according to the binary outputs to be detected.6 The gate 16 is configured as described above. Regarding the conventional counter device,
Its operation will be explained below. For example, if the program value is a binary number [111000], up-counting is performed from this value, and when the output of the counter reaches the detection value [001011], the detection gate 16 generates an output signal, and the detection gate 16 generates an output signal. This means that the desired count value has been detected.

However, in the above configuration, all the outputs of each unit stage are used to detect when the counter has reached a predetermined binary output, so the input terminals of the gate 16 are required as many as the number of stages of the counter, and A similar number of wires are also required to connect each unit stage and the input terminal of the detection gate. In particular, if there are multiple binary outputs to be detected, the number of wires is calculated using the following formula: Number of wires - (number of counter stages) x (binary to be detected -
The number of outputs (output number) is required, and when added to the integrated circuit, it becomes difficult to configure a detection gate with only multi-input gates, and a gate circuit with a multi-stage configuration as shown in FIG. 2 is required. Therefore, the number of elements required for detection increases, and the delay time from when the output of the counter becomes a binary output to be detected until the detection gate outputs a detection signal also increases.

OBJECTS OF THE INVENTION An object of the present invention is to provide a counter device that can detect a binary output value of a counter with a smaller number of wires and elements.

Structure of the Invention The counter device of the present invention uses a flip-flop having a set function as a unit stage, and the unit stage is N.
(N is the number of counter stages, N>2) binary up counters are connected in cascade, and in the binary output to be detected of the binary up counter, all outputs of unit stages that become 1 are supplied. , 0, M pieces (
M is the number of unit stages that output 0, and L is the number of unit stages that output 0, including the unit stage near the MSB (most significant stage) among the unit stages (N2M>1). Number of unit stays 7 supplied to the gate, 1<:
It is constructed of a detection gate to which the output of the L(M) unit stage is supplied, thereby reducing the number of wires and elements required for detection.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows a block configuration of a counter device according to an embodiment of the present invention. In FIG. 3, unit stages 1.2.3.4.5.6 are cascaded to form a binary
It constitutes an up counter. 7, 8, 9, 10, 1
1.12 is a program terminal to which the program value of each bit is applied, 13 is a clock signal input terminal, 14 is a set terminal, and 16 is a count value detection output terminal. 1
6 is a NARD gate that detects the binary output of the counter, and when the binary value [0Q1011] to be detected is output to the input terminal of the NAND gate, "
All the non-inverting outputs of the unit stages that become "1" and the inverting outputs of the MSB unit stage among the unit stages that become "0" are connected.

Now, FIG. 4 is a time chart for explaining the circuit operation of FIG. 3, and the circuit operation of FIG. 3 will be explained with reference to FIG.

13a in FIG. 4 is a clock signal waveform supplied to the clock signal input terminal 13, which is IQ, 2Q.

3Q, 4Q, sQ, and eQ are the non-inverted outputs of unit stages 1.2, 3, 4, and 6.6, respectively. Further, 14a in FIG. 4 is a set signal waveform supplied to the set terminal 14, and 15a is an output waveform of the detection gate 15.

When the circuit in Figure 3 is busy, the level of the cent terminal is HI+ before time to, and the preset data is stored in each unit stage.
111oOQ] is cented, then HAN
The output level of the D gate 16 is also HI+.

When the level of the set signal changes from "H" to "L" at time to, the binary up counter counts the clock signal.

At time t1, the binary output of the counter becomes [0O1
011], the output level of the detection gate 16 becomes “L”.
" level and outputs a detection signal. At time t2, when the binary output of the counter becomes [o01100], the output level of the detection gate 16 becomes "HI+ level", indicating that detection has ended. Similarly to the above, the output of the detection gate 16 goes to L'' level at times H, ts, and t7 because there are unit stages that do not detect the output, and at time t.
4. t6. It becomes H'' level at t8. Therefore, the detection gate 16 outputs the detection signal four times, and also outputs the detection signal for binary output values other than the binary output value to be detected.

However, after data is preset in the binary up counter, the detection gate 16 first outputs a detection signal at time t1, and the binary output of the binary up counter at that time is the binary value to be detected. It has become. Therefore, since the first detection signal output is the binary output that should be detected by the binary up counter, there is no practical problem when performing sequential operations based on the output of the detection gate. does not occur at all.

Effects of the Invention As is clear from the above description, the present invention provides a binary up counter in which a flip-flop having a set function is used as a unit stage, and N unit stages (N>2) are connected in cascade; - At the binary output of the up-counter to be detected, all outputs of the unit stage which are 1 are supplied, and M which are 0 (M>1
) among the unit stages near the MSB, it is composed of detection gates to which the outputs of L (1≦L(M)) unit stages are supplied, including the unit stage near the MSB. An excellent effect can be obtained in that the number of wires required for output detection is small, and the number of elements required for detection is also small.In addition, the effect is that the delay time that occurs during detection can also be reduced. is obtained.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a conventional counter device, FIG. 2 is a specific circuit configuration diagram of the main part of FIG. 1, FIG. 3 is a block configuration diagram showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the circuit operation of FIG. 3. FIG. 1~ra...unit stage, 7~12...
・Program terminal, 13... Clock signal input terminal, 14... Set terminal, 16...
Detection signal output terminal, 16...Detection gate. Name of agent: Patent attorney Toshio Nakao and one other person
Figure 1

Claims (2)

[Claims] (1) A flip-flop having a set function is used as a unit stage, and N unit stages (however, N
〉2) Pinary asoph counters connected in cascade,
In the binary output of the binary up counter to be detected, all the outputs of the unit stages which become 1 are supplied, and among the y unit stages (where M>1) which become 0, the highest stage A counter device comprising a detection gate to which outputs of L unit stages (where 1≦L(M)) including the unit stage near the MSB (MSB) are supplied. (2) In the binary output to be detected by the binary up counter, all the inverted outputs (or non-inverted outputs) of the unit stage that become 1 are supplied, and the non-inverted outputs (or inverted outputs) of the unit stage that become 0 are supplied. ) The counter device according to claim 1, wherein the detection gate is constituted by an AND gate to which .