JP3338722B2 - Counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit, and more particularly to a counter circuit built in a chip microcomputer for counting an external clock signal input.

[0002]

2. Description of the Related Art In recent years, the application fields of microcomputers have been rapidly expanding, and microcomputers are being used in various fields. In particular, recently, in the fields of OA, FA, and the like, it is increasingly used for controlling a motor that drives an object. When used for controlling such a motor, a microcomputer including hardware suitable for controlling the motor is required.

In general, as shown in FIG. 6, a microcomputer 24 has a microcomputer 25 and a CPU 26 corresponding to an external circuit 28.
And a peripheral control circuit 27. The CPU 26 performs arithmetic processing in accordance with instructions stored in the memory 25, and performs various control signals and status signal input / output operations by the peripheral control circuit 27. , The external device 28 is controlled. The present invention relates to a counter circuit that counts pulse signals input from an external device 28 to the microcomputer 24. Hereinafter, a conventional example of the counter circuit will be described.

FIG. 7 is a diagram showing the configuration of a conventional counter circuit of this type, and is an example in which the number of data bits is eight. As shown in FIG.
Data bus 201, bus 202 and counter bus 20
3, transfer gates 2 and 6, each having a bus connection function to bus 202 and counter bus 203, compare registers 3 and 4, inverter 5, counter 7, and clear, respectively. It comprises a circuit 29, an incrementer 9, and a read / write control circuit 10. FIG. 8 is a diagram showing the internal configuration of the incrementer 9 and the clear circuit 29 in the conventional example. The incrementer 9 includes adders 22 _-0 , 22 _-1 ,... 22 _-7 , and the clear circuit 29 includes an AN corresponding to an 8-bit value.
D circuits 19 _-0 , 19 _-1 ,..., 19 _-7 and 30;
Similarly, transfer gates 20 _-0 , 20 _-1 ,..., 20 _-7 and 21 _-0 , each corresponding to an 8-bit value,
20 _-1 ,..., 21 _-7 , OR circuit 31, inverters 17 and 32, RS flip-flop 33, D
And a latch 34. Incidentally, the adder 22 _-0 and the adder 22 _-1 constituting the incrementer 9 are each adder corresponding to the least significant bit and the next higher-order bit, adder 22-7 corresponds to the most significant bit It is an adder. The description of the adders corresponding to the other bits is omitted. 9 (a), 9 (b),
(C), (d), (e), (f), (g), (h),
(I) and (j) are timing charts showing the operation state of the conventional example.

In FIG. 7, an address signal 106, a read signal 107, and a write signal 108 output from the CPU 26 (see FIG. 6) are provided by an OR circuit 1 and a read / write control circuit of the counter circuit included in the peripheral control circuit 27. 10 is input. Read / write control circuit 10
Receives input of these address signal 106, read signal 107 and write signal 108, selection signals 109, 110, 111 and 112 are generated and output, and selection signals 109 and 110 are input to compare register 3. , Select signals 111 and 112 are input to the compare register 4. In addition, the OR circuit 1 receives the input of the read signal 107 and the write signal 108, and outputs a “1” level in both cases of reading and writing, and inputs the “1” level to the gate of the transfer gate 2. You. As a result, the transfer gate 2 is turned on, and the data bus 201 is connected to the compare registers 3 and 4 via the transfer gate 2 and the bus 202. In this state,
The value of each compare register is read out via the data bus 201, or the data on the data bus 201 is written into each compare register.

When the system clock 101 is at the "0" level, the "1" level is input to the gate of the transfer gate 6 via the inverter 5, and the counter is then turned on via the transfer gate 6 and the counter bus 203 which are turned on. The count value at 7 is input to compare registers 3 and 4, where the written data is compared with the count value at counter 7. When the comparison results in compare registers 3 and 4 match, match signals 105 and 104 are output, respectively, and output to CPU 26 (see FIG. 6) as interrupt request signals, respectively. The coincidence signal 104 is also input to the clear circuit 29 as a clear signal.

The counter 7 holds an 8-bit value, and the value is input to a clear circuit 29. When the external clock signal 103 is at “1” level, the increment is incremented (+1) by the incrementer 9 and the clear circuit 2
When the external clock signal 103 is at the "0" level, the increment is not performed. The system reset signal 10 is applied to the clear circuit 29.
When 2 is input, or when the match signal 104 is output from the compare register 4 and input to the clear circuit 29 as a clear signal, the value written back to the counter 7 is forcibly cleared to “00H”. Is done.

Next, the internal configuration of the incrementer 9 and the clear circuit 29 shown in FIG. 8 and FIGS.
(C), (d), (e), (f), (g), (h),
The operation related to increment and clear of the counter value will be described with reference to the timing chart of (i). In FIG. 8, the circuit configuration of the portion corresponding to each bit in the incrementer 9 and the clear circuit 29 is the same, and the circuits of the portion corresponding to each bit all perform the same operation. In the following description, the operation will be described only for the circuit corresponding to the least significant bit.

The external clock signal 103 is input to the A terminal of the adder _22-0 corresponding to the least significant bit included in the incrementer 9, and during the period of the "1" level of the system clock signal 101, The least significant bit Q ₀ is input to the B terminal via the transfer gate _21-0 which is turned on. In the adder 22 _-0 is performed the addition of the external clock signal 103 and the least significant bit Q _0, is output from the Q terminal of the added value is AN
It is input to the D circuit _19-0 . In this case, if there is a carry is "1" level is outputted from the CY terminal is inputted to the A terminal of the next higher bit adder 22 _-1, adder corresponding to the next significant bit It is input to the a terminal of the 22 _-1 and adding a bit Q ₁ is performed by a similar procedure. Hereinafter, similarly, for each bit including Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q _6, and Q ₇ corresponding to the counter bus 203, the carry output from the corresponding lower-order bit and Are added.

On the other hand, the system reset signal 10
2 and the clear signal 104 are input to the OR circuit 31, and when either of the system reset signal 102 or the clear signal 104 becomes "1" level, "1" is output.
The level signal is output and input to the R terminals of the inverter 32 and the RS flip-flop 33. The output of the inverter 32 is input to the AND circuit 30, and
In the circuit 30, the logical product of the output of the inverter 32 and the external clock signal 103 is obtained, and the output is R
The signal is input to the S terminal of the S flip-flop 33. Also,
The system clock signal 101 is inverted by the inverter 17 and input to the C terminal of the RS flip-flop 33, and at the same time, the transfer gates 20 _-0 , 20 _{-1 ,.}
..., it is also input to the gate of the 20 _-7.

It is now assumed that "00H" is written in the compare register 4. In the period up to stage A shown in FIG. 9A, since the system reset signal 102 is at the “1” level, the OR circuit 3
A “1” level system reset signal 102 is output from “1” and input to the R terminal of the RS flip-flop 33. As a result, the RS flip-flop 33 is reset, and the Q terminal output signal 116 is output at the “0” level. The Q terminal output signal 116 is _supplied to the AND circuits 19 _-0 , 1
9 _-1 ,..., 19 _-7 ,
The outputs of the D circuits all become "0" level. Therefore, during the system reset period, each bit Q0, Q1,.
,..., Q7 are all output "00H" and the value of the counter 7 is initialized to "00H".

Next, in the stage A, it is assumed that the system reset signal 102 has changed from "1" level to "0" level. In this case, since both the system reset signal 102 and the clear signal 104 are at “0” level, a signal of “0” level is output from the OR circuit 31 and input to the R terminal of the RS flip-flop 33. At the same time, a “1” level signal is input to the AND circuit 30 via the inverter 32. FIG. 9 (a)
In the stage A, since the external clock signal 103 is at the "0" level, the output signal of the AND circuit 30 remains at the "0" level and remains unchanged. However, in stage B, since the external clock signal 103 changes to “1” level,
The output signal of the D circuit 30 becomes “1” level, and the “1” level is input to the S terminal of the RS flip-flop 33. In the stage B of FIG. 9, when the system clock signal 101 becomes “0” level,
The Q terminal output signal 116 of the S flip-flop 33 becomes “1” level and is input to the D latch 34. The system clock signal 101 is connected to the C terminal of the D latch 34.
Are inverted by the inverter 17 and input.
In the state where the system clock signal 101 is at the “1” level in stage C, the D latch 34 is at the “1” level. However, in stage B,
Since the D latch is still at the "0" level, the Q output signal of the D latch 34 is output at the "0" level, and AND circuits 19 _-0 , 19 _-1 ,...
_-7 is entered. Therefore, although the first external clock signal 103 is input in the stage B, the value of the counter 7 remains "00H" and the count is not performed.

Next, assuming that the next external clock signal 103 has been input at stage D, the Q terminal output signal of D latch 34 is at the "1" level at this time. At the timing when the system clock signal 101 is at the “0” level, the external clock signal 1 in the adder _22-0 is output.
03 and bit Q ₀ are added to the AND circuit 1
9 through _-0 and transfer gate 20 _-0, output as bits Q _0, "00H" is written back to the counter 7. Thereafter, the counter 7 counts up in the same manner.

In the stage F, the value of the counter 7 becomes "0".
When the signal becomes 2H, the match signal (clear signal) 104 is output from the compare register 4 at the timing when the system clock signal 101 becomes "0" level.
The system clock signal 101 of the stage F is “0”
At the timing of the level, it is input to the R terminal of the RS flip-flop 33. As a result, the Q terminal output signal 116 of the RS flip-flop 33 becomes “0” level. System clock signal 101 in stage G
Is at the "1" level, the Q terminal output of the D latch 34 is at the "0" level, and the AND circuit 1
9 _-0 , 19 _-1 ,..., 19 _-7 , whereby the outputs of these AND circuits are supplied to the corresponding adders 22-0, 2
..,..., Regardless of the addition result output from 22-7. Further, in stage H, in the timing of the system clock signal 101 is "0" level, the transfer gate 20 _- 0,2
0 _-1, ........., the 20 _-7 gate of a state in which each "1" level is inputted, thereby, each of these transfer gates, all become on, the above AND circuit 19 _{- 0,} 19 _-1, ........., "0" level output of 19 _-7, bit Q ₀ through respective transfer gates, Q _1, ............, it is outputted as a Q _7. Therefore, at the timing when the system clock signal of the stage H becomes “0” level, the counter 7 is initialized to “00H”.

As described above, in the counter 7, the number "n-1" obtained by subtracting 1 from the number "n" to be counted is written in the compare register 4, so that each time an external clock signal is input, 0, 1, 2, ...
(N-1), 0, 1, 2,..., Etc., the counting operation of counting up / clearing is repeatedly performed at a cycle of n.

On the other hand, when a match signal (clear signal) 104 is generated from the compare register 4 in the stage F,
As described above, it is sent to the CPU 26 (see FIG. 6) as an interrupt request signal. When the CPU 26 detects that the external clock signal 103 has been input a predetermined number of times, a predetermined control action is performed on the external device (see FIG. 6) 28. For example, in the HDD servo control, processes such as recognizing the number of sectors by an external clock and stopping the motor when a predetermined number of sectors are counted are performed.

[0017]

In the above-described counter circuit built in the one-chip microcomputer, when the value of the counter 7 matches the set value of the compare register 4, the next count is performed each time. At the up timing, the value of the counter 7 becomes “00”.
Therefore, in this case, the value of the counter 7 “00H” is “1” when the external clock signal 103 is “1”.
This means that it has been entered twice. Further, the value of the counter 7 is initialized to “00H” by the system reset signal 102. In this case, the value of the counter 7 “00”
H ”means that the external clock signal 103 is not input.

For this purpose, the value of the counter 7 is
When the read value is “00H” when the read is performed, the external clock signal 1
It is impossible to determine whether the value is a value obtained when 03 is input or a value obtained when an external clock signal has not yet been input immediately after initialization by the system reset signal 102, by only software processing. There is a disadvantage that it is.

[0019]

According to a counter circuit of the present invention, in a counter circuit incorporated in a one-chip microcomputer, counting is performed based on a supplied clock signal, and the value of the held data is determined through the counting. Receiving one or more counters that are sequentially updated, and the value of the updated held data output from the counter,
Performs comparison and comparison with the value of its own held data, and when the values of both data match, a compare register that outputs a predetermined match signal; and receives the match signal and receives the value of both data in the compare register. Immediately after the occurrence of a match, an initial control operation is performed such that the value of the data held in the counter is initialized to a state where it is advanced by one count from the value of the initial state in response to the input of the clock signal supplied first. And a conversion control circuit.

[0020]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, the present embodiment corresponds to a data bus 201, a bus 202, and a counter bus 203, and an OR circuit 1 and a transfer circuit having a bus connection function for the bus 202 and the counter bus 203, respectively. Gates 2 and 6 and compare registers 3 and 4
, An inverter 5, a counter 7, and an initialization control circuit 8
, Incrementer 9 and read / write control circuit 10
And is provided. FIG. 2 is a diagram showing the internal configuration of an incrementer 9 and an initialization control circuit (first embodiment) 8 in the conventional example.
_Are the adders 22 _-0 , 22 _-1 ,... Corresponding to the 8-bit value.
, 22 _-7 , and the initialization control circuit 8 outputs AND circuits 19 _-0 , 19 _-1 ,...
Transfer gates 20 _-0 , 20 ₋₁ ,..., 2 corresponding to 8-bit values, similarly to 19 _-7 and 18
0 _-7 and 21 _-0, 20 _-1, ........., 21 _-7, and inverters 11, 12, and 16 and 17, and includes a D latch 13 and 14, a NOR circuit 15. Incidentally, the adder 22 _-0 and the adder 22 _-1 constituting the incrementer 9, as in the case of the conventional example, are each adder corresponding to the least significant bit and the next higher-order bit,
The adder _22-7 is an adder corresponding to the most significant bit.
The description of the adders corresponding to the other bits is omitted. 3 (a), (b), (c),
(D), (e), (f), (g), (h), (i) and (j) are timing charts showing the operating state of the present embodiment.

In FIG. 1, as in the case of the conventional example, C
Address signal 10 output from PU 26 (see FIG. 6)
6, the read signal 107 and the write signal 108 are output to the OR circuit 1 of the counter circuit included in the peripheral control circuit 27.
And input to the read / write control circuit 10. In the read / write control circuit 10, these address signal 106, read signal 107 and write signal 108
, The selection signals 109, 110, 111 and 112 are generated and output. The selection signals 109 and 110 are input to the compare register 3 and the selection signals 11 and
1 and 112 are input to the compare register 4. In addition, the OR circuit 1 receives the input of the read signal 107 and the write signal 108, and outputs a “1” level in both cases of reading and writing, and inputs the “1” level to the gate of the transfer gate 2. You.
As a result, the transfer gate 2 is turned on,
Data bus 201 includes transfer gate 2 and bus 2
02 is connected to the compare registers 3 and 4. In this state, the value of each compare register is read out via the data bus 201, or the data on the data bus 201 is written to each compare register.

When the system clock 101 is at the "0" level, the "1" level is input to the gate of the transfer gate 6 via the inverter 5 and thereby turned on, so that the counter is supplied via the transfer gate 6 and the counter bus 203. The count value at 7 is input to compare registers 3 and 4, where the written data is compared with the count value at counter 7. Compare register 3
When the comparison results in steps 4 and 4 match, match signals 105 and 104 are output, respectively, and output to the CPU 26 (see FIG. 6) as interrupt request signals. The coincidence signal 104 is also input to the initialization control circuit 8 as a clear signal.

In FIG. 2, when the match signal (clear signal) 104 output from the compare register 4 is at "0" level, a "1" level signal is output to the AND circuit 18 via the D-latches 13 and 14 and the inverter 16. When the system clock signal 101 is input at the “1” level, the transfer gate _21-0 is turned on. As a result, the bit Q ₀ is input to the AND circuit 18 via the transfer gate _21-0 , the bit Q ₀ is output as the output signal 115 of the AND circuit 18, and is input to the B terminal of the adder _22-0. You. On the other hand, adder 2
The 2 _-0 A terminal, which is input an external clock signal 103, the adder 22 _-0 are summed and these external clock signal 103 and the bit Q ₀ is the addition result is Q terminal output signal And input to the AND circuit _19-0 . Note that if the addition result is Carry "1" from the CY pin level is output, is input to the A terminal of the adder 22 _-1 corresponding to the next higher-order bit. If the other system reset signal 102 is input at "0" level is inverted by "1" level signal is inputted to the AND circuit 19 _-0 by the inverter 12, the above-mentioned Q terminal of the AND circuit 19 _-0 An output signal is output. Also when the system clock signal 101 is "0" level is inverted by the inverter 17, "1" level signal is input to the gate of the transfer gate 20 _-0, and thereby the transfer gate 20 _-0 on state It is to be outputted as an addition output Ha bit Q ₀ of the adder 22 _-0.

The system reset signal 102 is set to NO
The clear signal 104 is also input to the R circuit 15,
Similarly, NOR circuit 15 is provided via D latches 13 and 14.
Has been entered. Therefore, the system reset signal 10
When either one of the clear signal 104 and the clear signal 104 becomes "1" level, the output of the NOR circuit 15 becomes "0" level, and when both become "0" level, the output of the NOR circuit 15 becomes "1" level. Become.

Next, the internal structure of the incrementer 9 and the initialization control circuit 8 in FIG. 2 and FIGS.
(C), (d), (e), (f), (g), (h),
The operation related to increment and clear of the counter value will be described with reference to the timing chart of (i). Note that the circuit configuration of the part corresponding to each bit in the incrementer 9 and the initialization control circuit 8 is the same, and all the same operations are performed. Therefore, in the following description, the part corresponding to the least significant bit will be described. The operation will be described only for the circuit.

Up to the stage P in FIG. 3A, the system reset signal 102 is at "1" level.
The output signal of the NOR circuit 15 is output at the “0” level and input to the AND circuits 19 _-1 ,..., 19 _-7 .
Further, since the system reset signal 102 is at the “1” level, the inverted output of the inverter 12 is input to the AND circuit _19-0 at the “0” level. Therefore, in this case, the added outputs from the adders _22-0 , _22-1 ,..., _22-7 are output to the corresponding AND circuits _19-0 , 1
Blocked at 9 _-1 ,..., 19 _-7 . Therefore, during the system reset period, bits Q0, Q1,.
.., Q7 are all output "00H", and the counter 7 is initialized to "00H".

Now, it is assumed that in the stage P, the system reset signal 102 has changed from "1" level to "0" level. In this case, the system reset signal 1
02 and the clear signal 104 are both at the “0” level, so that the signal 114 output via the D latches 13 and 14 is also at the “0” level, and the NOR circuit 15
Outputs a signal of “1” level from the AND circuit 1
9 _-1 ,..., 19 _-7 are input. On the other hand, the inverted output of the system reset signal 102 by the inverter 12 is input to the AND circuit _19-0 at "1" level.
Therefore, in this case, the adders 22 _-0 , 22 _-1 ,...
.., 22 _-7 are directly output from the AND circuit 19 _-0 ,
19 _-1 ,..., 19 _-7 and transfer gate 20
_-0, 20 _-1, ........., via 20 _-7, respectively bits Q _0, Q _1, ........., is outputted as Q _7. And
In stage Q, to the external clock signal 103 becomes "1" level, the output of the adder _{22-1 0} becomes "1" level, the counter 7 is written back is "01H". That is, in the present embodiment, the counter 7 counts up in response to the input of the first external clock signal 103 after the system reset. Hereinafter, in the same manner, the counter 7 sequentially counts up.

At the stage U, the value of the counter 7 becomes "0".
When the system clock becomes 3H, the match signal (clear signal) 104 is output from the compare register 4 at the timing when the system clock is "0", latched by the D latch 13, and the stage V receives the external clock signal 103 at the stage V. At the falling timing, the signal is latched by the D latch 14. The output signal 114 of the D latch 14 is output at "1" level and input to the NOR circuit 15. Therefore, the NOR circuit 15 outputs "0" level. The signals are output, and the outputs of the AND circuits 19 _-1 ,..., 19 _-7 are all at the "0" level. , The “0” level corresponds to bits Q ₁ ,..., Q ₇
Is output as

In the stage W, the D latch 1
4 is output from the inverter 16
And input to the AND circuit 18. As a result, the "0" level is output from the AND circuit 18, and
It is input to the B terminal of the adder _22-0 . In the adder _22-0 , the external clock signal 10 input to the A terminal is output.
3 and the “0” level input to the B terminal are added,
The “1” level is output from the Q terminal. In this case, since the system reset signal 102 is at the “0” level and the system clock signal 101 is also at the “0” level, “1” output from the Q terminal of the adder _22-0 is output.
Level through the AND circuit 19 _-0 and the transfer gate 20 _-0, is outputted as the bit Q _0. Also,
“01H” is written back to the counter 7 at the falling edge of the system clock signal 101 in the stage W.

That is, after the system reset is released or after the value of the compare register 4 matches the count value of the counter 7, the counter 7 starts counting up from the first input of the external clock signal 103. Thereafter, each time the external clock signal 103 is input, the counter 7 continues counting up. Thus, the number "n" to be counted
Is written in the compare register 4 so that the counter 7 counts up and clears in the cycle of n every time the external clock signal 103 is input, such as 1, 2, 3,... It is performed repeatedly. In this case, when the external clock signal 103 is input at “00H” only after the system reset is released, the counter 7 always has a value of “01H” or more. As a result, the counter 7 reads “0”.
If so, it is determined that the external clock signal 103 has never been input.

Next, a second embodiment of the present invention will be described. A block diagram showing the configuration of this embodiment is the same as that of the first embodiment, and is as shown in FIG. This embodiment is different from the first embodiment in that FIG.
In the internal configuration of the initialization control circuit shown in FIG.

FIG. 4 is a diagram showing the internal configuration of an incrementer 9 (same configuration as in the first embodiment) 9 and an initialization control circuit (second embodiment) 8 in this embodiment. Adder _22-0 corresponding to the 8-bit value, 2
2 _-1, ........., is composed of 22 _-7, the initialization control circuit 8, the AND circuit 19 _-0 corresponding to 8-bit values, 1
_9-1, ........., 19 _-7, likewise, the transfer gate 20 _-0 corresponding to each 8-bit value, 20 _-1, ...
…, 20 _-7 and 21 ₋₀ , 20 ₋₁ , ………, 21
_-7 , OR circuit 23 corresponding to bit Q ₀ , inverters 11 and 17, D latches 13 and 14, NO
An R circuit 15 is provided. FIG. 5A,
(B), (c), (d), (e), (f), (g),
(H), (i), (j) and (k) are timing charts showing the operating state of the present embodiment.

In the initialization control circuit 8 of this embodiment shown in FIG. 4, although there is a slight difference in the logic circuit configuration for taking in the system reset signal 102 and the coincidence signal (clear signal) 104, each stage has A system clock signal 101 input to the initialization control circuit 8,
System reset signal 102, external clock signal 103
The operation function of the initialization control circuit 8 corresponding to the incrementer 9 according to each input level of the coincidence signal 104 is the same as that of the first embodiment.

For example, in FIGS. 1, 4 and 5,
Considering bit Q ₀ (the same applies to the other bits, the description is omitted). In stage j, the value “03H” is held in the compare register 4, and
When a value of “03H” is input as a count value from the counter 7, the match signal (clear signal) 104 is output at the “1” level from the compare register 4 and input to the initialization control circuit 8. . In this case, in stage j, the output signal 114 of the D latch 14 is at the “0” level, and is input to the OR circuit 23 and the NOR circuit 15. Therefore, the output level of the NOR circuit 15 is still "1".
In the state of the level, the signal of the “1” level is AN
It is input to the D circuit _19-0 . In this stage j,
During a period in which the system clock signal 101 is at the “0” level, the transfer gate _20-0 is turned on, and the addition output of the adder _22-0 is output to the AND circuit _19-0 ,
It is output as a bit Q ₀ via the OR circuit 23 and the transfer gate _20-0 .
As shown in (k), “01H” is written back to the counter 7 at the fall of the system clock signal 101 in the stage 1.

That is, as in the case of the first embodiment, after the system reset is released or after the value of the compare register 4 matches the count value of the counter 7, the input of the first external clock signal 103 is performed. From the time point, the counter 7 starts counting up. Thereafter, each time the external clock signal 103 is input, the counter 7 continues counting up. By writing the number “n” to be counted in the compare register 4 in this way, every time the external clock signal 103 is input, the counter 7 outputs 1, 2, 3,... , N, the count up and the clear are repeated. In this case, when the external clock signal 103 is input at “00H” only after the system reset is released, the counter 7 always has a value of “01H” or more. As a result, if the reading is “0” in the counter 7, it is determined that the external clock signal 103 has never been input.

In the above description of the operation of the first and second embodiments of the present invention, the contents of the counter 7 are initialized to "00H" by a system reset and "01H" is input by the input of an external clock signal. Although the counter circuit to be added is described, the present invention is also applied to a counter circuit which is initialized to “n” by a system reset and subtracts “01H” from the counter content by an external clock signal input. It is needless to say that the same effect can be obtained by initializing to "n-1" at the next count timing when a match occurs.

[0038]

As described above, the present invention is applied to the counter circuit built in the conventional one-chip microcomputer, and the count-up operation is necessarily performed in response to the input of the external clock signal. By providing the initialization control circuit for controlling the external clock signal, the presence or absence of the input of the external clock signal can be determined by extremely simple software processing for reading the counter value.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of an incrementer and an initialization control circuit included in the embodiment.

FIG. 3 is an operation timing chart of the one embodiment including the first embodiment of the initialization control circuit.

FIG. 4 is a circuit diagram showing a second embodiment of an incrementer and an initialization control circuit included in the one embodiment.

FIG. 5 is an operation timing chart of the one embodiment including the second embodiment of the initialization control circuit.

FIG. 6 is a system configuration diagram of a general microcomputer.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a circuit diagram showing an incrementer and a clear circuit included in the conventional example.

FIG. 9 is an operation timing chart of the conventional example.

[Explanation of symbols]

1, 23 OR circuit 2,6,20 _-0 to 20 _-7, 21 _-0 to 20 _-7 transfer gates 3 and 4 compare register 5,11,12,16,17,32 inverter 7 counter 8 initialization control circuit REFERENCE SIGNS LIST 9 incrementer 10 read / write control circuit 13, 14, 34 D latch 15 NOR circuit 18, 19 _{−0 to} 19 ₋₇ , 30 AND circuit 22 _{−0 to} 22 ₋₇ adder 23, 31 OR circuit 24 microcomputer 25 Memory 26 CPU 27 Peripheral control circuit 28 External device 29 Clear circuit 33 RS flip-flop

Claims (1)

(57) [Claims] 1. A counter circuit incorporated in a one-chip microcomputer, wherein counting is performed based on a supplied clock signal, and a value of a single or a plurality of counters is sequentially updated through the counting. And receiving the updated value of the retained data output from the counter, performing comparison and collation with the value of the retained data,
A compare register that outputs a predetermined coincidence signal when the values of both data coincide with each other; and receiving the coincidence signal, the clock supplied first after the occurrence of the coincidence of the values of both data in the compare register. And an initialization control circuit that performs a control operation so as to initialize the value of the data held in the counter by one count from the value of the initial state in response to the input of the signal. Counter circuit.