JPS59145083U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS59145083U
JPS59145083U JP1983039187U JP3918783U JPS59145083U JP S59145083 U JPS59145083 U JP S59145083U JP 1983039187 U JP1983039187 U JP 1983039187U JP 3918783 U JP3918783 U JP 3918783U JP S59145083 U JPS59145083 U JP S59145083U
Authority
JP
Japan
Prior art keywords
integrated circuit
heat sink
conductive path
hybrid integrated
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983039187U
Other languages
Japanese (ja)
Other versions
JPH0351992Y2 (en
Inventor
風見　明
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1983039187U priority Critical patent/JPS59145083U/en
Publication of JPS59145083U publication Critical patent/JPS59145083U/en
Application granted granted Critical
Publication of JPH0351992Y2 publication Critical patent/JPH0351992Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Mounting Components In General For Electric Apparatus (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を説明する上面図、第２図は第１図の■
−■線断面図、第３図は来者禽を説明する上面図、第４
図は第３図のＩＶ−ＩＶ線断面図である。 主な図番の説明、１１は良熱伝導性混成集積回路基板、
１２は導電路、１３はヒートシンク、１４は電力用半導
体素子、１５はニッケルメッキ抵抗体、１７は張出しリ
ードである。Figure 1 is a top view explaining the conventional example, and Figure 2 is the same as in Figure 1.
-■ Line sectional view, Figure 3 is a top view explaining the visitor bird, Figure 4 is a top view to explain the visitor bird.
The figure is a sectional view taken along the line IV-IV in FIG. 3. Explanation of the main drawing numbers: 11 is a hybrid integrated circuit board with good thermal conductivity;
12 is a conductive path, 13 is a heat sink, 14 is a power semiconductor element, 15 is a nickel-plated resistor, and 17 is an overhanging lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 良熱伝導性混成集積回路基板と該基板上に設けた所望形
状の導電路と該導電路上に固着されたヒートシンクと該
ヒートシンクに固着された電力用半導体素子と前記ヒー
トシンクを固着した導電路に一端を重畳したニッケルメ
ッキ抵抗体とを具備する混成集積回路に於いて、前記ニ
ッケルメッキ抵抗体を前記ヒートシンクを固着した導電
路より延在され且つ離間された張出しリードにその一端
を重畳して成る混成集積回路。A hybrid integrated circuit board with good thermal conductivity, a conductive path of a desired shape provided on the substrate, a heat sink fixed on the conductive path, a power semiconductor element fixed to the heat sink, and one end of the conductive path fixed to the heat sink. In a hybrid integrated circuit comprising a nickel-plated resistor overlaid with a nickel-plated resistor, one end of the nickel-plated resistor is overlapped with an overhang lead extending from a conductive path fixed to the heat sink and spaced apart. integrated circuit.
JP1983039187U 1983-03-17 1983-03-17 hybrid integrated circuit Granted JPS59145083U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983039187U JPS59145083U (en) 1983-03-17 1983-03-17 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983039187U JPS59145083U (en) 1983-03-17 1983-03-17 hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS59145083U true JPS59145083U (en) 1984-09-28
JPH0351992Y2 JPH0351992Y2 (en) 1991-11-08

Family

ID=30169839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983039187U Granted JPS59145083U (en) 1983-03-17 1983-03-17 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59145083U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140754U (en) * 1974-09-20 1976-03-26
JPS56157086A (en) * 1980-05-09 1981-12-04 Tokyo Shibaura Electric Co Hybrid integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140754B2 (en) * 1972-12-25 1976-11-05

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140754U (en) * 1974-09-20 1976-03-26
JPS56157086A (en) * 1980-05-09 1981-12-04 Tokyo Shibaura Electric Co Hybrid integrated circuit

Also Published As

Publication number Publication date
JPH0351992Y2 (en) 1991-11-08

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