JPS59139446A - 加算回路 - Google Patents
加算回路Info
- Publication number
- JPS59139446A JPS59139446A JP1344683A JP1344683A JPS59139446A JP S59139446 A JPS59139446 A JP S59139446A JP 1344683 A JP1344683 A JP 1344683A JP 1344683 A JP1344683 A JP 1344683A JP S59139446 A JPS59139446 A JP S59139446A
- Authority
- JP
- Japan
- Prior art keywords
- input
- logic gate
- signal
- inputs
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1344683A JPS59139446A (ja) | 1983-01-28 | 1983-01-28 | 加算回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1344683A JPS59139446A (ja) | 1983-01-28 | 1983-01-28 | 加算回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59139446A true JPS59139446A (ja) | 1984-08-10 |
JPH0142431B2 JPH0142431B2 (enrdf_load_stackoverflow) | 1989-09-12 |
Family
ID=11833357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1344683A Granted JPS59139446A (ja) | 1983-01-28 | 1983-01-28 | 加算回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59139446A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4866658A (en) * | 1984-09-10 | 1989-09-12 | Raytheon Company | High speed full adder |
-
1983
- 1983-01-28 JP JP1344683A patent/JPS59139446A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4866658A (en) * | 1984-09-10 | 1989-09-12 | Raytheon Company | High speed full adder |
Also Published As
Publication number | Publication date |
---|---|
JPH0142431B2 (enrdf_load_stackoverflow) | 1989-09-12 |
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