JPS59138338A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59138338A
JPS59138338A JP58013271A JP1327183A JPS59138338A JP S59138338 A JPS59138338 A JP S59138338A JP 58013271 A JP58013271 A JP 58013271A JP 1327183 A JP1327183 A JP 1327183A JP S59138338 A JPS59138338 A JP S59138338A
Authority
JP
Japan
Prior art keywords
layer
impurities
phosphorus concentration
gettering effect
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58013271A
Other languages
Japanese (ja)
Inventor
Akinori Shimizu
了典 清水
Misao Saga
佐賀 操
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP58013271A priority Critical patent/JPS59138338A/en
Publication of JPS59138338A publication Critical patent/JPS59138338A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To give the resistance to steam whereas keeping the gettering effect of impurities by constructing a phosphorus glass layer as the two-layer construction, that is a lower layer of high phosphorus concentration and an upper layer of low phosphorus concentration. CONSTITUTION:In a polycrystalline Si gate FET, phosphorus glass layers 71 and 72 are deposited on a polycrystalline Si gate region 5 through an oxide film and on a field oxide film 6. Among these layers, the layer 71 has the phosphorus concentration of 8X10<20>cm<-3> and the layer 72 has that of 1-8X10<20>cm<-3>. By this constitution, the layer 71 sucks out impurities present on the surface of an Si substrate 1 and performs gettering. Meanwhile, the layer 72, whose gettering effect is weaker than that of the layer 71, comprises the phosphorus concentration showing enough gettering effect for the impurities from external atmosphere as well as the resistance to steam.

Description

【発明の詳細な説明】 本発明はパッシベーション膜としてυんを含む酸化珪素
を主成分とする被膜を備えた半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a film mainly composed of silicon oxide containing υ as a passivation film.

半導体装置のパッシベーション膜として半導体材料の化
合物を用いる例としては、シリコン半導体装置における
窒化珪素膜あるいはυんを含んだ酸化珪素膜(以下りん
ガラスと記す)が知られている。窒化珪素は不純物イオ
ンの透過を阻止する性質は酸化珪素よフすぐれているが
、窒化珪素膜生成の際の半導体装置の特性の変鯖による
歩留りの低下を招き、装置の製造コストが上昇するとい
う問題点がある。9んガラスはこれに対しりんのゲッタ
リング効果を利用して半導体表面から不純物を除くもの
でおるが、ゲッタリング効果を充分にするために夛ん濃
度を高くするとシんガラスの吸水性が増大し、外部ふん
囲気中の水蒸気に対する耐性が弱まるほか、エツチング
されやすくなってパッシベーション膜の微細加工精度が
サイドエッチによって低下する欠点がある。
As an example of using a compound of a semiconductor material as a passivation film of a semiconductor device, a silicon nitride film or a silicon oxide film containing υ (hereinafter referred to as phosphorus glass) in a silicon semiconductor device is known. Although silicon nitride has better properties than silicon oxide in blocking the permeation of impurity ions, it causes changes in the characteristics of semiconductor devices during silicon nitride film formation, resulting in lower yields and higher device manufacturing costs. There is a problem. On the other hand, phosphor glass uses the gettering effect of phosphorus to remove impurities from the semiconductor surface, but if the concentration of phosphorus is increased to ensure a sufficient gettering effect, the water absorption of the phosphor glass increases. However, it has the drawback that its resistance to water vapor in the external ambient air is weakened, and it also becomes more susceptible to etching, reducing the precision of microfabrication of the passivation film due to side etching.

本発明は、上記の欠点を除去して不純物のゲッタリング
効果を維持しつつ外部ふん囲気中の水蒸気に対する耐性
を有し、しかも微細加工が充分に可能なりんガラスパッ
シベーション膜を有する半導体装置を提供することを目
的とする。
The present invention eliminates the above drawbacks and provides a semiconductor device having a phosphor glass passivation film that maintains the gettering effect of impurities, has resistance to water vapor in the external surrounding air, and is sufficiently capable of microfabrication. The purpose is to

この目的はパッシベーション膜としてのりんガラス層が
半導体素体に近い側に設けられる8X1020薗−3を
超えるシんを含む層と、半導体素体より遠い側に設けら
れる1〜8X10 QI7B  のυんを含む層からな
ることによって達成される。
The purpose of this is to use a phosphor glass layer as a passivation film, which includes a layer containing more than 8X1020 QI7B provided on the side closer to the semiconductor element, and a layer containing more than 1 to 8X10 QI7B provided on the side farther from the semiconductor element. This is achieved by comprising layers containing:

以下図を引用して本発明の実施例について説明する。第
1図に示すポリシリコンゲート電界効果トランジスタに
おいては、シリコン基板1はソース領域2、ドレイン領
域8を有し、ソース領域2とドレイン領域8にまたがる
ゲート酸化膜4の上にポリシリコンゲート領域5が形成
されている。
Embodiments of the present invention will be described below with reference to the drawings. In the polysilicon gate field effect transistor shown in FIG. is formed.

このポリシリコンゲート領域5の上に酸化膜を介してな
らびにフィールド酸化膜6の上に表面保饅膜としてシん
濃度1.5X10”rn−3のρんガラス層71を化学
的気相成長法(CVD法)によシ被着した後、その上面
に同じ< CVD法によυシん濃度7X10 crnの
シんガラス層72を堆積する。各りんガラス層71゜7
2の厚さはそれぞれ80001である。次いでゲート酸
化膜4、フィールド酸化膜6、シんガラス層71゜72
に光蝕刻法を利用して窓を明けたのち、A/配線8t−
蒸着し、さらにファイナルパッシベーション膜として窒
化珪素膜9を被覆する。このように構成することにより
下側のシんガラス層71はシリコン基板10表面にある
不純物を吸い出してゲッタリングする。上側のシんガラ
ス層72は下側の層71よりゲッタリング効果は低いも
のの外部ふん囲気よりの不純物に対して充分なゲッタリ
ング効果を示すシん濃度を有し、かつ水蒸気に対する耐
性も保有する。またエツチングによる窓明は加工の際に
は、上側のシんガラス層72の耐食性が充分である庭め
サイドエッチが少なく、微細加工が可能である。さらに
全面をファイナルパッシベーション膜9が被覆している
ので保護効果はよシ完全となる。なおこの窒化珪素膜9
はシんガラス層71.72の上に設けられるので、装置
の特性を変動させることもない。
A glass layer 71 with a density of 1.5 x 10"rn-3 is formed on the polysilicon gate region 5 via an oxide film and on the field oxide film 6 as a surface protection film by chemical vapor deposition. (CVD method), then a phosphor glass layer 72 with a phosphor concentration of 7×10 crn is deposited on the upper surface by the same CVD method.Each phosphor glass layer 71°7
The thickness of 2 is 80001 mm. Next, gate oxide film 4, field oxide film 6, and thin glass layer 71°72
After opening the window using photoetching method, A/wiring 8t-
Then, a silicon nitride film 9 is coated as a final passivation film. With this configuration, the lower thin glass layer 71 sucks out impurities on the surface of the silicon substrate 10 and performs gettering. Although the upper thin glass layer 72 has a lower gettering effect than the lower layer 71, it has a thin concentration that exhibits a sufficient gettering effect against impurities from the external ambient air, and also has resistance to water vapor. . Furthermore, when etching the window, the corrosion resistance of the upper shingle glass layer 72 is sufficient, and there is little side etching, allowing for fine processing. Furthermore, since the entire surface is covered with the final passivation film 9, the protective effect is even more complete. Note that this silicon nitride film 9
Since they are provided on the thin glass layers 71, 72, they do not change the characteristics of the device.

しかし第1図と共通の部分に同一の符号を付した第2図
に示すようにこのような二層構造のシんガラス層71.
72を電極膜8の配線後のファイナルパッシベーション
膜として適用することも可能である。
However, as shown in FIG. 2, in which parts common to those in FIG.
It is also possible to apply 72 as a final passivation film after wiring of the electrode film 8.

以上述べたように、本発明によれば半導体装置のパッシ
ベーション膜としてのシんガラス層を、ゲッタリング効
果の大きい高ルん濃度の下層と水蒸気に対する耐性の大
きい低υん濃度の上層との2層構造としたため、半導体
の表面状態に影響を与える不純物のゲッタリング効果を
充分に存し、しかも外部雰囲気の水蒸気あるいは不純物
の作用も阻止できるパッシベーション膜としての機能を
保持させることができる。従って半導体装置の信頼性を
向上させることができる。
As described above, according to the present invention, a thin glass layer as a passivation film of a semiconductor device is made of two layers: a lower layer with a high phosphor concentration, which has a large gettering effect, and an upper layer with a low phosphor concentration, which has a high resistance to water vapor. Because of the layered structure, it has a sufficient gettering effect for impurities that affect the surface state of the semiconductor, and can also maintain its function as a passivation film that can block the effects of water vapor or impurities in the external atmosphere. Therefore, the reliability of the semiconductor device can be improved.

本発明は実施例に挙げたポリシリコンゲート電界効果ト
ランジスタに限らずバイポーラトランジスタ、ダイオー
ド1抵抗等の個別素子にも適用でき、さらにパッシベー
ション膜の微細加工性も良好なので、それらの素子から
構成される集積回路の高集積化も可能であるなど、すべ
ての半導体装置に対して得られる効果はすこぶる大きい
The present invention is not limited to the polysilicon gate field effect transistor mentioned in the embodiment, but can also be applied to individual elements such as bipolar transistors, diode single resistors, etc. Furthermore, since the passivation film has good microfabrication properties, it can be constructed from these elements. The effects that can be obtained on all semiconductor devices, such as the possibility of higher integration of integrated circuits, are extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図は本発
明の別の実施例を示す断面図である。 1・・・シリコン基板、4・・・ゲート酸化膜、5・・
・ポリシリコンゲート、6・・・フィールド酸化膜、7
1・・・高シん濃度りんガラス層、72・・・低シん濃
度シんガラス層、8・・・ke配線。 2/  凹 rz  口
FIG. 1 is a sectional view showing one embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment of the invention. 1... Silicon substrate, 4... Gate oxide film, 5...
・Polysilicon gate, 6...Field oxide film, 7
1...High phosphorus concentration phosphor glass layer, 72...Low phosphor concentration phosphor glass layer, 8...Ke wiring. 2/ Concave rz mouth

Claims (1)

【特許請求の範囲】[Claims] 1)パッシベーション膜としてのシんガラス層が半導体
素体に近い側に設けられる8X10 an  を超える
シんを含む層と、半導体素体よシ遠い側に設けられる1
〜8X1020ryrrb−3のυんを含む層とからな
ることを特徴とする半導体装置。
1) A thin glass layer as a passivation film is provided on the side closer to the semiconductor body, and a layer containing more than 8×10 an is provided on the side far from the semiconductor body.
A semiconductor device comprising a layer containing υ of ˜8×1020ryrrb-3.
JP58013271A 1983-01-28 1983-01-28 Semiconductor device Pending JPS59138338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58013271A JPS59138338A (en) 1983-01-28 1983-01-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58013271A JPS59138338A (en) 1983-01-28 1983-01-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59138338A true JPS59138338A (en) 1984-08-08

Family

ID=11828547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58013271A Pending JPS59138338A (en) 1983-01-28 1983-01-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59138338A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125940A (en) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348474A (en) * 1976-10-15 1978-05-01 Hitachi Ltd Electronic parts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348474A (en) * 1976-10-15 1978-05-01 Hitachi Ltd Electronic parts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125940A (en) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd Semiconductor device

Similar Documents

Publication Publication Date Title
US4816425A (en) Polycide process for integrated circuits
US3837935A (en) Semiconductor devices and method of manufacturing the same
US4700215A (en) Polycide electrodes for integrated circuits
JPS6132471A (en) Thin film transistor
JPS60170972A (en) Thin film semiconductor device
JPS59138338A (en) Semiconductor device
GB1577017A (en) Method for manufacturing a semiconductor intergrated circuit device
KR840008210A (en) Gettering method for semiconductor substrate material of integrated circuit
JP2538830B2 (en) A method for partial oxidation of silicon using a ceramic barrier layer.
JP3013628B2 (en) Semiconductor device
JPH02130961A (en) Field-effect transistor
GB1255347A (en) Improvements in semiconductor devices
JPS61150276A (en) Semiconductor device
JPS6242560A (en) Electrode for semiconductor device
JPH0579184B2 (en)
JPS61228661A (en) Semiconductor device and manufacture thereof
JPS6097628A (en) Manufacture of semiconductor device
JPS6195562A (en) Manufacture of semiconductor device
JPS6159539B2 (en)
JPS6127177Y2 (en)
JPH07147403A (en) Semiconductor device and manufacture thereof
JPS6346736A (en) Semiconductor device
JPH08125022A (en) Manufacture of semiconductor device
JPS63128733A (en) Semiconductor device
JPS58171852A (en) Manufacture of semiconductor device