JPS59137989A - Electronic equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention Technical Field The present invention relates to electronic equipment, and more particularly to personal computers, word processors, etc. that use an RT display as a display means, and a CRTC (CRT control means) that uses a VRAM.
The present invention relates to an electronic device that performs CPU-CRTC independent operation without stopping the operation of a CPU (central processing unit) when accessing data in a random access memory for image data.

BACKGROUND OF THE INVENTION In conventional electronic devices of this type, it is common to display input points by blinking a cursor on a CRT. To control a CRT display in this type of system, it is common to once send image data to a VRAM, access the VRAM by a CRTC (CRT controller), and perform display using the stored data.

As a method for the CRTC to control the CRT, there is a so-called C'PU-CRTC independent operation method in which the operation of the CPU is not stopped when the CRTC accesses the VRAM. The feature of this method is that the CPU continues to operate and the CR
Since the TC controls the CRT, it is very effective in lightening the load on the CPU and maintaining the original speed of the CPU, but if the time when the CPU accesses the VRAM and the time when the CRTC accesses the VRAM overlap, There is a drawback that noise may be generated on the screen because priority is given to the operation of the CPU.

In view of this, in order to prevent noise, when the CPU accesses the VRAM for cursor blinking, normally in this system, when the CRTC does not access the VRAM, the retrace period (from the end of the vs line) In the section up to the start point of the next bright line, there are two types: between bright lines and between screens.) The CPU accesses VRAM and blinks the cursor, but this slows down the display speed. There was a drawback.

Purpose The present invention has been made in view of the above points, and an object of the present invention is to provide an electronic device having a CRT display means that does not generate noise on the screen and has a high display speed.

EXAMPLES Hereinafter, the present invention will be explained in detail based on examples shown in the drawings.

FIG. 1 shows a block diagram of an electronic device adopting the present invention. The configuration shown in FIG. 1 is common to electronic devices such as personal computers and word processors that use a CRT as a display means.

In the figure, the symbol l indicates the CPU (Central Processing Unit), the ROM (Read Only Memory), the RAM (
It has a random access memory (random access memory), a control section, etc., and performs all processing operations based on a clock generated by the crystal oscillator 2 according to a program stored in a known ROM.

This CPUI has an address bus 8 and a multiplexer 17.
It is connected to VRAM16 via
specifies the data address by the signal line 18 of the multiplexer 17. The image data to be displayed is transferred via the data bus 9, transfer game) 19, and data/<A22.
．． [Transferred to VRAM 16.

In addition, a memory write signal indicating the timing of memory read and memory write of the CPU is input to the AND gate 5 via the signal line 4, and the output of the AND gate 5 is input via the signal line 6 to the VRAM memory input. connected to the terminal. The other input terminal of AND gate 5 is set to “0” only when accessing the memory via signal line 3.
The inverted signal of the system signal is input. The R/W signal outputted to the signal line 4 is a signal that becomes "0" only during memory writing, and therefore the output signal line 6 of the AND gate 5 becomes "0" during memory writing.

Furthermore, the system signal on the signal line 3 is inverted and input to the AND gate 25, and furthermore, the system signal on the AND gate 25 is
The most significant bit of the address bus 8, the second bit and the third bit are inverted by an AND gate 15, and the resulting logical sum is input to the address bus 8. In this embodiment, VRAM
16 addresses are set from 8000 to 9FFF,
When the VRAM 16 is accessed, the upper three digits of the address are always in the form rlooJ in binary (8 in hexadecimal is 1000.9 in binary and 1001). The two input lines are set to rlJ only when the address of the VRAM 16 is specified by the address bus 8.
A VRAM access signal is obtained on the output signal line 7, and the access signal on the signal line 7 controls the multiplexer 17 and transfer gate 19 to perform address designation and image data transfer. CPU1 is VR
The address bus 9 is separated from the data bus 22 on the VRAM 1B side by the transfer gate 19 unless the AMI 6 is accessed, that is, unless the access signal on the signal □ line 7 becomes rlJ.

The CRTCl 2 has a crystal oscillator 13, and this clock signal determines the fundamental frequency of the video signal.
This is to control T. A data bus 22 is directly connected to the CRTC 12, and the CRTC 12 directly specifies the address of the VRAM 16 via the address bus 14, multiplexer 17, and signal line 18, and transfers image data via the data bus 22.

The CRTC 12 is configured so that a retrace interval signal is outputted from the terminal indicated by the reference numeral 24 to the signal line 21.
This signal line 21 is connected to the clock input of the D flip-flop 20. The D input of this D flip-flop is always bolded to "1", and when the retrace interval signal of the signal line 21 is input, the non-inverted output of the D flip-flop 2o becomes rlJ, and the signal is passed through the signal line lo. The CPU is inter-wired.

The CPUI cancels the interconnected mode via the signal line 11.
The D flip-flop may be reset by sending "l" to the reset terminal of the flip-flop 2o, and the signal line 11 may be held at rlJ when the cursor blinking is unnecessary.

According to the above configuration, the address bus and data bus of the VRAM 16 are connected to the CPU side only when the CPUI is accessing the VRAM 16, so that the operation of the CPUI and the operation of the CRTC 12 can be performed independently.

When accessing the VRAM 16 on the CPUI side, the access is performed by sending an access signal through the AND gate 25 while observing the state of the retrace interval signal on the signal line 21, thereby preventing noise on the screen.

Next, the processing when the retrace section signal is output from the CRTC 12 side will be explained in more detail with reference to the flowchart of FIG.

That is, in step Sl in FIG.
When a retrace interval signal is generated and an interband is applied to the CPU, the CPU adds 1 to a predetermined counter that counts the retrace interval signal, and then in step S2, the contents of this counter are set to a predetermined value (this embodiment 10) or more is determined.

If the content of the counter is greater than or equal to the predetermined value in step S2, the counter value is reset to O in step S3, the cursor is inverted in step S4, and the process moves to step S5.

On the other hand, if the counter value is less than or equal to the predetermined value in step S2, the process directly proceeds to step S5, and if the counter value is greater than or equal to the predetermined value, the signal on the signal line 11 is set to "1" as post-processing, and then set to "0".
The latch output of the D flip-flop 20 for interconnection is reset.

As described above, the cursor can be inverted and blinked at every predetermined frame on the screen, but when the CPU determines whether or not to blink the cursor, it is always within the retrace interval, which causes noise on the screen. It is possible to immediately invert the cursor without having to do so. That is, since there is no need for the CPUI to wait for the retrace section, the cursor can be blinked without using a timer or the like for blinking the cursor, and it can also be used as an interactive mask, which is highly effective.

(1) According to the present invention, a CRT display capable of displaying an input position by blinking a cursor is used as a display means, and when the control means of this CRT accesses data in the VRAM, the CPU CP that does not stop the operation of
The electronic device that performs U-CRTC independent operation employs a configuration in which the CPU counts retrace section signals generated by the CRT control means to determine the timing of cursor reversal processing when the cursor blinks. Therefore, it is possible to provide an excellent electronic device that does not generate noise on the screen and has a fast display speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an electronic device according to the present invention, and FIG. 2 is a flowchart explaining the processing procedure in the configuration of FIG. 1. l...CPU 5.15.25...AND gate 8.14...Address bus 9.22...Data bus 12...CRTC16...VRAM20...D flip-flop

Claims (1)

[Claims] A CRT display that can display the input position by blinking the cursor is used as the display means, and the control means for this CRT is VRA.
In an electronic device that performs C, P U - CRT C independent operation without stopping the CPU operation when accessing data of M, the cursor is controlled by the CPU counting blanking section signals generated by the CRT control means. An electronic device characterized by determining the timing of cursor reversal processing when blinking.