JPS59134934A - Stereo demodulating circuit - Google Patents

Abstract

PURPOSE:To attain no adjustment of a synchronizing frequency without using resonator by rpoviding two systems of LPFs and a variable amplifier in a phase locked loop and adjusting the amplification gain to change a sysnchronizing frequency band. CONSTITUTION:Passing frequency band of the LPFs 10,12 is taken respectively as f1,f2. The former is a narrow band and the latter has the relation of f1>f2. Before a PLL circuit 4 is locked to a pilot signal of a stereo signal, a gain A1 of an amplifier 14 is set low and a gain A2 of an amplifier 16 is set high, and after locking, the gain A1 is set high and the gain A2 is set low. This adjustment is performed continuously and linearly by interlocking each amplifier. Let characteristics A and B be gains of the amplifiers 14, 16 to a system, then the system of the amplifier 16 keeps the characteristic B before syncrhronism and the system of the amplifier 14 decreases the gain as shown in the characteristic A' by the gain adjustment. The synthesized characteristics of them is the sum of the both, the frequency band is extended and a high gain is attained at the band. After locking, the systems of the amplifiers 14,16 are adjusted for the gain as shown in the charcteristics A',B', and the frequency band of the synthesized gain is narrowered.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo demodulation circuit, and more particularly, to a stereo demodulation circuit that uses a phase-locked loop (PLL).
This invention relates to non-adjustment of the synchronization frequency of a stereo demodulation circuit using a stereo demodulation circuit (op) circuit).

Generally, a PLL circuit is used in a stereo demodulation circuit to detect a pilot signal, and the synchronization frequency fo of this PLL circuit needs to be adjusted to a constant frequency. Conventionally,
A resonator is used in this PLL circuit, and the synchronous frequency is not adjusted, but the use of this resonator has the disadvantage of making the system expensive.

Therefore, it is theoretically possible (2) to synchronize the PLL circuit to the pilot signal frequency without using a resonator, but it is extremely difficult due to the frequency characteristics of the circuit, loop gain, etc., and is practically impossible. It is. For example, if the lock range is set wide, the capture range will expand due to the relationship between the DC loop gain and the filter, and for the viroft signal frequency 19KIIz, the capture range will be 19/2.19/3KH.
Complex frequency components such as z are generated, which causes beat disturbances.

As a result, stable demodulation of stereo signals becomes difficult.

The object of the present invention is to provide a stereo demodulation circuit that makes it possible to eliminate synchronization frequency adjustment without using a resonator.

This invention provides at least two systems of low-pass filters having different frequency bands, individually or in conjunction, in a phase-locked loop that synchronizes with the frequency of a pilot signal included in a stereo composite signal and detects the pilot signal. It is characterized in that amplifiers with variable amplification gains are installed, and the synchronous frequency band is varied by adjusting the amplification gains of one or more of these amplifiers.

(3) Embodiments of the invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the stereo demodulation circuit of the present invention. A stereo composite signal demodulated by an FM demodulation circuit is supplied to the input terminal 2, and this stereo composite signal is supplied to a PLL circuit 4 that detects a biloft signal and a stereo decoder 6 that detects left and right audio signals. .

A phase comparator 8 is installed in the input stage of the PLL circuit 4 to which the stereo composite signal is applied, and the phase comparator 8 is installed at the input stage to which the stereo composite signal is applied.
A phase comparison with the output frequency of the circuit 4 is performed. This embodiment includes two low-pass filters 10.12 and an amplifier 14.16 on the output side of the phase comparator 8.
is installed. Assuming that the pass frequency band of the low-pass filter 10.12 is f7 for the former and f2 for the latter, the former has a narrow band and the latter has a wide band fI x f2. For example, f
It is assumed that l is set to several tens to several hundred H2zf2 is set to several hundred to several kHz. Further, the amplifiers 14.16 are configured so that the amplification gain can be adjusted continuously and linearly from the outside in accordance with the control signal input, and the passband and system gain of the low-pass filter 10.12 allow A desired synchronization frequency range is set.

A voltage controlled oscillator 18 that generates a frequency output according to the amplified output is installed on the output side of these two systems of amplifiers 14 and 16, and a capacitor 20 is connected to the outside for frequency setting. A 1/2 frequency divider 22, 24 is installed on the output side of this voltage controlled oscillator 18. The 38KH++ switching signal taken out from the output side of the 1/2 frequency divider 22 is given to the stereo decoder 6, and the 19KHz biloft signal of the 1/2 frequency divider 24 is given to the phase comparator 8. ing.

Then, the stereo decoder 6 receives the stereo composite signal and P
It is configured to be able to detect left and right audio signals from the 38 KHz switching signal from the LL circuit 4.

The operation of the above configuration will be explained. Before the PL L circuit 4 synchronizes with the pilot signal fo, the gain A1 of the amplifier (5) 14 is set low and the gain A2 of the amplifier 16 is set high, and after synchronization, the gain A1 of the amplifier 14 is set high and the gain A2 of the amplifier 16 is set high. Adjust lower. It is assumed that such gain adjustment is performed continuously and linearly by interlocking each amplifier 14, 16.

Figure 2 shows the frequency-gain relationship, and characteristic A is defined as amplifier 1.
If characteristic B is the gain in the amplifier 16 system, the amplifier 16 system maintains characteristic B before synchronization, while the amplifier 14 system gains a gain as shown in characteristic A by adjusting its gain. decrease. These composite characteristics are the sum of characteristic A' and characteristic B, and the frequency band is expanded, resulting in a high gain in that frequency band. As a result, before synchronization, the synchronization frequency range is expanded, prompt synchronization is performed, and inconveniences such as loss of synchronization are prevented.

After synchronization, as shown in FIG. 2, the amplifier 14 system is adjusted to a high gain as shown in characteristic A, while the amplifier
System 6 lowers the gain as shown in characteristic B'' and narrows the frequency band of these combined gains (6).As a result, after synchronization, the synchronization frequency range is narrowed and the synchronization state with respect to the pilot signal frequency is maintained. The generation of conventional beat frequencies can be prevented.

The pilot signal detected by the PLI circuit 4 is then applied to the stereo decoder 6 together with the stereo composite signal to separate left and right audio signals, which are taken out from output terminals 26 and 28.

In addition, if the amplification gain of the amplifiers 14 and 16 is adjusted continuously and linearly in response to frequency synchronization, the synchronization state can be quickly obtained, and the generation of unnecessary frequencies after synchronization can be reliably suppressed. This makes it possible to prevent synchronization from occurring due to gain changes, and to eliminate frequency adjustment.

Furthermore, regarding the adjustment of the gains AI and A2 of the amplifiers 14 and 16, the combined gain before synchronization is Gl (AI''+A2),
If the composite gain after synchronization is 02 (AI + A2'), set the composite gain G2 after synchronization to be larger than the composite gain G1 before synchronization (Gl < G2). (7) Toniyori, expand the DC loop gain. It is possible to achieve a stable synchronization state.

In addition, when an amplitude limiter (limiter) is installed inside the PLL circuit 4, in the gain adjustment, before synchronization,
By controlling the limit range to be expanded, it is possible to eliminate frequency adjustment.

In the embodiment, the gains of both the amplifiers 14 and 16 are adjusted, but the same effect can be expected by fixing the gain of either one and widening the gain adjustment range of the other.

FIG. 3 shows the low-pass filter 10.12 and the amplifier 1.
A specific example of 4.16 is shown.

In the figure, capacitors 30 and 32 constitute the low-pass filter 10.12, and an amplifier 14.16 is integrated with each capacitor 30.32 so that the operating current can be adjusted. That is, transistors 34 and 36 have a common emitter, and transistors 38 and 40 also have a common emitter, and these constitute a pair of differential amplifiers. The collectors of each transistor 34, 36, 38, 4o are connected to the power supply terminal 41 via resistors 42, 44, 46, 48, respectively, and the capacitor 3o is connected to the transistor 34, 38, 4o.
6 and the capacitor 32 is connected between the collectors of the transistor 38.4o. The bases of the transistors 34, 40 are connected together to form a bias input terminal 50, which
A constant bias voltage VB+ is applied to the transistors 36 and 38, an input terminal 52 is commonly formed at the bases of the transistors 36 and 38, and a long signal is applied from the phase comparator 8.

Transistor 5 is connected to the emitter of transistor 34 and 36.
The collectors of the transistors 56 and 56 are connected to the emitters of the transistors 38 and 40, and the emitters of the transistors 54 and 56 are connected in common through a resistor 58.6o, and the center point of the resistor 58.60 is connected to the reference point. A constant current source 64 is connected between the potential point terminal 62 and the potential point terminal 62 .

A bias input terminal 66 (9) is formed at the base of the transistor 54 to which a constant bias voltage VB2 is applied, and a control input terminal 68 is formed at the base of the transistor 56 to which a control voltage Vc is applied.

The transistors 70 and 72, the resistors 74 and 76, and the constant current source 78 constitute an output circuit that takes out the output from the capacitor 30 side, and the transistors 80 and 82 constitute an output circuit that takes out the output of the 32 capacitors. ing. Output terminals 84.86 are formed at the collectors of transistor 70180 and transistors 72.82.

In the above configuration, the operation will be explained. Control input terminal 6
Adjusting the applied control voltage will change the proportion of current flowing through transistors 54, 56 in response to this voltage input. Accordingly, the operating currents of the differential amplifier composed of the transistors 34 and 36 and the differential amplifier composed of the transistors 38 and 40 change, and as a result, the amplification gain is adjusted.

That is, when the control voltage is changed continuously and linearly, these gains change accordingly. (10) Therefore, the signal given to the input terminal 52 is
0.32 and can be taken out at output terminals 84.86 at output levels with different gains.

Therefore, according to such a circuit, it is possible to adjust the frequency characteristics and amplification gain as in the embodiment described above, and it is possible to eliminate adjustment of the synchronization frequency in the PLL circuit as in the embodiment described above.

In the embodiment, the low-pass filter and the amplifier are configured with two systems, but the same effect can be expected even if the low-pass filter and amplifier are configured with three or more systems.

As explained above, according to the present invention, without using a conventional resonator, the frequency bands of at least two systems are changed before and after synchronization by adjusting the amplification gain, thereby eliminating the need to adjust the synchronization frequency. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the stereo demodulation circuit of the present invention, FIG. 2 is an explanatory diagram showing its characteristics, and FIG. 3 is a circuit diagram showing a gain adjustment system. 4... Phase locked loop, 1o, 12... Low pass filter, 14.16... Increased IHjt.

Claims (1)

[Claims] +11 In a phase-locked loop that synchronizes with the frequency of a pilot signal included in the stereo composite signal and detects the pilot signal, at least two systems of low-pass filters having different frequency bands are used individually or together. A stereo demodulation circuit characterized by installing amplifiers whose amplification gains can be varied in conjunction with each other, and adjusting the amplification gain of one or more of these amplifiers to vary a synchronous frequency band. (2) The low-pass filter is composed of two systems, one wideband and one narrowband, and each of these low-pass filters is equipped with an amplifier whose amplification gain can be individually varied, and before synchronization, the amplification gain of the wideband side system is set high. At the same time, the amplification gain of the system on the narrowband side is lowered, and after synchronization, the amplification gain of the system on the wideband side is lowered, and the amplification gain of the system on the narrowband side is increased. The stereo demodulation circuit according to item 1. (1) (3) The low-pass filter is composed of two systems, one wideband and one narrowband, and an amplifier with variable amplification gain is installed in each system, so that the combined gain after synchronization is higher than the combined gain before synchronization. Claim 1 characterized in that
The stereo demodulation circuit described in section.