JPH0654849B2 - PLL synchronous detection circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a PLL synchronous detection circuit.

[Technical background of the invention]

There is a PLL synchronous detection method as a high-performance detection method for television signals. However, since the steady state characteristic and the synchronous characteristic of the PLL are in a contradictory relationship, a PLL synchronous detection circuit applying a two-mode PLL in which a wide pull-in range and a narrow noise band are compatible is generally used.

FIG. 2 is a block diagram showing an example of a PLL synchronous detection circuit using a 2-mode PLL. In the following description, the case of negative polarity detection will be described, but the same applies to the case of positive polarity detection.

First, the video intermediate frequency signal output from the tuner is supplied to the video detector 2 and the phase detector 3 amplified by the intermediate frequency amplifier 1, respectively. The phase detector 3 is cascade-connected to a low pass filter 4, a voltage controlled oscillator 5, and a 90 ° phase shifter 60 ° to form a PLL.

Therefore, when the PLL is synchronized, the output of the voltage controlled oscillator 5 becomes in phase with the carrier of the video intermediate frequency signal input to the video detector 2. Therefore, in this state, the output of the voltage controlled oscillator 5 is used as the second input of the video detector 2, whereby synchronous detection can be performed and a demodulated signal can be obtained from the video detector 2. The demodulated video signal is amplified by the video amplifier 7 and output. The AGC circuit 8 is supplied with the output of the video amplifier 7 and controls the gain of the intermediate frequency amplifier 1 so that the output level becomes a predetermined level. The lock detector 9 also provides an output of the video amplifier 7, the output waveform, utilizing causing a potential difference V _E becomes a video waveform in a sine wave, the locked state is unlocked as for example shown in Figure 3 By detecting that the PLL is synchronized, the time constant of the low-pass filter 4 is switched.

FIG. 4 is a circuit diagram showing a concrete example of the lock detector, which is obtained by a smoothing circuit composed of a resistor R ₁ and a capacitor C ₁ by a comparator composed of transistors Q ₁ , Q ₂ , a resistor R ₂ and a current source IC _1. The reference potential V ₁ is compared with the average potential obtained.
When the average potential becomes lower than the reference potential V ₁ , a current flows through the resistor R ₂ and the voltage generated here turns on the transistor Q ₃ . Then current flows through the resistor R _3, the voltage generated in the resistor R ₃ to turn on the transistor Q ₄ a current flows through the resistor R ₄ in the collector, the resistance R
The contact points of ₅ and R ₆ , that is, the collector of the transistor Q ₄ has a substantially ground potential. Therefore, the time constant of the lag-lead filter in which the resistors R ₅ , R ₆ , the capacitor C _6, and the resistor R ₇ are connected in series can be switched.

FIG. 5 is a diagram showing an example of frequency characteristics of the lag-lead filter. Curve A shown in the figure is the characteristic before switching, and curve B is the characteristic after switching.

[Problems of background technology]

In such a conventional PLL synchronous detection circuit, the pull range of the PLL can be widened when the PLL is asynchronous, and the noise band can be narrowed when the PLL is synchronized. You can

However, in such a device, when the input signal level becomes low, the detection gain of the phase detector becomes low, and the PLL and the loop gain decrease. Therefore, the steady characteristics and the synchronization characteristics of the PLL are deteriorated, the synchronization is easily lost due to disturbance, and in the worst case, the synchronous and asynchronous states are repeated.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and is a PL that can obtain stable synchronization performance with respect to variations in the input signal level.
It is an object to provide an L synchronous detection circuit.

[Outline of Invention]

That is, the present invention detects the level of the carrier level of the video intermediate frequency signal by comparing the sync tip level of the video signal output from the video detector with the reference level, and detects the carrier level of the video intermediate frequency signal to carry the video intermediate frequency signal. When it is detected that the carrier level is low, the PLL circuit has a loop gain with improved synchronization performance, and when the carrier carrier level of the video intermediate frequency signal is detected to be high. , The loop filter constant or the phase loop gain is switched so that the PLL circuit has a loop gain with improved steady-state performance.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the block diagram shown in FIG. The same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, 10 is a level detector to which the output of the video amplifier 7 is given. That is, since the sync chip level of the video signal obtained from the video amplifier 7 is proportional to the carrier level of the input signal, that is, the video intermediate frequency signal, when the sync chip level becomes higher than a predetermined level, the low pass filter is used. The time constant of 4 is switched to improve the synchronization performance of the PLL.

FIG. 6 is a circuit diagram showing a specific example of the level detector 10. Wherein the transistor _Q 1 to Q _4, resistor _R 1 to R ₇ and capacitors _C 1, _{C 2} constitute a lock detector shown in Figure 4. The output of the video amplifier 7 is supplied to the base of the transistor Q ₁₁ and the lock detector, respectively, and in the comparator composed of the transistors Q ₁₁ , Q ₁₂ , resistors R ₁₀ , R ₁₁ , and the current source I _C2 , the sync tip level is obtained. Is compared with the reference potential V ₂ . The reference potential V ₂ is equal to the sync tip level in the normal state. When the sync tip level is higher than the reference potential V ₂ , the transistor Q
_The capacitor C ₃ is charged by ₁₃ and when the sync tip level is lower than the reference potential V ₂ , the transistor Q ₁₄
As a result, the capacitor C ₃ is discharged and becomes stable at the potential V ₃ of the capacitor C ₃ . Therefore, the potential of the capacitor C ₃ increases as the video intermediate wave signal level input to the video detector 2 decreases. The potential of the capacitor C ₃ is compared with the reference potential V ₃ by a comparator composed of the transistors Q ₁₅ and Q ₁₆ and the current source I _{C3. When} the potential of the capacitor C ₃ becomes higher than the reference potential V _{3, the} potential of the current source I _C3 is changed. All current flows through the collector of transistor Q ₁₅ . The transistors Q ₁₇ and Q ₁₈ are a current mirror circuit, and the same amount of current as the collector current of the transistor Q ₁₅ is applied to the transistor Q _15.
It flows through the collector of ₁₈ , and it is flowing through the collector of the transistor Q ₂ . Here, if the current sources I _C1 and I _C3 are made the same, no voltage is generated in the resistor R ₂ and the transistor Q ₄ is turned off. Therefore, even if the PLL is synchronized, if the input video intermediate frequency signal level becomes low, the PLL becomes an asynchronous loop constant, and the synchronization performance can be improved.

FIG. 7 is a block diagram showing another embodiment of the present invention, AGC.
The circuit 8 is used as a carrier level detector for the input signal. The AGC circuit 8 generally detects the sync tip level of the monotone video signal and controls the gain of the intermediate frequency amplifier 1 so as to keep this level constant. Therefore, it depends on the carrier level of the input signal. Generates control voltage. Therefore, by utilizing this control voltage, the time constant of the low-pass filter is switched according to the carrier level of the input signal.

Note that the present invention is not limited to the above-mentioned embodiment, and in short, it is sufficient that the loop constant of the PLL is changed according to the input signal level. For example, in FIG. 1, the intermediate frequency amplifier 1 and the AGC circuit 8 may be omitted. Further, the circuit is not limited to the TV, and any circuit using a PLL can be applied. Further, as a method of switching the loop constant, other than the low-pass filter, for example, the gain of the phase detector may be changed, and the switching is not limited to two modes, but various levels detecting means such as multimode or continuous one, , Various applications are possible.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a PLL synchronous detection circuit that can obtain stable synchronization characteristics with respect to variations in the input signal level.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional PLL synchronous detection circuit, FIG. 3 is a diagram showing an output waveform of a video amplifier, and FIG. 4 is a lock. FIG. 5 is a circuit diagram showing a concrete example of a detector, FIG. 5 is a diagram showing frequency characteristics of a lag lead filter, FIG. 6 is a diagram showing a concrete example of a level detector, and FIG. 7 is another embodiment of the present invention. It is a block diagram shown. 1 ... Intermediate frequency amplifier, 2 ... Video detector, 3 ... Phase detector, 4 ... Low pass filter, 5 ... Voltage controlled oscillator, 6 ... 90 ° phaser, 7 ... Video amplifier, 8 …… A
GC circuit, 9 ... Lock detector, 10 ... Level detector.

Claims (2)

[Claims] 1. A video detector having a video intermediate frequency signal as one input and an output of a phase detector having the video intermediate frequency signal as one input are provided to a voltage controlled oscillator through a low pass filter. , The signal of the same phase as the carrier of the video intermediate frequency signal is reproduced from the voltage controlled oscillator by using the output of the voltage controlled oscillator as the other input of the phase detector.
A video signal obtained by demodulating the video intermediate frequency signal from the video detector by using the reproduction signal output from the voltage controlled oscillator of the PLL circuit as the other input of the video detector. In the PLL synchronous detection circuit to be obtained, a detection means for detecting the level of the carrier carrier level of the video intermediate frequency signal by comparing the sync tip level of the video signal output from the video detector with a reference level. When the detecting means detects that the carrier level of the video intermediate frequency signal is low, the P
The PLL circuit is set to a loop gain with improved steady-state performance so that the LL circuit has a loop gain with improved synchronization performance, and in the state where it has been detected that the carrier level of the video intermediate frequency signal has increased. Thus, a PLL synchronous detection circuit comprising a switching means for switching a loop filter constant or a phase loop gain. 2. The detecting means detects a sync tip level of the video signal output from the video detector, and applies the video intermediate frequency to the video detector so that the sync tip level becomes constant. By comparing the level of the control signal output from the AGC circuit that controls the gain of the intermediate frequency amplifier that amplifies the signal with the reference level,
The P according to claim 1, wherein the level of the carrier level of the video intermediate frequency signal is detected.
LL synchronous detection circuit.