JPH04369188A - Pll lock detector - Google Patents

Abstract

PURPOSE:To realize the PLL lock detector with less terminal number in the case of circuit integration. CONSTITUTION:A maximum voltage discrimination circuit 20 discriminates whether or not the maximum voltage of a signal A is smaller than a maximum reference voltage 40. A minimum voltage discrimination circuit 30 discriminates whether or not minimum voltage of the signal A is smaller than a minimum reference voltage 60. A NOR circuit 100 outputs a signal representing an oscillating frequency of a PLL circuit 2 locks a frequency of carrier included in a video intermediate frequency signal based on the result of discrimination of the maximum voltage discrimination circuit 20 and the minimum voltage discrimination circuit 30. Thus, it is not required to employ a capacitor of a large capacitance and number of terminals in the case of circuit integration is reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a phase-locked loop circuit that receives a video intermediate frequency signal and outputs a lock signal locked to the frequency of a carrier included in the video intermediate frequency signal, and Used in a video signal processing device equipped with a video detector that receives a signal and detects a video intermediate frequency signal using a lock signal, and detects whether the lock signal is locked to the frequency of a carrier wave included in the video intermediate frequency signal. The present invention relates to a PLL lock detection device.

0002

2. Description of the Related Art In recent years, PLL (phase-locked loop) fully synchronous detectors with good linearity have come into widespread use as video detection devices. FIG. 5 is a block diagram showing the configuration of a conventional PLL fully synchronous detector. A video intermediate frequency signal whose amplitude is limited to a constant by a video intermediate frequency signal amplifier (not shown) is applied to a PLL circuit 2 and a video detector 3 via an input terminal 1. The PLL circuit 2 operates as a carrier extraction circuit, and includes a phase comparator 4 and a low-pass filter (hereinafter referred to as L).
Abbreviated as PF. ) 5, a voltage controlled oscillator (hereinafter abbreviated as VCO) 6, a shifter 7 that advances the phase of the output of the VCO 6 by 45 degrees, and a shifter 8 that delays the phase of the output of the VCO 6 by 45 degrees. The phase comparator 4 connects the video intermediate frequency signal to the transfer unit 7.
Compare the phase of the output. The LPF 5 is composed of a series circuit of a resistor R1, a capacitor C1, and resistors R2 and R3, and removes unnecessary harmonic components from the output of the phase comparator 4. The VCO 6 is connected to a common connection point between the resistor R1 and the capacitor C1, and as is well known, the oscillation frequency changes according to the output of the LPF 5. This oscillation frequency is locked to a frequency equal to the carrier wave of the video intermediate wave signal input to the phase comparator 4. As is well known, the phase of this oscillation output is shifted by 90° with respect to the input to the phase comparator 4. Therefore, by shifting the phases by 90° by the shifters 7 and 8, the signal input from the shifter 8 to the video detector 3 becomes a signal that matches the carrier wave of the video intermediate frequency signal in both frequency and phase. This signal and the video intermediate frequency signal are multiplied by the video detector 3 to perform video synchronous detection, and the video synchronous detection output is taken out as the signal A from the output terminal 9.

By the way, in a PLL fully synchronous detector, if the loop time constant of the PLL circuit 2 is increased, the PLL
Although the purity of the carrier wave extracted by circuit 2 is improved, the pull-in range is narrowed. In order to optimize the relationship between the purity of the extracted carrier wave and the pull-in range, it is determined whether the oscillation frequency of the PLL circuit 2 is locked to the carrier wave frequency included in the video intermediate frequency signal, and the loop is activated according to the determination result. I am trying to change the time constant. That is, a smoothing circuit 10, a comparator 11, and a switch SW1 are provided. The smoothing circuit 10 is connected between the output terminal 9 and the negative input of the comparator 11, and smoothes the signal from the output terminal 9. The comparator 11 has a reference voltage Vref connected to its +input, and if the signal level to its -input is greater than the reference voltage Vref, it is determined to be non-locked and set to "L", and if it is smaller, it is determined to be locked. Outputs “H”. switch SW1
is connected to the common connection point of resistors R2 and R3, and the comparator 11
Turns ON in response to “L” from , and turns OF in response to “H”
F. By turning on/off switch SW1, PLL
The loop time constant of circuit 2 changes.

When the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal, the signal A output to the output terminal 9 has a waveform as shown in FIG. This signal A is smoothed by the smoothing circuit 10, and the -
The average voltage of the vertical period (20 seconds) of the signal is given to the input. The magnitude relationship among the average voltage, reference voltage Vref, and no-signal voltage is as shown in FIG. In other words, since the average voltage is smaller than the reference voltage Vref, PL
It is determined that the oscillation frequency of the L circuit 2 is locked to the frequency of the video intermediate frequency signal, and the comparator 11 outputs "H". Switch SW1 turns OFF in response to this "H", and the loop time constant increases, the pull-in range narrows, and P
The purity of the carrier wave extracted by the LL circuit 2 is improved.

On the other hand, when the oscillation frequency of the PLL circuit 2 is not locked to the frequency of the carrier wave of the video intermediate frequency signal,
As shown in FIG. 7, the signal A output to the output terminal 9 has a waveform in which the carrier wave is not removed. This signal A
is vertically symmetrical as shown in FIG. 7, so its average voltage is equal to the no-signal voltage. As shown in FIG. 6, the no-signal voltage is higher than the reference voltage Vref. Therefore,
It is determined that the oscillation frequency of the PLL circuit 2 is not locked to the frequency of the carrier wave of the video intermediate frequency signal, and the comparator 11 outputs "
The switch SW2 is turned ON in response to this "L", and as a result, the loop time constant becomes smaller, the pull-in range becomes larger, and the oscillation frequency of the PLL circuit 2 becomes higher than that of the carrier wave of the video intermediate frequency signal. It becomes easier to lock into the frequency.

[0006] Even if the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal, if the amplitude of the video intermediate frequency signal is small, the average voltage of the signal 4 from the video detector 3 is used as the reference. The voltage may be higher than the voltage Vref, and it is determined that the lock is not locked, regardless of whether the lock is unlocked or not.

[0007]

[Problems to be Solved by the Invention] In the conventional PLL fully synchronous detector, the vertical period (2
0 msec), the average voltage must be held in the capacitor C2, and therefore the capacitance of the capacitor C2 increases to the μF order, making it difficult to integrate. Therefore, the capacitor C2 had to be an external component, which caused the problem that the number of terminals increased.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a PLL lock detection device with a small number of terminals when integrated.

[0009]

[Means for Solving the Problems] The present invention provides a phase-locked loop circuit that receives a video intermediate frequency signal and outputs a lock signal locked to the frequency of a carrier included in the video intermediate frequency signal; After receiving the lock signal,
A PLL lock detection device used in a video signal processing device including a video detector that detects a video intermediate frequency signal using a lock signal, and detects whether the lock signal is locked to the frequency of a carrier wave included in the video intermediate frequency signal. Applies to.

[0010] The PLL lock detection device according to the present invention includes:
a maximum value determining means having a maximum value reference voltage, receiving an output from the video detector and determining whether the maximum value of the output is greater than the maximum value reference voltage; and having a minimum value reference voltage. , a minimum value determining means that receives an output from the video detector and determines whether the minimum value of the output is smaller than the minimum reference voltage; and a determination result of the maximum value determining means and the minimum value determining means. and lock determination means for determining whether or not the lock signal is locked to the frequency of the carrier wave included in the video intermediate frequency signal based on the determination result.

[0011]

[Operation] This invention has a maximum reference voltage,
Maximum value determining means receives the output from the video detector and determines whether the maximum value of the output is smaller than the maximum reference voltage, and has a minimum reference voltage and receives the output from the video detector; Minimum value determining means for determining whether the minimum value of the output is smaller than the minimum value reference voltage; and a lock signal from the phase-locked loop circuit based on the determination result of the maximum value determining means and the determination result of the minimum value determining means. A lock determination means is provided for determining whether or not the frequency of the carrier wave included in the video intermediate frequency signal is locked. Since it is determined whether the lock signal is locked to the frequency of the carrier wave included in the video intermediate frequency signal, it is necessary to determine whether the lock signal is locked to the frequency of the carrier wave based on the average voltage in the vertical period. It disappears.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of a PLL lock detection device according to the present invention. In the figure, the difference from the conventional PLL lock detection device shown in FIG.
The reason is that 0 is set. The maximum voltage constant circuit 20 is an NPN
It consists of transistors Q1 and Q2, a capacitor C20, a maximum reference voltage 40, and a comparator 50. The transistor Q1 has a base connected to the output terminal 9, a collector connected to the power supply voltage Vcc, and an emitter connected to ground via the constant current source 22. Capacitor C20 is connected in parallel with constant current source 22 between the emitter of transistor Q1 and ground. The constant current source 22 is for discharging the charge in the capacitor C20.

The base of the transistor Q2 is connected to the maximum reference voltage 40, and the emitter is connected to the ground through the constant current source 23. The collector of transistor Q2 is connected to power supply voltage Vcc. The comparator 50 has a + input connected to a common connection point between the emitter of the transistor Q1 and the capacitor C20, and a - input connected to the emitter of the transistor Q2.

The minimum voltage determination circuit 30 includes PNP transistors Q3 and Q4, a capacitor C30, and a minimum value reference voltage 6.
0, comparator 70. The transistor Q3 has a base connected to the output terminal 9, a collector grounded, and an emitter connected to the power supply voltage Vcc via the constant current source 33. Capacitor C30 is connected in parallel with constant current source 33 between the emitter of transistor Q3 and power supply voltage Vcc. The constant current source 33 is for discharging the charge in the capacitor C30.

The base of transistor Q4 is grounded via the minimum reference voltage 60, and the collector is directly grounded. The emitter of transistor Q4 is connected to power supply voltage Vcc via constant current source 34. The comparator 70 is
+ input is the emitter of transistor Q3 and capacitor C3
0, the - inputs are each connected to the emitter of transistor Q4.

A comparator 5 is connected to one input of the NOR circuit 100.
The output of 0 is input to the other input, and the output of the comparator 70 is input to the other input. The rest of the configuration is similar to the conventional device.

Next, the operation will be explained. The operation until a video intermediate frequency signal is input to the input terminal 1, synchronously detected by the video detector 3, and the signal A is taken out to the output terminal 9 is the same as the conventional one.

Signal A is applied to the bases of transistors Q1 and Q3. The emitter potentials of transistors Q1 and Q3 change according to the voltage value of signal A.

By adjusting the current value of the constant current source 22, the maximum voltage of the signal A can be held in the capacitor C20.

On the other hand, by adjusting the current value of the constant current source 33, the minimum voltage of the signal A can be held in the capacitor C30.

Hold voltage of capacitor C20 (signal A
) is applied to the +input of the comparator 50, and the maximum reference voltage 40 is applied to the -input of the comparator 50 via the emitter follower formed by the transistor Q2. Comparator 50 determines whether the hold voltage of capacitor C20 is smaller than maximum reference voltage 40, and outputs a signal according to the determination result.

Hold voltage of capacitor C30 (signal A
) is applied to the +input of the comparator 70, and the minimum reference voltage 60 is applied to the -input of the comparator 70 via the emitter follower formed by the transistor Q4. Comparator 70 determines whether the hold voltage of capacitor C30 is smaller than minimum reference voltage 60 and outputs a signal according to the determination result.

First, when the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal, the signal A output to the output terminal 9 has the conventional waveform shown in FIG. 6, as shown in FIG. The waveform will be similar to . At this time, it is assumed that the amplitude of the video intermediate frequency signal is relatively large. As shown in FIG. 2, the maximum voltage of signal A is less than the maximum reference voltage 40 and the minimum voltage is less than the minimum reference voltage 60. Therefore, both comparators 50 and 70 output "L", and NOR
The circuit 100 receives these outputs and outputs "H". This "H" becomes a signal indicating that the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal. The switch SW1 is turned on in response to "H", and the loop time constant increases.

Next, when the oscillation frequency of the PLL circuit 2 is not locked to the frequency of the carrier wave of the video intermediate frequency signal,
The signal A output to the output terminal 9 is as shown in FIG.
The waveform is similar to the conventional waveform shown in . At this time, it is assumed that the amplitude of the video intermediate frequency signal is relatively large. As shown in FIG. 3, the maximum voltage of signal A is greater than the maximum reference voltage 40, and the minimum voltage is less than the minimum reference voltage 60. Therefore, the comparator 50 outputs "H" and the comparator 70 outputs "L".
is applied to the NOR circuit 100. The NOR circuit 100 receives these outputs and outputs "L". This “L” is PLL
This is a signal indicating that the oscillation frequency of the circuit 2 is not locked to the frequency of the carrier wave of the video intermediate frequency signal. The switch SW1 is turned off in response to "L", and the loop time constant becomes small.

Furthermore, when the amplitude of the video intermediate frequency signal is relatively small and the oscillation frequency of the PLL circuit 2 is not locked to the frequency of the carrier wave of the video intermediate frequency signal, the output terminal 9
The signal A output to has a waveform as shown in FIG. As shown in FIG. 4, the maximum voltage of signal A is the maximum reference voltage 40
The minimum voltage is greater than the minimum reference voltage 60. Therefore, the comparator 50 outputs "L", and the comparator 70 outputs "H".
” to the NOR circuit 100. The NOR circuit 100 receives these outputs and applies “L” to switch SW1 in the same way as described above. Switch SW1 turns OFF in response to “L”, and the loop time constant becomes becomes smaller.

Note that even when the amplitude of the video intermediate frequency signal is relatively small and the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal, the maximum voltage of the signal A is equal to the maximum reference voltage. 40, the minimum voltage is greater than the minimum reference voltage 60, it is determined that the lock is not present, and the same operation as the conventional device is performed.

As described above, it is determined whether the oscillation frequency of the PLL circuit 2 is locked to the frequency of the carrier wave of the video intermediate frequency signal based on the output of the maximum voltage determination circuit 20 and the output of the minimum voltage determination circuit 30. Therefore, during a short fixed period, for example, a horizontal period (64 μsec), the signal A
It is sufficient to hold the voltage of 20 msec.
), the hold period is approximately 1/300th that of the previous case. Therefore, there is no need to use a large-capacity capacitor like in the past, and when integrated, the number of external elements is reduced, and the number of terminals is reduced.

[0028]

[Effects of the Invention] As described above, according to the present invention, the device has a maximum reference voltage, receives the output from the video detector, and determines whether the maximum value of the output is smaller than the maximum reference voltage. Maximum value determining means; Minimum value determining means having a minimum reference voltage and receiving an output from the video detector and determining whether the minimum value of the output is smaller than the minimum reference voltage; and Maximum value determining means. lock determination means for determining whether or not the lock signal from the phase-locked loop circuit is locked to the frequency of the carrier included in the video intermediate frequency signal based on the determination result of the determination result of the minimum value determination means and the determination result of the minimum value determination means; Since it is determined whether the lock signal is locked to the frequency of the carrier wave included in the video intermediate frequency signal based on whether the maximum and minimum values of the output of the device are smaller than the reference voltage, There is no need to determine whether the lock signal is locked to the frequency of the carrier wave based on the average voltage. As a result, there is no need to use a large-capacity capacitor, and when integrated, the number of external elements is reduced and the number of terminals is reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a PLL lock detection device according to the present invention.

FIG. 2 is a diagram for explaining the operation of the device shown in FIG. 1.

FIG. 3 is a diagram for explaining the operation of the apparatus shown in FIG. 1.

FIG. 4 is a diagram for explaining the operation of the device shown in FIG. 1.

FIG. 5 is a circuit diagram showing a conventional PLL fully synchronous detector.

FIG. 6 is a diagram for explaining the operation of the circuit shown in FIG. 5;

7 is a diagram for explaining the operation of the device shown in FIG. 5. FIG.

[Explanation of symbols]

2 PLL circuit 3 Video detector 20 Maximum voltage judgment circuit 30 Minimum voltage judgment circuit 40 Maximum reference voltage 60 Minimum reference voltage 100 NOR circuit

Claims (1)

[Claims] 1. A phase-locked loop circuit that receives a video intermediate frequency signal and outputs a lock signal locked to the frequency of a carrier included in the video intermediate frequency signal, and receives the video intermediate frequency signal and the lock signal, Used in a video signal processing device comprising a video detector that detects the video intermediate frequency signal using the lock signal, and detects whether the lock signal is locked to the frequency of a carrier wave included in the video intermediate frequency signal. A PLL lock detection device having a maximum value reference voltage, receiving an output from the video detector, and determining whether the maximum value of the output is larger than the maximum value reference voltage. , minimum value determining means having a minimum value reference voltage, receiving the output from the video detector and determining whether the minimum value of the output is smaller than the minimum value reference voltage; and the maximum value determining means. A PLL lock detection device comprising: lock determination means for determining whether or not the lock signal is locked to a frequency of a carrier included in the video intermediate frequency signal based on a determination result and a determination result of the minimum value determination means.