JPH02260919A - In-phase detector for pll - Google Patents

Abstract

PURPOSE:To prevent a signal in a blanking period from being smoothed by installing a switching means which becomes nonconducting in correspondence with the blanking period of te output signal in a video detector and which does not transmit the signal in the blanking period. CONSTITUTION:The switching means SW2 which is turned off in the blanking period of the output signal in the video detector 3 is newly installed between a smoothing circuit 10 and an output terminal 9. The switching means SW2 consists of a differential amplifier consisting of NPN transistors Q1 and Q2, a current mirror circuit consisting of PNP transistors Q3 and Q4, a constant current source 11 and a switch SW3. The switch SW3 is turned off when the blanking signal is 'H', and is turned on when the signal is 'L'. When the switch SW3 is turned on, the base voltage of the transistor Q1 becomes equal to that of the transistor Q2. Although the signal from the video detector 3 is transmitted to the smoothing circuit 10 while the switch SW3 is in an ON- period, it is not transmitted when the switch SW3 is turned off.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a PLL fully synchronous detection double-wing built in a television receiver or VTR capable of receiving a transmitted signal of the SECAM-L system, for example. Regarding, especially that P
The present invention relates to a PLL synchronization detection device that detects synchronization of an LL circuit.

[Conventional technology]

In recent years, PLL (phase-locked loop) fully synchronous detectors with good linearity have come into widespread use as video detection devices. FIG. 3 is a block diagram showing the configuration of a conventional PLL fully synchronous detector. A video intermediate frequency signal whose amplitude is limited to a constant by a video intermediate frequency signal amplifier (not shown) is transmitted to the PLL circuit 2 through an input terminal l. The signal is applied to the video detector 3.

The PLL circuit 2 operates as a carrier extraction circuit, and the phase comparator 4. Low-pass filter (hereinafter abbreviated as LPF) 5. It consists of a voltage controlled oscillator (hereinafter abbreviated as vCO) 5, a shifter 7 that advances the phase of the output of the VCO 6 by 45 degrees, and a shifter 8 that delays the phase of the output of the VCO 6 by 45 degrees. The output of the transfer device 7 is compared in phase.The LPF 5 includes a resistor R1, a capacitor CI, a resistor R
2 and R3 in series, and removes unnecessary harmonic components from the output of the phase comparator 4. VCO6 is resistor R
1 and the capacitor C1, and as is well known, the oscillation frequency changes according to the output of the LPF 5. This oscillation frequency is locked to a frequency equal to the carrier wave of the video intermediate wave signal input to the phase comparator 4. As is well known, the phase of this oscillation output is shifted by 90 degrees with respect to the input to the phase comparator 4. Therefore, by shifting the phase by 90 degrees by the shifter 7. The input signal is the carrier wave and frequency of the video intermediate frequency signal,
The signal also matches the phase. This signal and the video intermediate frequency signal are multiplied by the video detector 3 to perform video synchronous detection, and the video synchronous detection output is taken out from the output terminal 9.

By the way, in the PLL fully synchronous detector, increasing the loop time constant of the PLL circuit 2 improves the purity of the carrier wave extracted by the PLL circuit 2, but narrows the pull-in range. In order to optimize the relationship between the purity of the extracted carrier wave and the pull-in range, it is determined whether the oscillation frequency of the PLL circuit 2 is synchronized with the carrier frequency included in the video intermediate frequency signal, and the loop is activated according to the determination result. I am trying to change the time constant. That is, smoothing circuit 10° comparator 11. A switch SW1 is provided. Smoothing circuit 10
is connected between the output terminal 9 and the output terminal of the comparator 11, and smoothes the signal from the output terminal 9. The comparator 11 is connected to the reference voltage ref' to the human power, and the signal level to the - human power is equal to the reference voltage V.
If it is larger, it is determined that it is asynchronous and outputs "L", and if it is smaller, it is determined that it is synchronized and outputs "H". Sui Sochi SW
I is connected to the common connection point of resistors R2 and R3, and comparator 1
In response to “L” from 1, ONL goes “H”.

Turns off in response to. Switch SWI 0N10FF
As a result, the loop time constant of the PLL circuit 2 changes.

Now, if the video intermediate frequency signal is a negatively modulated signal,
When the oscillation frequency of the PLL circuit 2 is synchronized with the carrier frequency of the video intermediate frequency signal, a signal as shown in FIG. 4 is outputted to the output terminal 9. This signal is smoothed by a smoothing circuit 10 and applied to the comparator 11 as an average voltage. Average voltage.

The magnitude relationship between the reference voltage V and the no-signal voltage is the 4th ref.
' As shown in the figure. That is, since the average voltage is smaller than the reference voltage V, it is determined that they are synchronized, and the comparator 11 outputs "H". switch SW
1 is turned off in response to this "H", the loop time constant becomes larger, the pull-in range becomes narrower, and the purity of the carrier wave extracted to the PLL circuit 2 improves.

On the other hand, when the oscillation frequency of the PLL circuit 2 is not synchronized with the carrier wave of the video intermediate frequency signal, a signal from which the carrier wave has not been removed is output to the output terminal 9, as shown in FIG. Since this signal is vertically symmetrical as shown in FIG. 5, its average voltage is equal to the no-signal voltage. As shown in FIG. 4, the no-signal voltage is higher than the reference voltage V.sub.2. Therefore, it is determined that there is no synchronization, and the comparator 11 outputs "L". The switch SW2 turns ONL in response to this "L", and as a result, the loop time constant becomes smaller, the pull-in range becomes larger, and the oscillation frequency of the PLL circuit 2 becomes more likely to be locked to the carrier frequency of the video intermediate frequency signal.

[Problem to be solved by the invention]

However, when detecting a positively modulated signal such as the SECAM-L method, the video detection output becomes as shown in Figure 6, and the difference between the average voltage and the reference voltage vref becomes small, so the input terminal 1 If the level of the input signal is low, the average level will also be low, and it may be incorrectly determined that the signals are asynchronous even though they are synchronized. On the other hand, if the reference voltage ■ is increased in order to increase the difference between the average voltage and the reference voltage V, the difference between the voltage at the time of no signal and the reference voltage V becomes smaller, and ref noise etc. causes errors in synchronization and synchronization during non-synchronization. There was a problem with the judgment.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a PLL synchronization detection device that does not malfunction due to the magnitude of input signals or the influence of noise.

[Means to solve the problem]

A PLL synchronization detection device according to the present invention includes a phase-locked loop circuit that receives a video intermediate frequency signal and outputs a lock signal locked to the frequency of a carrier included in the video intermediate frequency signal, and a video intermediate frequency signal and a lock signal. The present invention is used in a video detection device having a video detector that detects a video intermediate frequency signal using a lock signal to detect whether the oscillation frequency of the PLL circuit is synchronized with the carrier frequency of the video intermediate frequency signal. a switching means connected to the video detector, which becomes non-conductive in response to a blanking period of the output signal of the video detector, and does not transmit a signal during the blanking period; and a switching means connected to the switching means; A smoothing circuit smoothes the output signal of the video detector given through this switching means, one input is connected to the smoothing circuit, the other input is given a reference voltage, and the output of the smoothing circuit is compared with the reference voltage. Accordingly, the present invention includes a comparison circuit for determining whether or not the oscillation frequency of the phase-locked loop circuit is synchronized with the carrier frequency of the video intermediate frequency signal.

[Effect]

The switching means in this invention becomes non-conductive corresponding to the blanking period of the output signal of the video detector and does not transmit the signal during the blanking period, so that the signal during the blanking period is not smoothed and the SECAM -L
Even in the case of a positively modulated video intermediate frequency signal as in the method, the difference between the base 4m voltage and the average voltage of the output signal of the video detector does not become small.

〔Example〕

FIG. 1 is a block diagram showing an example of the configuration of a PLL synchronization detection device according to the present invention. In the figure, the difference from the conventional device shown in FIG.
This is because a switching means SW2 for FF is newly provided. The switching means SW2 is an NPN transistor Ql.

A differential amplifier consisting of Q2, a PNP transistor Q3,
Q4, a current mirror circuit, a constant current source 11, and a switch SW3. The transistor Q1 has its base connected to the smoothing circuit 10 and its own collector, and its emitter connected to the emitter of the transistor Q2. The base of the transistor Q2 is connected to the output terminal 9. A common emitter connection point of the transistors Ql and Q2 is connected to a switch SW3 via a constant current source 11. A blanking signal is given to the switch SW3, and in response to "H"/'L" of this signal, the switch SW3 changes to 0FF10.
Do N. The emitter of the transistor Q3 is connected to the power supply voltage Vc.
c, the collector is connected to the collector of the transistor Q2, and the base is connected to its own collector. The transistor Q4 has an emitter connected to the power supply voltage Vcc, a collector connected to the collector of the transistor Q1, and a base connected to the transistor Q.
3 bases, respectively. The other configurations are the same as the conventional device.

Next, the operation will be explained. The operation from inputting a video intermediate frequency signal to the input terminal 1, synchronously detecting it at the video detector 3, and taking it out to the output terminal 9 is the same as in the conventional system.

Next, regarding the operation of the switching means SW2, SECA
A case will be described in which a positively modulated video intermediate frequency signal such as the M-L method is detected.

The signal given from the video detector 3 to the switching means SW2 is a signal as shown in FIG. 6, which is similar to the conventional one. On the other hand, switch SW3 included in switching means SW2
A blanking signal as shown in FIG. 2 is applied to the switch SW3, and the switch SW3 is turned 0FFL when the blanking signal is "H" and turned ON when the blanking signal is "L". When the switch SW3 is turned on, the base voltage of the transistor Q1 becomes equal to the base voltage of the transistor Q2, and the signal from the video detector 3 is transmitted to the smoothing circuit 10 while the switch SW3 is on, but when the switch SW3 is turned off, the signal is transmitted. Not done. In other words, what is transmitted to the smoothing circuit 1o is the true video signal obtained by removing the blanking period signal from the output signal of the video detector 3. Therefore, as shown in FIG. 2, the average voltage applied to the comparator 11 becomes smaller by the amount by which the signal during the blanking period is removed, and the reference voltage V
and the difference between the average voltage becomes larger. Therefore, even if the level of the er input signal is small, the oscillation frequency of the PLL circuit 2 is not erroneously determined to be asynchronous even though it is synchronized with the carrier frequency of the video intermediate frequency signal as in the conventional case. In addition, since the difference between the reference voltage Vr8f and the average voltage is large as described above, it is no longer necessary to increase the reference voltage Vrer in order to increase the difference between the two voltages as in the past, and as a result, noise etc. can cause problems in the PLL circuit. The oscillation frequency of No. 2 is no longer erroneously determined to be synchronized with the carrier frequency of the video intermediate frequency signal even though it is not.

Incidentally, in the above embodiment, the case where the switching means is constituted by an analog switch using a differential amplifier has been explained, but the output signal is set to 0FFL corresponding to the blanking period of the output signal of the video detector 3, and the analog signal is set to 0FFL at other times. Any switching means may be used as long as it can transmit the following.

〔Effect of the invention〕

As described above, according to the present invention, since the switching means is provided which becomes non-conductive corresponding to the blanking period of the output signal of the video detector and does not transmit the signal during the blanking period, unlike the SECAM-L method, Even if a video intermediate frequency signal that is positively modulated is applied to the blanking period, the signal during the blanking period is not smoothed. As a result, the difference between the reference voltage applied to the comparator and the average voltage will not become small, and malfunctions will not occur due to the magnitude of the input signal or the influence of noise.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the PLL synchronization detection device according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of the device shown in FIG. 1, and FIG. 3 is a conventional PLL synchronization detection device. A block diagram showing the configuration of the detection device, and FIGS. 4 to 6 are waveform diagrams for explaining the operation of the conventional device. In the figure, 2 is a PLL circuit, 3 is a video detector, SW2
is a switching means, 10 is a smoothing circuit, 11 is a comparator,
SWI is a switch. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A phase-locked loop circuit that receives a video intermediate frequency signal and outputs a lock signal locked to the frequency of a carrier included in the video intermediate frequency signal, and the video intermediate frequency signal and the lock signal. and is used in a video detection device having a video detector that detects the video intermediate frequency signal using the lock signal, and whether or not the oscillation frequency of the phase-locked loop circuit is synchronized with the carrier frequency of the video intermediate frequency signal. a PLL synchronization detection device for detecting the PLL synchronization detection device, comprising: switching means connected to the video detector and becoming non-conductive in response to a blanking period of the output signal of the video detector; a smoothing circuit for smoothing an output signal of the video detector provided via a switching means; one input is connected to the smoothing circuit, the other input is provided with a reference voltage, and the output of the smoothing circuit and the reference voltage are connected to each other; and a comparison circuit that determines whether the oscillation frequency of the phase-locked loop circuit is synchronized with the carrier frequency of the video intermediate frequency signal by comparing the PLL synchronization detection device.