JPS59134896U - monitor device - Google Patents
monitor deviceInfo
- Publication number
- JPS59134896U JPS59134896U JP2540783U JP2540783U JPS59134896U JP S59134896 U JPS59134896 U JP S59134896U JP 2540783 U JP2540783 U JP 2540783U JP 2540783 U JP2540783 U JP 2540783U JP S59134896 U JPS59134896 U JP S59134896U
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- group
- address signal
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す構成図、第２図は出力
部の動作を説明するための詳細図である。
Ａ工〜Ａｎ・・・・・・入力基板、Ｂ、、 Ｂ２・・・
・・・入力信号端子群、Ｃ・・・・・・アドレス信号線
、Ｄ、 Ｅ・・・・・・状態信号線、Ｆ・・・・二中央
制御装置、Ｇ１． Ｇ１６・・・・・・出力基板、Ｈ１
〜Ｈ１２８・・・・・・出力信号線群、■・・・・・・
アドレス・データ信号線、Ｊ、 Ｋ、 Ｌ、 Ｍ、 Ｎ
・・・・・・ストローブ信号線。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a detailed diagram for explaining the operation of the output section. A-An... Input board, B, B2...
... Input signal terminal group, C ... Address signal line, D, E ... Status signal line, F ... Two central control units, G1. G16...Output board, H1
~H128... Output signal line group, ■...
Address/data signal lines, J, K, L, M, N
...Strobe signal line.
Claims (1)
装置であって、入力側に複数の群よりなる入力信号端子
群が接□続され、出力側に、前記入力信号端子群に対す
る共通のアドレス信号が入力されるアドレス信号線と、
前記アドレス信号により指定された入力信号端子群の中
の所定端子の入力状態を現わす状態信号を出力しかつ補
記入力信号端子群に対応する数よりなる状態信号線が接
続され、これらアドレス信号線および状態信号線が前記
中央制御装置の入力側に接続される入力基板を１つまた
はそれ以上有することを特徴とするモニター装置。A monitor device that inputs signals dispersed outside to a central control device, in which a group of input signal terminals consisting of a plurality of groups is connected to the input side, and a common address signal for the group of input signal terminals is connected to the output side. an address signal line into which
A state signal line representing the input state of a predetermined terminal among the input signal terminal group designated by the address signal is output, and the number of state signal lines corresponding to the supplementary input signal terminal group is connected, and these address signal lines and one or more input boards, the status signal lines of which are connected to the input side of the central control unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2540783U JPS59134896U (en) | 1983-02-22 | 1983-02-22 | monitor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2540783U JPS59134896U (en) | 1983-02-22 | 1983-02-22 | monitor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134896U true JPS59134896U (en) | 1984-09-08 |
Family
ID=30156396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2540783U Pending JPS59134896U (en) | 1983-02-22 | 1983-02-22 | monitor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134896U (en) |
-
1983
- 1983-02-22 JP JP2540783U patent/JPS59134896U/en active Pending
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