JPS59134823A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to integrate elements by a method wherein Pt is adhered over the entir surface of a substrate and heat-treated, a PtSi is formed at an Si region, and then a Pt layer not formed is utilized for the wiring from the Si region. CONSTITUTION:The N<-> type Si substrate 1 is isolated with an oxide film 5 by a conventional method, and a gate electrode 9 and wiring layers 13 and 26 of poly Si are formed via a gate insulation film 15. It is covered with an SiO2 34, a resist mask 35 is applied, and then SiO2 films 20, 23, 10 and 11 are formed by reactive ion etching. The PtSi's 6, 7, 8, 14 and 24 are formed by adhering the Pt 36 over the entire surface and heat-treating it, and only the Pt is etched with aqua regina by applying the resist 37. Next, an Al wiring 28 is formed by covering with a PSG22 and opening a window. This constitution enables to obtain the wiring directly from the source and drain by self-alignment and then unnecessitates the mask alignment for forming a connection hole, resulting in the improvement of the connection accuracy of an electrode by that and in the increase of the integration degree.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device 2. and its manufacturing method,
In particular, the present invention relates to a semiconductor device using a silicide layer as a wiring layer and a method for manufacturing the same.

MlSlS used as an insulated gate field effect transistor (hereinafter simply referred to as M5FET) circuit element
As a technology to increase the operating speed of molded conductor integrated circuits,
a gate electrode made of polycrystalline silicon of a circuit element, and
A technology in which the source and drain regions formed on a single-crystal silicon substrate are each made of platinum silicide (PTST) and the PTST layer with sufficiently low resistance is used as an electrode has already been reported in Nikkei Electronics Vol. 6, published on September 1, 1980.
Known on page 2. Furthermore, this gate electrode, polysilicon (po1+-
81) As a method for converting wiring and source and drain regions into 1Ptsi, goo)! The applicant has developed a technique for separating the silicide layers formed in the gate electrode and the source/drain regions from each other by an insulating layer formed on the extreme side surface using a special method of reactive ion etching (R-E). The patent application No. 56-1.57510 has already been filed.

Compared to the conventional technology in which the gate electrode is formed using polycrystalline silicon and only the entire diffusion layer of the source and drain, Kowara's technology can sufficiently reduce the resistance, and therefore the access time etc. of the memory cell can be reduced. The switching time can be reduced and higher speeds can be achieved.

However, in the conventional platinum silicide technology, divided silicon regions such as polycrystalline silicon gate electrodes, wiring layers extending from the gate electrodes, silicon source and drain regions, etc. are transferred to the semiconductor substrate. After being formed on the main surface in advance, a platinum silicide-forming metal layer is deposited on the entire main surface of the semiconductor substrate, and is thermally treated to form a platinum silicide layer in the partitioned silicon region. After that, the platinum layer f covering other parts other than the part where the platinum silicide layer is formed, such as on the source and drain regions, is removed by etching, making full use of the difference in the etching process between the platinum silicide layer and the platinum layer. It is something to do.

Therefore, in order to extend the wiring layer from the surface of the source and drain regions where platinum silicide is formed, contact holes are formed in the insulating film over the source and drain regions. Through,
Providing a third wiring metal such as aluminum has been practiced.

For this reason, in the conventional method of forming contact holes in the insulating film of the source and drain regions and removing wiring layers of aluminum or the like, a mask for forming the contact holes,
In addition, alignment work with the aluminum wiring layer type mask is required, and the source/drain region must be designed to be large considering the allowance for these double mask alignments. This has the disadvantage that the area occupied by the circuit elements becomes too large and high integration density cannot be achieved.

An object of the present invention is to provide a semiconductor device including an insulated gate field effect element having a wiring structure suitable for high speed and high integration, and a method for manufacturing the same.

According to the present invention, a substrate main body including a silicon region such as a gate electrode existing on a thick field insulating film, or a silicon region of a source and a drain existing in an HFC area limited by a field insulating film. A silicide-forming metal layer is entirely formed on the surface, a silicide layer is formed on the contact surface with the silicon region, and a part of the remaining silicide-forming metal layer on which the silicide layer could not be formed is used as a wiring layer. . In this case, by forming a silicide-forming metal layer extending from a silicide layer such as a source or drain as a wiring, it is possible to draw out the wiring directly from the element region without forming a contact hole. This increases the degree of integration. 6. Better, by depositing a silicide-forming metal layer on the entire surface of the substrate, and siliciding the lower layer of the metal layer where phosphorus is present by heat treatment. The shape of the silicide layer is divided corresponding to the silicon semiconductor region, and the metal layer on which the silicide layer is not formed is formed as a wiring extending from the silicon region where the silicide layer is formed. Second, the conventional process of forming contact holes is omitted, and the area of mask displacement that must be taken into consideration when forming contact holes is eliminated, and the degree of integration is obtained by that area.

In addition, in order to completely omit the formation of contact holes, the wiring spacing in the same layer is reduced by the area for forming the contact holes, and the polycrystalline silicon layer formed at the same time as the polycrystalline silicon layer for forming the gate electrode. By using the layer as a cross wiring with a silicide-forming metal wiring layer, cross wiring is facilitated and elements are integrated.

Further, in the manufacturing method of the present invention, after forming a silicide-forming metal layer on the entire surface, a region where the lower layer of the metal layer is silicon is silicided, and the silicided portion m of the metal layer and the silicide fossil are separated. The difference between etching the car and the parts is fully utilized (the wiring pattern is formed.

The silicide-forming metal used in the present invention means a metal such as platinum (Pt), molybdenum (MO), tungsten (W), etc., which is obtained by forming silicide with silicon.

Hereinafter, the present embodiment will be specifically described with reference to the sections. FIG. 1 shows a top view of a semiconductor device according to the invention used as a M5FETi circuit element. 1st
Area A in the figure is the part where the M-5FKT is configured, B is the area where the M-5FET and cross wiring are configured, and C is the area where the M-5FKT is configured.
Figures 2, 3 and 4 respectively show the parts where the cross wiring is constructed.
FIG. 3 shows cross-sectional views along lines Y-Y' and z-z', respectively.

1 to 4, reference numeral 1 indicates an N-type silicon semiconductor substrate, and 2 and 3 indicate P-type source and drain regions. 5
is a thick field oxide film consisting of silicon oxide (sho). 15 is a thin gate oxide film made of silicon oxide. 9.13.26 are polycrystalline silicon electrodes and wiring layers formed at the same time. 4.6.7.8.12 is MI8FF! in area A. TG1. , a platinum layer formed simultaneously with .

These platinum layers form a base silicon layer and a platinum silicide layer in a portion 6.7.8 that has a silicon layer as a base layer, and a wiring layer is formed by a single layer of platinum in the other portion 4.12. is forming.

Similarly, 14.16.17.18.19.20.2
1 and 24 in area B, above 4.6.7.8
．． The platinum layer was formed at the same time as 12, and portions 14, 16, 17, and 24 of this platinum layer form an underlying silicon layer and a platinum silicide layer.

The other portions 18, 19 and 21 constitute a wiring layer made of a single layer of platinum. Reference numerals 20 and 23 are silicon oxide interlayer insulating films used for the cross wiring portion.

25 and 27 are platinum layers formed in region C, and these form intersecting wiring.

That is, the platinum wiring layer 25 is formed to cross the polycrystalline silicon layer 26 formed under the interlayer insulating film 23, and the platinum layer 27 is electrically conductive at both ends of the polycrystalline silicon layer 26. As a result, the wiring 27
can intersect with the distribution +1!25. Connections between both ends of the polycrystalline silicon layer 26 and the platinum layer 27 are formed by both ends. This is done through a platinum silicide layer. That is, a platinum silicide layer is formed in region 29.

22 is a phosphosilicate glass film (P2O film).

Reference numeral 28 denotes an aluminum wiring layer electrically connected to the platinum wiring layer 25 through a contact hole in the phosphosilicate glass film.

According to such a semiconductor device, 7'CM is formed in region A.
As in ISFETQ, the platinum layer formed with the source and drain regions 2, 3 and platinum silicide is spread over the thick insulating film 5 from the source and drain regions to the wiring layer 4,
12 and extends as L7. That is, it is used as a wiring layer on a thick field insulating film.

As is clear from the cross-wiring structure in region B, after forming an interlayer insulating film 20 on the polycrystalline silicon layer formed in advance in the area where cross-wiring is required, a platinum layer 21, By forming 14 and 24, it is possible to easily form a cross wiring. In this case, the laterally extending arrangement 11J14.24, except at the intersections, can be a platinum silicide layer.

Furthermore, as shown in region C, it is possible to use a structure in which a lower wiring layer of a polycrystalline silicon layer is used only at the crossing portion, and platinum layers are used for the other wiring portions, as the crossing wiring.

Below, the method for manufacturing a semiconductor device of the present invention is illustrated in FIGS. 5 to 2.
This will be explained with reference to FIG.

(Formation of field insulating film) As shown in FIG. )3
0't-form. This is a silicon nitride film (5L3N) when forming a field insulating film.

This is to prevent crystal defects from occurring on the surface of the silicon substrate 1 due to the difference in thermal expansion coefficient between the film 31 and the silicon substrate 1.

On this oxide film, an insulating film that does not allow oxygen to pass through (oxidation-resistant film),
9, a silicon nitride group (SiiN4 film) 31 is formed by, for example, a vapor phase chemical reaction method (OVD method) as shown in FIG.

Then, the photoresist film 32 is replaced with a silicon nitride film (ε'
i<N<k) 31, and using this photoresist film 32 as a mask, the silicon nitride 1 (Si, N(gd)) 31 is etched using highly precise plasma etching to form field insulation. A female mask for film formation is formed as shown in FIG.

After removing 32 photoresist films, the surface of the silicon substrate 1 is thermally oxidized to form a thick silicon oxide film (s1o2 film) 5, as shown in FIG.

This is called a field insulating film for insulating adjacent MIS FETs.

(Surface butyridization removal process) After removing the silicon nitride film (5i31J, film) 31'ii, for example, using hot phosphoric acid (H*Po4) 1, silicon oxidation is performed to obtain a clean gate insulating film. film(
StO, film) 30 is removed. For example, hydrofluoric acid (HF'
Etch a thin layer of silicon nitride (S) on the entire surface using
The surface of the silicon substrate 1 in the portion where the field insulating film 5 is not formed except for the iqN* film 30 is exposed as shown in FIG.

(Gate formation process) As shown in Figure 1O, silicon oxide film (StO2 film)
After removing 30, a gate insulating film which is an insulating film of the gate portion, for example, a silicon oxide film (Boo□ film) 15?
11 - Form. First, in order to obtain a clean Kate insulating film, the surface of the silicon substrate 1 is thermally oxidized again to form a thin silicon oxide film (not shown). Furthermore, this thin oxide film is removed and the surface of the clean silicon substrate 1 is coated with, for example,
A silicon oxide film 15 for an insulating film is formed by thermal oxidation at a high temperature in an oxidizing atmosphere. This silicon oxide film 15 serves as a gate insulating film for all MISFETs formed on the silicon substrate l.

Next, a polycrystalline silicon film is formed on the entire surface of the gate insulating film 15 and the field insulating film 5 using, for example, the CVD method. - This will be the lower layer wiring where the gate electrode and wiring line cross. In order to remove the polycrystalline silicon film in areas other than the regions where the gates are to be formed, a photoresist film 33 is selectively formed, and the polycrystalline silicon films 9, 13, .
26'r Etch as shown in FIG.

(Formation of source and drain) As shown in Fig. 12, the P-channel MI'5FET
In order to form P-type source and drain regions in the formation region, P-type impurity ions, such as boron, are implanted by ion implantation using the polycrystalline silicon layer 9.13 and the selectively formed photoresist film 33 as a mask. (B) P the ion
1. After that, 33 photoresist films are removed, thermally diffused, and P
Source/drain 2.3 of channel MO8 formation region
form.

Note that the source/drain 2.3 of this P channel MO8 formation region is formed by forming a thin silicon oxide PIiL (stoz) in the active region after sidewall formation as shown in FIG.
(win) 'r shadow formation, P-type impurity ions may be implanted and thermally diffused.

(Formation of sidewalls and insulating films for multilayer wiring) In order to form sidewalls and insulating films for multilayer wiring, a silicon oxide film (SiOg film) 34 or a phosphosilicate glass film (PSG film) is formed on the entire surface. Furthermore, in order to form an insulating film for multilayer wiring, a photoresist film 35 is selectively formed as shown in FIG. Silicon oxide 11 (8
The 10g film) 34 is etched by a reactive ion etching method (RtE method), but in this case, due to the isotropic nature of the reactive ion etching method (R1K method), as shown in FIG. Absolute #l! Sidewalls 10.11 of silicon oxide (5t02) are completely formed on the sides of the glands 20.23 and the polycrystalline silicon film of the gate portion. This sidewall serves as an insulating region between the gate electrode and the source and drain electrodes.

(Step of forming silicide) When the sidewalls and multilayer wiring are completely formed, as shown in FIG. 15, a silicide forming metal, for example,
Thirty-six layers of platinum (PT) are deposited on the entire surface, and the whole is heated in an oxygen atmosphere. - polycrystalline silicon layer,
and platinum (at)N with a crystallized silicon layer underneath.
36, a platinum silicide layer is formed. Platinum (PT) on an insulating film such as a field insulating film is left as is, and the structure as a whole is formed as shown in FIG. Tsumashi,
At this point, a platinum silicide layer (PtS) is placed on top of the polycrystalline silicon layer 9.13.
i-layer) 7.14.24 are formed, and Kate t@iG has a two-layer structure. In history, source Sumire'eIis,
Also in the drain electrode, a platinum silicide layer (pt
stJ everyone) 6.8 is formed.

(Step of forming wiring) Next, wiring is formed in the selected π portion of the platinum layer (PT layer) that was not silicided in the above process. In this method, the wiring layer 412.2 is masked as shown in FIG.
5'(r form.

If you use a chemical etching method that etches only the platinum m (Pt layer) without etching the platinum silicide layer (PtSi layer), the so-called etchant whose etching intensity differs depending on the material, for example, using aqua regia, can be used for masking. ,
It is not necessary to carry out this process on parts that have been made into platinum silicide (PTST).

FIG. 18 shows a cross-sectional view after etching, and the platinum layer (Pt layer) 21 used as wiring,
The platinum layer (PT layer) 25 intersects with the wiring layer 14 from the gate and the arrangement layer 26 from the other direction, respectively.

According to this method, the end portion of the mask 37 applied to the platinum layer (PT layer) may be formed so that a portion thereof overlaps the portion where the platinum silicide layer is formed. , Strict accuracy is not required for mask alignment with the silicon regions such as the source and drain of the mask 37.

(Formation process of aluminum wiring) In order to stabilize the surface of the formed semiconductor, a phosphosilicate glass film (PSA film) 22 is formed using a vapor phase chemical reaction method C0V.
Method D) is used to form the entire surface.

Furthermore, this phosphosilicate glass film (PsG film) 22
In order to make the undulations gentler, the entire structure is heated in a phonetic atmosphere to eliminate protrusions. Next, a two-layer photoresist film (
(not shown) is selectively formed, and using this as a mask, the phosphosilicate glass film (PsGh) 22 is etched to form a contact hole for aluminum wiring (first
Figure 9).

The reason why two layers of photoresist film are formed and etched is to prevent unnecessary etching due to non-uniformity of the photoresist film.

Next, 28 aluminum layers are formed on the entire surface by vacuum evaporation, and a photoresist film is selectively formed.
Using this as a mask, the aluminum layer 28 is etched to form wiring lines 28 as required, as shown in FIG.

Finally, passivation is applied as necessary to complete the process.

In the semiconductor device constructed and manufactured as described above, the gate electrode G is formed by forming the polycrystalline silicon layer 9 and the platinum silicide layer (
The source/drain electrodes are made of a platinum silicide layer (ptSi layer) 6.8, while the wiring layer 4.12.25 is connected to the gate electrode and the source/drain electrodes. Since it is composed of a single platinum layer (PT layer), the following effects can be obtained.

(1) The wiring layer connected to the gate electrode and the source/drain electrodes uses the same metal layer used to make each electrode into a silicide. There is no need to form contact holes. Therefore, there is no need to consider errors caused by mask alignment for making contact holes.
The degree of integration can be improved by that area. As shown in FIG. 21, even if a mask misalignment occurs and the wiring 47' is displaced from the position 47 during wiring formation for the source region 45, the wiring 47' and a part of the silicon region 45 will not come into contact with each other. For example, there is an advantage that electrical connection is possible.

Furthermore, in the past, double mask alignment was required for gate electrode wiring and source/drain regions, one for forming contact holes, and the other for wiring in contact with the contact holes. It was necessary to increase the wiring width or the source/drain regions in consideration of contact errors. However, in the present invention, since the wiring is obtained directly from the electrode in a self-aligned manner, there is no need for 472 alignment for contact hole formation, which increases the contact precision between the wiring and the electrode, and reduces the wiring width. Since it can be made thinner, higher integration can be achieved. Figure 22,
And, Fig. 23 shows the prior art and M-type 5FET, respectively.
This is an example of setting f#,' using the present invention.

When the wiring noise is 3μm and the mask deviation is 1.5μm,
According to the prior art, the contact hole 37 is made 2 μm square, and the end of the wiring is made 6 μm wide so as to completely cover the contact hole due to mask slippage for forming the contact hole and mask misalignment for forming the wiring layer. to form. In the source/drain regions, the ends of the wiring formed in a rectangular shape are connected to each other. It is necessary to provide a large area so as not to come into contact with the contact hole, and also to take into account the margin due to mask misalignment of the wiring end and the contact hole. M Engineering SFI was formed in this way! The area of iT is 20
X23 μm. In addition, if similar M engineering SF]lCT'i is formed according to the present invention, since no contact hole is formed, there is no need to consider the mask scratches, and the wiring ends are located close to the silicon layer in the source/drain region. It is sufficient that they are in partial contact, and there is no need to make the end part wide in consideration of the mask gap and contact hole as in the prior art. The formation area of the 1fiT M-type SF formed by the present invention is 6 x 18 μm, which is 2 µm compared to the conventional technology.
It is possible to achieve a one-fold increase in integration.

Furthermore, with respect to wiring spacing, integration is similarly achieved; in conventional technology, as shown in Figure 24, the wiring spacing must be widened to account for the bulge in the contact hole forming area. However, in the present invention, since contact holes are not formed in the first layer of wiring, the intervals are narrowed as shown in FIG. 25. For example, the wiring width is 3
In terms of .mu.m, conventional technology has a wire spacing of approximately 9 .mu.m, but according to the present invention, wiring can be performed with a wiring spacing of approximately 7 .mu.m, resulting in a high degree of integration.

(2) When forming the wires 4, 12, 25, and 27, it is possible to adopt a method that takes advantage of the difference in etching effect between a metal silicide layer and a metal layer on which no silicide is formed. Only the metal layer needs to be masked, and masking of the complex and fine gate electrode is unnecessary, making processability easier.

(3) Conventionally, since the first layer of wiring is first formed on the PSG film, in multilayer wiring, the thickness of the interlayer insulating film becomes thick, making it easy for the wiring to break. However, in the present invention, the first layer of wiring is on the field insulating film, and the thickness of the interlayer insulating film in multilayer wiring can be made thinner, so it is possible to reduce the noise caused by such step breakage. can. Furthermore, at the points where the platinum (PT) wiring intersects, a platinum silicide layer (PtS1 layer) formed at the same time as forming the polysilicon of the gate electrode can be used to mask the platinum (Pt) wiring once. It can be a two-layer wiring.

(4) a gate electrode made of polycrystalline silicon, and
The source and drain diffusion regions made of crystals are
Since it is made of platinum silicide, wiring resistance can be lowered and higher speeds can be realized.

As mentioned above, in the example, the electrode is silicided,
Platinum CP1 as silicide forming metal used as wiring:
) was used, but molybdenum (Mo
), tungsten (W), and other silicide-forming metals can be used. In this case as well, effects similar to those described above can be obtained.

In addition, although a P-channel type semiconductor was used in the example, N
Even in the case of a channel type semiconductor, effects similar to those described above can be obtained.

In the above embodiment, the interlayer insulating film 20.23
Although a silicon oxide film is used as the insulating film, a phosphosilicate glass film (PEG film) can also be used as another insulating film.

Furthermore, in the polycrystalline silicon layer used as the wire layer or the wire layer, there are
Impurities can be introduced and used in a variety of applications. Furthermore, in this case, it is also possible to form the resistor in such a way that impurities are not locally introduced into the polycrystalline silicon layer. For example, in the above-described embodiment, the polycrystalline silicon layer under the interlayer insulating film 20 can be used as a resistor without introducing impurities into it.

The present invention provides an MIEl type memory device, a logic circuit device MI
It can be applied to all S type 1 semiconductor devices.

The present invention can be modified in various ways without departing from the gist thereof.

[Brief explanation of the drawing]

1 is a plan view showing a semiconductor device of the present invention, FIG. 2 is a sectional view taken along line xx' in FIG. 1, and FIG. 3 is a sectional view taken along line Y-Y' in FIG. 1. Figure 4 shows the z − of Figure 1.
Cross-sectional view along the z' line, 22-23 Figure 18 Comparison between the prior art and the present invention (active area) A19, Figures 24-25 18 Comparison between the prior art and the present invention (wiring) t¥-tak1tn1゛Salt filter O 1...Silicon (Sl) substrate, 2.3...Diffusion region, 4.12.18.19. 21.25.27...Platinum (Pt'l wiring, 5...Field insulating film (8102
membrane), 6.17...Platinum silicide (ptst) i (
source electrode), 7.14...Platinum silicide (pts
l) layer (gate as pole), 8. -16...Platinum silicide (ptSi) scrap (drain electrode 8ii), 9.13.2
6... Polysilicon layer, 1O111... Silicon oxide layer (side wall), 15... Gate insulating film (S
10□兓), 20.23...Silicon oxide film (S10
□ film), or P2O film, 22... silicon oxide film (
sto, membrane), 24.29...Platinum silicide (pt
st) layer (wiring), 28...aluminum wiring, 3
0...Silicon oxide film (S10) film), 31...Silicon nitride film (SiqM4@), 32.33.35.3
7... Photoresist film, 34... Silicon oxide film (Si○, film), or P2O film, 36... Platinum (Pi) layer, 37... Contact hole, 38...
Drain head mounted (conventional technique), 39... Source region (conventional technique), 40... Gate Goose@! (prior art), 41
...Aluminum wiring, 42...Oxide insulating film, 43
... Gate electrode (present invention), 44... Drain region (present invention), 45... Source region (present invention), 46.
...Oxide insulating film, 47...Platinum (PT) wiring layer. Figure 1' / Otsuσ Figure 3, zF Figure 4 Figure 5 / Figure 6 / Figure 7 / Figure S Figure 9, 'f Figure 11 / Figure 12 Figure 13 Figure 14 Fig. 15 Fig. 16 Fig. 17 Fig. 18 Fig. 19 Fig. 20 Fig. 21 Fig. 47' Fig. 22 Fig. 23

Claims (1)

[Scope of Claims] 1. A silicon semiconductor region having a surface partitioned into a part of the main surface of a semiconductor substrate, and the contacting surface of the silicon semiconductor region that is in contact with at least a part of the surface of the silicon semiconductor region. and a silicide-formed metal wiring layer extending from the first part to the other part of the main surface of the semiconductor substrate on an insulating film, and the silicide-forming metal is formed in the first contact part of the silicon semiconductor metal region. A semiconductor device characterized in that it is formed entirely of silicide layers. 2. The semiconductor device according to claim 1, wherein the silicon semiconductor region is a polycrystalline silicon layer formed on an insulating film across the main surface of the semiconductor substrate. 3. The front n-Pi silicon semiconductor region is formed from a semiconductor region formed in the semiconductor substrate, and the surface of the front MC silicon semiconductor region is defined by a portion exposed from the # film covering the main surface of the semiconductor substrate. A semiconductor device according to claim 1, characterized in that the semiconductor device comprises: 4. The semiconductor device according to any one of claims 1 to 3, wherein the silicide-forming metal is platinum. 5. A section 7' (a silicon semiconductor region having an exposed surface) is formed on a part of the main surface of the semiconductor substrate, and a main surface of the semiconductor substrate is formed so as to be in contact with at least a part of the exposed surface of the silicon semiconductor region. forming a silicide layer in a portion of the silicide layer metal layer that contacts the silicon semiconductor region by heat-treating the semiconductor substrate with a portion having a silicide-forming metal layer formed thereon; After forming an etching-resistant etching mask on the silicide-forming metal layer on which the silicide layer has not been formed, the silicon semiconductor region is etched and removed selectively using the etching-resistant mask. A method for manufacturing a semiconductor device, comprising the steps of: forming a wiring layer extending on an insulating film covering a main surface of the semiconductor substrate; ] - a polycrystalline silicon layer formed on a covering insulating film? A method for manufacturing a semiconductor device according to claim 5.7. Claims include a semiconductor region formed in a semiconductor substrate, and the surface of the silicon semiconductor region 9 is partitioned by a portion exposed from an insulating film covering the main surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to item 5. 8. Forming an insulating film covering a portion of the silicon semiconductor region 7, and covering a selected portion of the silicide-forming metal layer located on the insulating film. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the etching-resistant mask is formed to form a silicide-forming metal wiring M that intersects the silicon semiconductor region. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the silicide-forming metal is platinum.