JPS59131164U - Flat package IC - Google Patents

Flat package IC

Info

Publication number
JPS59131164U
JPS59131164U JP2391283U JP2391283U JPS59131164U JP S59131164 U JPS59131164 U JP S59131164U JP 2391283 U JP2391283 U JP 2391283U JP 2391283 U JP2391283 U JP 2391283U JP S59131164 U JPS59131164 U JP S59131164U
Authority
JP
Japan
Prior art keywords
flat package
circuit board
printed circuit
electrode terminals
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2391283U
Other languages
Japanese (ja)
Inventor
哲夫 宮丸
Original Assignee
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ビクター株式会社 filed Critical 日本ビクター株式会社
Priority to JP2391283U priority Critical patent/JPS59131164U/en
Publication of JPS59131164U publication Critical patent/JPS59131164U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のフラットパッケージＩＣの平面図、第２
図はそのプリント基板への取付は状態を示す側断面図、
第３図はこの考案になるフラットパッケージＩＣをプリ
ント基板に取付けた状態の実施例を示す平面図、第４図
は第３図のＡ−Ａ′線における側断面図、第５図は電極
端子および位置決め端子の同時成形手段の一例を示す金
属板の平面図である。 １・・・フラットパッケージＩＣ，２，３・・・電極端
子、４・・・プリント基板、５・・・導電パターン、７
・・・位置決め端子、８・・・位置決め孔。Figure 1 is a plan view of a conventional flat package IC, Figure 2 is a plan view of a conventional flat package IC.
The figure is a side sectional view showing how it is installed on the printed circuit board.
Fig. 3 is a plan view showing an embodiment of the flat package IC of this invention attached to a printed circuit board, Fig. 4 is a side sectional view taken along line A-A' in Fig. 3, and Fig. 5 is an electrode terminal. FIG. 3 is a plan view of a metal plate showing an example of means for simultaneously forming positioning terminals. DESCRIPTION OF SYMBOLS 1... Flat package IC, 2, 3... Electrode terminal, 4... Printed circuit board, 5... Conductive pattern, 7
...Positioning terminal, 8...Positioning hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 互いに並設する複数の電極端子を有するフラットパッケ
ージＩＣにおいて、これら複数の電極端子とプリント基
板上の複数の導電パターンとをそれぞれ合致させるため
に、あらかじめプリント基板に設けた位置決め孔に挿入
する位置決め端子を付設させたことを特徴とするフラッ
トパッケージＣ０In a flat package IC having a plurality of electrode terminals arranged in parallel with each other, a positioning terminal is inserted into a positioning hole previously provided on a printed circuit board in order to match the plurality of electrode terminals with a plurality of conductive patterns on the printed circuit board. A flat package C0 characterized by the addition of
JP2391283U 1983-02-21 1983-02-21 Flat package IC Pending JPS59131164U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2391283U JPS59131164U (en) 1983-02-21 1983-02-21 Flat package IC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2391283U JPS59131164U (en) 1983-02-21 1983-02-21 Flat package IC

Publications (1)

Publication Number Publication Date
JPS59131164U true JPS59131164U (en) 1984-09-03

Family

ID=30154979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2391283U Pending JPS59131164U (en) 1983-02-21 1983-02-21 Flat package IC

Country Status (1)

Country Link
JP (1) JPS59131164U (en)

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