JPS59130437A - Method for selecting semiconductor devices - Google Patents
Method for selecting semiconductor devicesInfo
- Publication number
- JPS59130437A JPS59130437A JP58006122A JP612283A JPS59130437A JP S59130437 A JPS59130437 A JP S59130437A JP 58006122 A JP58006122 A JP 58006122A JP 612283 A JP612283 A JP 612283A JP S59130437 A JPS59130437 A JP S59130437A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive tape
- defective
- thyristors
- thyristor
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
この発明は半導体装置の選別方法に関し、特に接着テー
プに貼着された多数の半導体装置の外観検査を行なって
不良半導体装Ｍ全接着テープより除去する方法に関する
。TECHNICAL FIELD The present invention relates to a method for selecting semiconductor devices, and more particularly to a method for visually inspecting a large number of semiconductor devices attached to an adhesive tape and removing all defective semiconductor devices M from the adhesive tape.
背景技術
トランジスタ、サイリスタ等の半導体装置ハ、−稜の半
導体基板に多数の半導体装置を形成し、最後に半導体基
板を各半導体装置毎に細分割し、良品の半導体装置のみ
をステムやリードフレーム等の基板に固着して製造され
ている。したがって、多数の半導体装置の中から良品と
不良品とを選別する必要がある。この選別作業に先立っ
て、各半導体装置の電気的特性全検査する工程や、外観
状態を検査する工程がある。BACKGROUND TECHNOLOGY Semiconductor devices such as transistors and thyristors C. A large number of semiconductor devices are formed on a -edge semiconductor substrate.Finally, the semiconductor substrate is subdivided into each semiconductor device, and only good semiconductor devices are separated into stems, lead frames, etc. It is manufactured by being fixed to the substrate. Therefore, it is necessary to select good products and defective products from among a large number of semiconductor devices. Prior to this sorting operation, there is a step of fully inspecting the electrical characteristics of each semiconductor device and a step of inspecting its external appearance.
第１図は半導体基板ｌの要部断面図で、−例として多数
の逆阻止３端子サイリスタ（以下単にサイリスタという
）２が形成されている。この半導体基板ｌはまず各サイ
リスタ２の電気的特性が検査され、不良サイリスタ２ａ
には不良マーク３が付される。次に、この半導体基板１
の裏面を第２図に示すように接着テープ４に貼着し・各
サイ゛すスタ２，２間を切断分離して、各サイリスタ２
゜２に分割する。こののち、第３図（Ａ、）に示すよう
に、必要により接着テープ４を引き伸して・各サイリス
タ２，２間に隙間を形成し、第３図（Ｂ）に示すように
、不良マーク３のイ１された不良サイリスタ２ａを除去
する。次いで残った各サイリスタ２の外観を表面側から
検査して、欠け５等全有する不良サイリスク２ｂ２第３
図（Ｃ１のように除去する。さらに、接着テープ４全通
して各サイリスタ２の外観を裏面側から検査して、欠け
６等全有する不良サイリスク２ ｃ ｋ 、第３図（Ｄ
ｌのように、突き棒７で押して、真空吸着ペン８で成層
して除去する。かくして、接層テープ４上には、特性な
らびに外観の良好なサイリスタ２のみが残存するので、
この残存したサイリスタ２を順次接着テープ４より剥離
して、ステムやリードフレーム等に固着していけばよい
。FIG. 1 is a sectional view of a main part of a semiconductor substrate 1, in which a large number of reverse blocking three-terminal thyristors (hereinafter simply referred to as thyristors) 2 are formed as an example. This semiconductor substrate l is first inspected for the electrical characteristics of each thyristor 2, and the defective thyristor 2a is inspected.
A defective mark 3 is attached to the item. Next, this semiconductor substrate 1
Attach the back side of the thyristor 2 to adhesive tape 4 as shown in Fig. 2, cut and separate between each thyristor 2,
゜Divide into 2. After that, as shown in Fig. 3 (A), the adhesive tape 4 is stretched as necessary to form a gap between each thyristor 2, 2, and as shown in Fig. 3 (B), the adhesive tape 4 is stretched. The defective thyristor 2a with mark 3 is removed. Next, the appearance of each remaining thyristor 2 is inspected from the surface side, and the defective thyristor 2b2, which has all the defects such as chips, is detected.
Further, the appearance of each thyristor 2 is inspected from the back side by passing the adhesive tape 4 all the way through, and the defective thyristor 2 c k with all the chips 6 etc. is removed as shown in Fig. 3 (D
As shown in Fig. 1, push with a push rod 7 and remove it in layers with a vacuum suction pen 8. In this way, only the thyristor 2 with good characteristics and appearance remains on the contact tape 4.
The remaining thyristor 2 may be sequentially peeled off from the adhesive tape 4 and fixed to the stem, lead frame, or the like.
ところで、」二記第３図（Ｄｌのように、不良サイリス
タ２Ｃを真空吸着ペン８を利用して除去することは設備
費が嵩むσ）みならず、真空成層ペン８の上下動作のた
めに作業時間が長くなるという難点があった。By the way, it is not only necessary to remove the defective thyristor 2C using the vacuum suction pen 8 as shown in Figure 2 (Dl), but also because of the vertical movement of the vacuum lamination pen 8. The problem was that it took a long time to work.
発明の開示
それゆえ、この発明の主たる目的は、半導体装置の裏面
の外観検査工程に於ける設備費の低減および作業時間を
短縮することである。DISCLOSURE OF THE INVENTION Therefore, the main object of the present invention is to reduce the equipment cost and shorten the working time in the step of visual inspection of the back side of a semiconductor device.
この発明は要約すると、裏面が第１の接着テープに貼着
された半導体装置を所定間隔で第２の接着テープに対向
配置せしめ、前記第１の接着テープ全通して各半導体装
置の裏面の外観検査を行ない、不良半導体装置全型１の
接層テープを介して押圧して前記第２の接着テープに移
し換えることを特徴とするものである。In summary, the present invention can be summarized as follows: Semiconductor devices whose back surfaces are adhered to a first adhesive tape are placed facing a second adhesive tape at predetermined intervals, and the appearance of the back surface of each semiconductor device is passed through the entire first adhesive tape. This method is characterized in that the defective semiconductor device is transferred to the second adhesive tape by pressing through the adhesive tape of the entire mold 1 after inspection.
すなわち、上記のように第１の接着テープに裏面が貼着
された半導体装置に、所定間隔で第２の接層テープ全対
問配置し、不良半導体装置を第１の接層テープ全弁して
押圧することによって、押圧された半導体装置が第１の
接着テープから剥離されて第２の接着テープに移し換え
られるので、従来のような真空吸着ペンは不要となり、
しかも真空吸着ペンのような上下左右方向の移動が不要
になるので、作業時間も短縮できる。また、第２の接着
テープに、裏面の外観検査によって不良と判定され／乙
半導体装置が元の配列状態のま＼で残るので、不良マツ
プが直ちに得られ、外観不良の発生原因の解明およびそ
の対策立案に便利であるという作用効果を奏する。That is, the second adhesive tape is placed at predetermined intervals on the semiconductor device whose back side is adhered to the first adhesive tape as described above, and the defective semiconductor device is completely exposed to the first adhesive tape. By pressing the device, the pressed semiconductor device is peeled off from the first adhesive tape and transferred to the second adhesive tape, eliminating the need for a conventional vacuum suction pen.
Moreover, since there is no need to move vertically and horizontally like with a vacuum suction pen, work time can be shortened. In addition, since semiconductor devices determined to be defective by the visual inspection of the back side of the second adhesive tape remain in their original arrangement, a defect map can be immediately obtained, and the cause of the defective appearance can be clarified and corrected. It has the effect of being convenient for planning countermeasures.
発明を実施するだめの最良の形態 以下、この発明の一実施例を図面？参照して説明する。Best mode for carrying out the invention Below is a drawing of an embodiment of this invention? Refer to and explain.
第４図（に〜（Ｅ）はこの発明の各工程の要部断面図を
示す。FIGS. 4A to 4E show cross-sectional views of essential parts of each step of the present invention.
第５図および第６図はそれぞれ第４図（Ａｌおよび第４
図ＣＤ＋の段階の全体断面図全話す。Figures 5 and 6 are respectively shown in Figure 4 (Al and 4).
Full cross-sectional view of the CD+ stage.
第４図（ＡＪ〜（Ｃ１は第３図（Ａ、１〜（０）と同様
なので、同一部分には同一参照符号を付している。すな
わち、半導体基板１に形成された多数のサイリスタ２の
電気的特性を検査し、不良サイリスタ２ａに不良７−り
３を付したのち、半導体基板ｌの裏面を第）σ）接着テ
ープ４に貼着し、周知のダイシング。FIG. 4 (AJ-(C1) is the same as FIG. 3 (A, 1-(0)), so the same parts are given the same reference numerals. That is, a large number of thyristors 2 formed on the semiconductor substrate 1 After inspecting the electrical characteristics of the defective thyristor 2a and labeling the defective thyristor 2a as defective, the back surface of the semiconductor substrate 1 is pasted on an adhesive tape 4 and subjected to well-known dicing.
プレーキング工程等？実施して、各サイリスタ２゜２に
切断分離し、さらに要すれば、第１の接着テープ４に引
き伸して１各サイリスタ２，２間に若干の隙間全般ける
（第４図（Ａ））。第５図はこのときの全体の断面図全
話す。図において、１０は保持リングで、内方に向う庇
状の天板部１１と側壁部１２と全有し、側壁部１２の外
周面に沿って四部１３に有する。そして、第１の接着テ
ープ４の周縁部は、側壁部１２に沿って引き伸ばされ、
その上からゴムリング１４が凹部１３に嵌合されて、接
着テープ４が伸張状態に保持されている。こののち、不
良マーク３の付されている不良サイリスク２ａ全除去す
る（第４図（Ｂ））。次に残った各サイリスタ２の外観
状態全表面側から検査して、欠け５等全有する不良サイ
リスタ２ ｂｉｆ除去する。Preking process etc.? Then, each thyristor 2 is cut and separated, and if necessary, the first adhesive tape 4 is stretched to create a slight gap between each thyristor 2 (Fig. 4 (A)). ). FIG. 5 shows the entire sectional view at this time. In the figure, reference numeral 10 denotes a retaining ring, which has an inward eave-like top plate portion 11 and a side wall portion 12, and is provided at four portions 13 along the outer peripheral surface of the side wall portion 12. Then, the peripheral edge of the first adhesive tape 4 is stretched along the side wall 12,
A rubber ring 14 is fitted into the recess 13 from above to hold the adhesive tape 4 in a stretched state. After this, the defective side risk 2a with the defective mark 3 attached is completely removed (FIG. 4(B)). Next, the appearance condition of each remaining thyristor 2 is inspected from the entire surface side, and all defective thyristors 2 bif including chips or the like are removed.
このとき、裏面側に欠け６等全有する不良サイリスク２
ｃがあっても、表面側からは観察できず、当然除去され
ない（第４図（０））。次に、第１の接着テープ４に裏
面が貼着された各サイリスタ２に所定間隔Ｇで第２の接
着テープ１５を対向配置せ１、ぬる（第４図（Ｄ））。At this time, there is a risk of defective size 2 with all chips such as 6 on the back side.
Even if there is c, it cannot be observed from the surface side and is naturally not removed (Fig. 4 (0)). Next, a second adhesive tape 15 is placed facing each thyristor 2 whose back side is adhered to the first adhesive tape 4 at a predetermined interval G and applied (FIG. 4(D)).
第６図はこのときの全体の断ｍｊ図全話す。図において
、１６は前記第５図に示す保持リング１０を受は入れる
リングで、前記保持リング１０と第１の接着テープ４を
加えた外径寸法より若干大きい内径の側壁部１７と、高
さ寸法がＧの内方フランジ部１８とを有する。ナして、
前記内方フランジ部上８の下面に第２の接着テープ１５
が貼着されている。なお、内方フランジ部１８の内径寸
法は保持リング１０の天板部１１の内径寸法よりも大き
くしておく方が、後のサイリスタの移し換え工程におい
て、第１の接層テープ４の周辺部が変形しやすくて好都
合である。かくして、第１の接着テープ４全通して各サ
イリスタ２の裏面の外観状態全検査し、裏面側に欠け６
等？有する不良サイリスタ２Ｃがあれば、第１の接着テ
ープ４の上から突き棒１９で押圧して・第１の接着テー
プ４全変形せしめて、不良サイリスタ２ｃの表面上第２
の接着テープ１５に押し付けで貼着し、突き棒１９全持
ち上げると、第１の接着テープ４は弾性力で元の状態に
復帰し、前記不良サイリスタ２ｃは第２の接着テープ１
５に移し換えられて残る。このとき、突き棒１９の径を
サイリスタ２の寸法よりも小さくしたり、その下端を球
面状にすることによって、第１の接着テープ４と不良サ
イリスタ２ｃの接着面積が小さくなるので、第２の接着
テープ１５の接着力が第１の接着テープ４の接着力と同
等であっても、不良サイリスタ２ｃの移し換え作業は円
滑に行なえる。しかし、第２の接層テープ１５の接涜力
全、第１の接着テープ４の接層力よりも大きくすること
は、不良サイリスク２ｃの移し換え作業をより容易かつ
確実にする。Figure 6 shows the entire cross section mj diagram at this time. In the figure, reference numeral 16 denotes a ring that receives the retaining ring 10 shown in FIG. and an inner flange portion 18 having a dimension of G. Na,
A second adhesive tape 15 is attached to the lower surface of the inner flange upper portion 8.
is pasted. Note that it is better to make the inner diameter of the inner flange portion 18 larger than the inner diameter of the top plate portion 11 of the retaining ring 10 so that the peripheral portion of the first contact tape 4 can be It is convenient because it is easy to deform. In this way, the appearance condition of the back side of each thyristor 2 was fully inspected by passing the first adhesive tape 4 through, and there were no chips 6 on the back side.
etc? If there is a defective thyristor 2C, press the first adhesive tape 4 with a push rod 19 from above to completely deform the first adhesive tape 4, so that the second
When the push rod 19 is fully lifted, the first adhesive tape 4 returns to its original state due to elastic force, and the defective thyristor 2c is attached to the second adhesive tape 1.
It is transferred to 5 and remains. At this time, by making the diameter of the push rod 19 smaller than the dimension of the thyristor 2 or by making its lower end spherical, the adhesive area between the first adhesive tape 4 and the defective thyristor 2c becomes smaller, so that the second Even if the adhesive strength of the adhesive tape 15 is equivalent to the adhesive strength of the first adhesive tape 4, the work of replacing the defective thyristor 2c can be performed smoothly. However, by making the full contact force of the second adhesive tape 15 greater than the contact force of the first adhesive tape 4, the work of transferring the defective silicone 2c becomes easier and more reliable.
なお、上記実施例はサイリスクの場合について説明した
が、他の半導体装置においても同様に実施できるもので
ある。It should be noted that, although the above embodiment has been explained in the case of Cyrisk, it can be similarly implemented in other semiconductor devices.
第１図は多数のサイリスタを形成した半導体基板の要部
断面図である。
第２図は上記半導体基板を接着テープ１こ貼着して各サ
イリスク毎に分割した状態４示す要部断面図である。
第３図（Ａｌ−（Ｄ＋は従来の選別方法について説明す
るだめの各段階の要部断面図である。
第４図（Ａｌ−（Ｅｌはこの発明の選別方法について説
明するだめの各段階の要部断面図である。
第５文は第４図（Ａｔの段階における全体断面図である
。
第６図は第４図（Ｄ＋の段階における全体断面図である
。
１・・・・半導体基板、
２・・・・・・半導体装置（サイリスク）、２ ａ、〜
２ｃ・・・・・不良半導体装置（不良サイリスタ）−３
−・・・・不良マーク、
４・・・・・ 第１の接層テープ、
５．６ ・・・・欠け、
］−５・・・・ 第２の接層テープ、
１９・・・・・・突き棒。
第１図
第２図
第３図
第４図
第５図
第６図FIG. 1 is a sectional view of a main part of a semiconductor substrate on which a large number of thyristors are formed. FIG. 2 is a cross-sectional view of a main part showing a state 4 in which the semiconductor substrate is divided into individual silicon risks with one adhesive tape attached thereto. Figure 3 (Al- (D+ is a cross-sectional view of the main part of each step of the screen for explaining the conventional sorting method. This is a sectional view of the main parts. The fifth sentence is the entire sectional view at the stage of FIG. 4 (At). FIG. 6 is the entire sectional view at the stage of FIG. 4 (D+). 1...Semiconductor substrate , 2... Semiconductor device (Sirisk), 2 a, ~
2c...Defective semiconductor device (defective thyristor) -3
-...Failure mark, 4...First adhesive tape, 5.6...Chip, ]-5...Second adhesive tape, 19...・Pushing stick. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
テープに貼着する工程と、 前記半導体基板全容半導体装置毎に分割する工程と、 前記各半導体装置を所定間隔で第２の接着テープと対向
せしめる工程と、 前記第１の接着テープを通して各半導体装置の外観検査
を行ない、不良半導体装置を第１の接着テープを介して
押圧して前記第２の接着テープに移し換える工程と全含
む半導体装置の選別方法。[Claims] A step of adhering a semiconductor substrate on which a large number of semiconductor devices are formed to a first adhesive tape, a step of dividing the entire semiconductor substrate into semiconductor devices, and a step of dividing each semiconductor device at predetermined intervals. a step of placing the semiconductor device facing a second adhesive tape; performing an external inspection of each semiconductor device through the first adhesive tape; and pressing a defective semiconductor device through the first adhesive tape to transfer it to the second adhesive tape; Replacement process and selection method for all semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58006122A JPS59130437A (en) | 1983-01-17 | 1983-01-17 | Method for selecting semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58006122A JPS59130437A (en) | 1983-01-17 | 1983-01-17 | Method for selecting semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59130437A true JPS59130437A (en) | 1984-07-27 |
Family
ID=11629699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58006122A Pending JPS59130437A (en) | 1983-01-17 | 1983-01-17 | Method for selecting semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59130437A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63178333U (en) * | 1987-05-09 | 1988-11-18 | ||
| JPS6453558A (en) * | 1987-08-25 | 1989-03-01 | Matsushita Electric Ind Co Ltd | Visual inspection of chip component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5673444A (en) * | 1979-11-20 | 1981-06-18 | Fujitsu Ltd | Device for visual inspection |
-
1983
- 1983-01-17 JP JP58006122A patent/JPS59130437A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5673444A (en) * | 1979-11-20 | 1981-06-18 | Fujitsu Ltd | Device for visual inspection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63178333U (en) * | 1987-05-09 | 1988-11-18 | ||
| JPS6453558A (en) * | 1987-08-25 | 1989-03-01 | Matsushita Electric Ind Co Ltd | Visual inspection of chip component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101335191B (en) | Manufacturing method for semiconductor integrated device | |
| CN102623402B (en) | Manufacturing method for semiconductor integrated device | |
| EP1484791A4 (en) | Dicing method, method of inspecting integrated circuit element, substrate holding device, and pressure sensitive adhesive film | |
| US7833601B2 (en) | Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods | |
| JP2000208447A (en) | Semiconductor manufacturing apparatus and manufacture of semiconductor device | |
| US20150056727A1 (en) | Method of inspecting semiconductor device, method of fabricating semiconductor device, and inspection tool | |
| EP0294259A3 (en) | Screening of gate oxides on semiconductors | |
| JPS59130437A (en) | Method for selecting semiconductor devices | |
| JPS6244409B2 (en) | ||
| JPH02179708A (en) | Break separating method of semi-conductor wafer | |
| KR102007709B1 (en) | Method for manufacturing semiconductor chip | |
| JPH05343517A (en) | Die sorter tape | |
| JPH0376139A (en) | Upward pushing movement of semiconductor element | |
| JPS61180442A (en) | Manufacture of semiconductor device | |
| JPH04367250A (en) | Manufacture of semiconductor chip | |
| JPH03239346A (en) | Manufacture of semiconductor device | |
| JP2606890B2 (en) | Semiconductor chip pickup method | |
| JPH08293538A (en) | Pick-up method and device thereof | |
| JPH0425040A (en) | Manufacture of semiconductor device | |
| JPS593943A (en) | Manufacture of semiconductor device | |
| JPS644339B2 (en) | ||
| JPH03187242A (en) | Manufacture of semiconductor device | |
| JPS63276240A (en) | Manufacture of semiconductor device | |
| JPS62204542A (en) | Method and apparatus for dividing wafer | |
| JPS6290943A (en) | Manufacturing semiconductor device |