JPS59128806A - Agc circuit - Google Patents

Agc circuit

Info

Publication number
JPS59128806A
JPS59128806A JP285883A JP285883A JPS59128806A JP S59128806 A JPS59128806 A JP S59128806A JP 285883 A JP285883 A JP 285883A JP 285883 A JP285883 A JP 285883A JP S59128806 A JPS59128806 A JP S59128806A
Authority
JP
Japan
Prior art keywords
circuit
time constant
output
variable
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP285883A
Other languages
Japanese (ja)
Other versions
JPH0124444B2 (en
Inventor
Mitsuo Takemoto
竹本 光雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP285883A priority Critical patent/JPS59128806A/en
Publication of JPS59128806A publication Critical patent/JPS59128806A/en
Publication of JPH0124444B2 publication Critical patent/JPH0124444B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To shorten the transient response time of an output and to reduce the error time by using a time constant variable type integration circuit which controls a variable gain circuit and switching the time constant of the integration circuit to a small value when an input signal has a stepped change. CONSTITUTION:An input signal is supplied to a smoothing circuit 34 through a variable gain circuit 32 and a rectifying circuit 33. The output of the circuit 34 is supplied to voltage comparators 35 and 36 to be compared with comparing voltages VH and VL and then supplied to an exclusive AND circuit 37. The switch SW of a time constant variable type smoothing circuit 38 is switched with the output of the circuit 37. Then an AGC signal is delivered to an output terminal 39 through control of the circuit 32. The time constants of a resistance R2 and a capacitor C2, a parallel resistance RP of resistances R2 and R3 and a CR integration circuit consisting of the C2, R1 and C1 are defined as tau2=C2R2, tau3=C2RP and tau4=C1R1 respectively. Then the time constant is defined at tau1 for the stepped level change of an input. Here tau1 tau3<tau4<<tau2 is satisfied. Thus the transient response time of an output is shortened, and the error time is reduced.

Description

【発明の詳細な説明】 (技術分野) 本発明は信号の包絡線成分による混変調が小さく、信号
のレベル変動に対して速い応答速度をもつ自動利得制御
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an automatic gain control circuit that has low cross-modulation due to signal envelope components and has a fast response speed to signal level fluctuations.

(従来技術) 従来のAGC回路を第1図に示す。第1図において11
は信号入力端子、13は整流回路、14は平滑回路、1
2は平滑回路14の出力にょシ利得が制御される可変利
得回路、15は可変利得回路12の出力の直流成分を得
る出力端子である。可変利得回路12の出力が整流回路
13、平滑回路14を介して可変利得回路12自身の制
御入力にもどることによシ負帰還制御ループが形成され
て自動利得制御回路(AGC)となっている。
(Prior Art) A conventional AGC circuit is shown in FIG. 11 in Figure 1
is a signal input terminal, 13 is a rectifier circuit, 14 is a smoothing circuit, 1
2 is a variable gain circuit whose output gain is controlled by the smoothing circuit 14, and 15 is an output terminal for obtaining the DC component of the output of the variable gain circuit 12. The output of the variable gain circuit 12 is returned to the control input of the variable gain circuit 12 itself via the rectifier circuit 13 and the smoothing circuit 14, thereby forming a negative feedback control loop to form an automatic gain control circuit (AGC). .

第2図は第1図に示すAGC回路の各部における信号波
形を示し、第2図(、)は信号入力端子11における入
力信号波形、第2図(b)は平滑回路14の出力の信号
波形、第2図(c)は出力端子15のAGC出力信号波
形を示す。従来実施例の場合、入力信号の包絡線成分に
よる混変調を小さくする為、平滑回路14の時定数を太
きくシ、可変利得回路12への負帰還制御信号に包絡線
成分が包まれないようにしていた。その為、入力信号に
平滑回路の時定数に対して極端に速い時定数のステップ
的なレベル変化が発生した時、AGC出力は第2図に示
すように平滑回路14の時定数による長い時間の過渡応
答が発生することとなり、エラーとなる時間が長くなる
欠点を有していた。
FIG. 2 shows signal waveforms in each part of the AGC circuit shown in FIG. 1, FIG. 2 (,) shows the input signal waveform at the signal input terminal 11, and FIG. , FIG. 2(c) shows the AGC output signal waveform of the output terminal 15. In the case of the conventional embodiment, in order to reduce cross-modulation due to the envelope component of the input signal, the time constant of the smoothing circuit 14 is made thicker so that the envelope component is not wrapped in the negative feedback control signal to the variable gain circuit 12. I was doing it. Therefore, when a step level change occurs in the input signal with an extremely fast time constant compared to the time constant of the smoothing circuit, the AGC output will change over a long period of time due to the time constant of the smoothing circuit 14, as shown in Figure 2. This has the disadvantage that a transient response occurs and the time required for an error to occur becomes longer.

(発明の目的) 本発明は上記欠点を除去する為に平滑回路の時定数を入
力レベルのステップ的な変化時に自動的に切替制御して
過渡応答を最小限にするものであシ、以下詳細に説明す
る。
(Object of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention automatically switches and controls the time constant of the smoothing circuit when the input level changes stepwise to minimize the transient response.The details are as follows. Explain.

(発明の構成) 本発明は入出力利得を外部制御によシ可変とする可変利
得回路と、該可変利得回路の出力を絶対値化する絶対値
回路と、スイッチにより第1の時定数と第2の時定数に
切替えでき前記絶対値回路の出力を平滑化して前記可変
利得回路を制御する時定数可変型積分回路と、第3の時
定数をもち前記絶対値回路の出力を平滑化する積分回路
と、該積分回路の出力を各々異なるレベルの基準電圧と
比較する2つの電圧比較回路と、該2つの電圧比較回路
の出力の排他的論理和をとシその信号によって前記時定
数可変型積分回路のスイッチを制御する排他的論理和回
路とから成り、前記第2の時定数と第3の時定数を前記
第1の時定数よシも小さくなし1.入力信号のステップ
的変化時において前記スイッチを切替えて前記時定数可
変型積分回路の時定数を前記第1の時定数から第2の時
定数に切替えることを特徴とするAGC回路である。
(Structure of the Invention) The present invention includes a variable gain circuit whose input/output gain is made variable by external control, an absolute value circuit which converts the output of the variable gain circuit into an absolute value, and a switch that controls a first time constant and a first time constant. a variable time constant integrator circuit that can be switched to a second time constant and smoothes the output of the absolute value circuit to control the variable gain circuit; and an integrator circuit that has a third time constant and smoothes the output of the absolute value circuit. a circuit, two voltage comparator circuits that compare the outputs of the integrator circuits with reference voltages of different levels, and an exclusive OR of the outputs of the two voltage comparator circuits; an exclusive OR circuit for controlling the switches of the circuit, and the second time constant and the third time constant are made smaller than the first time constant.1. The AGC circuit is characterized in that the time constant of the variable time constant type integrating circuit is changed from the first time constant to the second time constant by switching the switch when the input signal changes stepwise.

(第1の実施例) 第3図は本発明の実施例によるAGC回路であシ、31
は信号入力端子、32は可変利得回路、33は整流回路
、34は平滑回路1.35 、36は電圧比較回路、3
7は排他的論理和回路、38は時定数可変型平滑回路、
39はAGC信号出力端子である。第3図において、一
点鎖線で囲んだ部分は、第1図に示した従来例のAGC
回路に新たに加えた回路部分であり、抵抗R2とコンデ
ンサc2がら成る積分回路は第1図の平滑回路に相肖す
る。抵抗R2とコンデンサC2、抵抗R2とR3の並列
抵抗値RpとコンデンサC2、抵抗R1とコンデンサC
1から成る各CR積分回路の時定数を各々τ2=C2R
2,τ3=C2Rp、τ、=ClR1とし、入力のステ
ップ的なレベル変化の時定数をτ1とすれば、τ1舞τ
3〈τ4くτ2のように設定されている。
(First Embodiment) FIG. 3 shows an AGC circuit according to an embodiment of the present invention.
is a signal input terminal, 32 is a variable gain circuit, 33 is a rectifier circuit, 34 is a smoothing circuit, 36 is a voltage comparison circuit, 3
7 is an exclusive OR circuit, 38 is a variable time constant smoothing circuit,
39 is an AGC signal output terminal. In Fig. 3, the part surrounded by the dashed line is the AGC of the conventional example shown in Fig. 1.
The integrating circuit, which is a new circuit part added to the circuit and is composed of a resistor R2 and a capacitor c2, is comparable to the smoothing circuit shown in FIG. Resistor R2 and capacitor C2, parallel resistance value Rp of resistors R2 and R3 and capacitor C2, resistor R1 and capacitor C
The time constant of each CR integrator circuit consisting of τ2=C2R
2, τ3 = C2Rp, τ, = ClR1, and if the time constant of the stepwise level change of the input is τ1, then τ1 dance τ
3<τ4 × τ2.

第4図は第3図に示した本発明の実施例によるAGC回
路の各部における信号波形を示し、第4図(、)は信号
入力端子31における入力信号、第4図(b)は平滑回
路34の出力信号、第4図(c)は電圧比較回路35の
出力信号、第4図(d)は電圧比較回路36の出力信号
、第4図(、)は排他的論理和回路37の出力信号、第
4図(f)は時定数可変型平滑回路38の出力信号、第
4図0)は出力端子39における出力信号の各信号波形
である。
FIG. 4 shows signal waveforms at various parts of the AGC circuit according to the embodiment of the present invention shown in FIG. 3, FIG. 4(,) shows the input signal at the signal input terminal 31, and FIG. 34, FIG. 4(c) is the output signal of the voltage comparison circuit 35, FIG. 4(d) is the output signal of the voltage comparison circuit 36, and FIG. 4(,) is the output of the exclusive OR circuit 37. 4(f) is the output signal of the variable time constant smoothing circuit 38, and FIG. 4(0) is the signal waveform of the output signal at the output terminal 39.

次に第3図、第4図を用いて本発明の詳細な説明する。Next, the present invention will be explained in detail using FIGS. 3 and 4.

入力信号を第4図(、)に示す信号とする。Let the input signal be the signal shown in FIG. 4(,).

入力信号は可変利得回路32.整流回路33を通り、平
滑回路34において、入力信号がステップ電する為、平
滑回路34の出力は第4図(b) Oのように変化する
。次に電圧比較回路36にて比較電圧VLと比較され、
第4図(a) @に示すハイレベルとなる。この時電圧
比較回路35の出力はハイレベルにホールドしているこ
とから、排他的論理和回路37−の出力は第41k(e
)@に示すように電圧比較回路36の出力を反転したも
のとなる。時定数可変型平滑回路38のスイッチSWは
排他的論理和回路37の出力がロウレベルの時にオンさ
れる。スイッチSWがオンされると、時定数可変型平滑
回路38の時定数はτs =C2Rp (< C2R2
)となシ、これによって時定数可変型平滑回路38の出
力はτ3の時定数で放電して第4図(f)に示すような
波形となシ、その出力が可変利得回路32を制御し、A
GC信号出力端子39の出力信号もτ3の時定数で利得
制御される(第4図(g))。利得制御された結果、整
流回路33の出力は低下したレベルが復旧し、平滑回路
34の出力もレベルが上昇して再び比較電圧V、よシ高
くなシ、電圧比較回路36の出力はロウレベルとなる。
The input signal is sent to the variable gain circuit 32. Since the input signal passes through the rectifying circuit 33 and enters the smoothing circuit 34 in a step manner, the output of the smoothing circuit 34 changes as shown in FIG. 4(b) O. Next, it is compared with the comparison voltage VL in the voltage comparison circuit 36,
The high level shown in Fig. 4(a) @ is achieved. At this time, since the output of the voltage comparison circuit 35 is held at a high level, the output of the exclusive OR circuit 37- is the 41kth (e
) As shown in @, the output of the voltage comparison circuit 36 is inverted. The switch SW of the variable time constant smoothing circuit 38 is turned on when the output of the exclusive OR circuit 37 is at a low level. When the switch SW is turned on, the time constant of the time constant variable smoothing circuit 38 becomes τs = C2Rp (< C2R2
) As a result, the output of the variable time constant smoothing circuit 38 is discharged with a time constant of τ3 and has a waveform as shown in FIG. 4(f), and the output controls the variable gain circuit 32. ,A
The output signal of the GC signal output terminal 39 is also gain controlled with a time constant of τ3 (FIG. 4(g)). As a result of the gain control, the output of the rectifier circuit 33 returns to its lowered level, the level of the output of the smoothing circuit 34 rises again, the comparison voltage V becomes higher, and the output of the voltage comparison circuit 36 becomes a low level. Become.

続いて排他的論理和回路37の出力はハイレベルとなり
、時定数可変型平滑回路38のスイッチSWがオフする
ため、時定数可変型平滑回路38の時定数はτ2にもど
る。
Subsequently, the output of the exclusive OR circuit 37 becomes high level, and the switch SW of the variable time constant smoothing circuit 38 is turned off, so that the time constant of the variable time constant smoothing circuit 38 returns to τ2.

次に入力信号の入力レベルがステップ的に上昇した時(
第4図(a)[相])、平滑回路34の出力が電圧比較
回路35において比較電圧VHよシ高くなシ比較回路3
6の出力はロウレベルであるから、排他的論理和回路3
7の出力はロウレベル(第4図(e) @ )となり、
時定数可変型平滑回路38のスイッチSWを切替えて時
定数可変型平滑回路38の時定数をτ2からτ3(τ2
〉τ3)に切替え、AGC出力信号はτ3 (−〇2R
,)の時定数で過渡応答が復旧する。その後前述した場
合と同様に、平滑回路34の出力が比較電圧V、よシも
低くなる為電圧比較回路35の出力がハイレベル、電圧
比較回路36の出力がロウレベルとなる為、排他的論理
和回路37の出力がハイレベルとなシ、その結果時定数
平滑回路38の時定数はスイッチSWがオフされてτ3
からτ2に切替る。従って、第3図に示しだAGC回路
では第4図(、)に示した入力信号に対して第4図G)
に示したAGC出力を得ることができる。
Next, when the input level of the input signal increases stepwise (
FIG. 4(a) [phase]), the comparison circuit 3 in which the output of the smoothing circuit 34 is higher than the comparison voltage VH in the voltage comparison circuit 35
Since the output of 6 is low level, exclusive OR circuit 3
The output of 7 becomes low level (Fig. 4(e) @ ),
Switch SW of the variable time constant smoothing circuit 38 is changed to change the time constant of the variable time constant smoothing circuit 38 from τ2 to τ3 (τ2
〉τ3), and the AGC output signal is τ3 (-〇2R
The transient response is restored with a time constant of , ). After that, as in the case described above, the output of the smoothing circuit 34 becomes lower than the comparison voltage V, so the output of the voltage comparison circuit 35 becomes high level, and the output of the voltage comparison circuit 36 becomes low level, so the exclusive OR The output of the circuit 37 is not at a high level, and as a result, the time constant of the time constant smoothing circuit 38 becomes τ3 when the switch SW is turned off.
to τ2. Therefore, in the AGC circuit shown in Fig. 3, for the input signal shown in Fig. 4(,), Fig. 4G)
The AGC output shown in can be obtained.

本実施例のAGC回路においては、入力レベルのステッ
プ的な変化に対して出力の過渡応答時間を大巾に短縮で
き、エラ一時間を短かくすることができる利点を有する
The AGC circuit of this embodiment has the advantage that the transient response time of the output to a stepwise change in the input level can be greatly shortened, and the error time can be shortened.

(第2の実施例) 第1の実施例ではアナログ信号処理の場合について説明
したが、これをディジタル信号処理におき替えても同様
の効果を得ることができる。すなわち、第1の実施例に
て説明した第3図において、可変利得回路32を乗算回
路に、整流回路33を絶対値回路に、平滑回路34をア
キュームレータ(積算回路)に、電圧比較回路35.3
6をマグニチーードコンパレータに、時定数可変型平滑
回路38を入力利得可変型アキュームレータに各々置き
換えてディジタル信号処理回路を構成することによって
も前記第1の実施例と同じ機能を有するAGC回路を構
成することができる。
(Second Embodiment) Although the first embodiment describes the case of analog signal processing, similar effects can be obtained even if this is replaced with digital signal processing. That is, in FIG. 3 described in the first embodiment, the variable gain circuit 32 is used as a multiplier circuit, the rectifier circuit 33 is used as an absolute value circuit, the smoothing circuit 34 is used as an accumulator (integration circuit), and the voltage comparison circuit 35 . 3
An AGC circuit having the same function as the first embodiment can also be obtained by configuring a digital signal processing circuit by replacing 6 with a magniceed comparator and the variable time constant smoothing circuit 38 with a variable input gain accumulator. Can be configured.

この場合、第1の実施例と同じ効果を提供できるととも
に、LSI化が可能となる利点を有することができる。
In this case, it is possible to provide the same effects as the first embodiment, and also to have the advantage of being able to be integrated into an LSI.

(発明の効果) 本発明はAGC回路において入力レベルのステップ的な
変化に対して出力の過渡応答時間を大巾に短縮できるの
で、モデムの受信部に利用することができる。又レベル
のステップ的な変化の検出に微分回路を使用せずに積分
回路で構成している為、雑音に対する誤動作余裕におい
て利点があシ、更にレベルのステップ的な変化の検出を
AGC出力側で行なっているので、ステップ変化検出出
力が広いレベル範囲で得られるという利点がある。
(Effects of the Invention) The present invention can greatly shorten the transient response time of the output in response to stepwise changes in the input level in the AGC circuit, and therefore can be used in the receiving section of a modem. In addition, since an integrator circuit is used instead of a differentiating circuit to detect step-like changes in level, there is an advantage in terms of margin for malfunction due to noise. This has the advantage that the step change detection output can be obtained over a wide level range.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例におけるAGC回路図、第2図は第1図
に示すAGC回路の各部における信号波形図、第3図は
本発明の実施例によるAGC回路図、第4図は第3図に
示すAGC回路の各部における信号波形図である。 3J・・・信号入力端子、32・・・可変利得回路、3
3・・・整流回路、34・・・平滑回路、35.36・
・・電圧比較回路、32・・・排他的論理和回路、38
・・・時定数可変型平滑回路、39・・・出力端子、R
1,R2゜R3・・・抵抗、C1,C2・・コンデンサ
、sw・・・スイッチ。 特許出願人 沖電気工業株式会社 第3図 第4図
FIG. 1 is an AGC circuit diagram in a conventional example, FIG. 2 is a signal waveform diagram at each part of the AGC circuit shown in FIG. 1, FIG. 3 is an AGC circuit diagram according to an embodiment of the present invention, and FIG. FIG. 3 is a signal waveform diagram at each part of the AGC circuit shown in FIG. 3J...Signal input terminal, 32...Variable gain circuit, 3
3... Rectifier circuit, 34... Smoothing circuit, 35.36.
...Voltage comparison circuit, 32...Exclusive OR circuit, 38
... variable time constant smoothing circuit, 39... output terminal, R
1, R2゜R3...Resistor, C1, C2...Capacitor, sw...Switch. Patent applicant Oki Electric Industry Co., Ltd. Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 入出力利得を外部制御によシ可変とする可変利得回路と
、該可変利得回路の出力を絶対値化する絶対値回路と、
スイッチ切替えによシ第1の時定数と第2の時定数に切
替えでき前記絶対値回路の出力を平滑化して前記可変利
得回路を制御する時定数可変型積分回路と、第3の時定
数をもち前記絶対値回路の出力を平滑化する積分回路と
、該積分回路の出力を各々異々るレベルの基準電圧と比
較する2つの電圧比較回路と、該2つの電圧比較回路の
出力の排他的論理和をとシその信号によって前記時定数
可変型積分回路のスイッチを制御する排他的論理和回路
とから成シ、前記第2の時定数と第3の時定数を前記第
1の時定数よシも小さくなし、入力信号のステップ的変
化時において前記スイッチを切替えて前記時定数可変型
積分回路の時定数を前記第1の時定数から第2の時定数
に切替えることを特徴とするAGC回路。
a variable gain circuit whose input/output gain is variable by external control; an absolute value circuit which converts the output of the variable gain circuit into an absolute value;
a time constant variable type integrating circuit that can be switched between a first time constant and a second time constant by switching a switch and smoothes the output of the absolute value circuit to control the variable gain circuit; an integrator circuit that smoothes the output of the absolute value circuit; two voltage comparator circuits that compare the output of the integrator circuit with reference voltages of different levels; and an exclusive control circuit for the outputs of the two voltage comparator circuits. an exclusive OR circuit which performs a logical sum and controls a switch of the variable time constant type integrating circuit by the signal thereof, and the second time constant and the third time constant are set to be equal to the first time constant. The AGC circuit is characterized in that the time constant of the variable time constant integrating circuit is changed from the first time constant to the second time constant by switching the switch when the input signal changes stepwise. .
JP285883A 1983-01-13 1983-01-13 Agc circuit Granted JPS59128806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP285883A JPS59128806A (en) 1983-01-13 1983-01-13 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP285883A JPS59128806A (en) 1983-01-13 1983-01-13 Agc circuit

Publications (2)

Publication Number Publication Date
JPS59128806A true JPS59128806A (en) 1984-07-25
JPH0124444B2 JPH0124444B2 (en) 1989-05-11

Family

ID=11541075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP285883A Granted JPS59128806A (en) 1983-01-13 1983-01-13 Agc circuit

Country Status (1)

Country Link
JP (1) JPS59128806A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496510A (en) * 1990-08-13 1992-03-27 Nec Corp Automatic level control circuit
WO1995034136A1 (en) * 1994-06-03 1995-12-14 Transwitch Corporation Data independent automatic gain control circuit for telecommunication applications
US5697074A (en) * 1995-03-30 1997-12-09 Nokia Mobile Phones Limited Dual rate power control loop for a transmitter
WO2001003292A1 (en) * 1999-07-02 2001-01-11 Nokia Networks Oy Power control for non-constant envelope modulation
US6246285B1 (en) 1999-10-18 2001-06-12 Mitsubishi Denki Kabushiki Kaisha AGC circuit based on a peak detection system
FR2884659A1 (en) * 2005-04-18 2006-10-20 Siemens Vdo Automotive Sas Variable-gain signal e.g. voice signal, amplifier`s automatic gain controlling device, has control units controlling slow variation of gain and rapid variation of gain based on variation of voice signal level
JP2007166588A (en) * 2005-11-16 2007-06-28 Samsung Electronics Co Ltd Automatic gain control apparatus
JP2010124031A (en) * 2008-11-17 2010-06-03 Mitsubishi Electric Corp Signal transmission system
JP2010213128A (en) * 2009-03-12 2010-09-24 Sumitomo Electric Device Innovations Inc Electronic circuit
JP2015046725A (en) * 2013-08-27 2015-03-12 株式会社五洋電子 Tone squelch circuit
JP2016127557A (en) * 2015-01-08 2016-07-11 日本無線株式会社 Power control apparatus

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496510A (en) * 1990-08-13 1992-03-27 Nec Corp Automatic level control circuit
WO1995034136A1 (en) * 1994-06-03 1995-12-14 Transwitch Corporation Data independent automatic gain control circuit for telecommunication applications
US5697074A (en) * 1995-03-30 1997-12-09 Nokia Mobile Phones Limited Dual rate power control loop for a transmitter
WO2001003292A1 (en) * 1999-07-02 2001-01-11 Nokia Networks Oy Power control for non-constant envelope modulation
US6246285B1 (en) 1999-10-18 2001-06-12 Mitsubishi Denki Kabushiki Kaisha AGC circuit based on a peak detection system
FR2884659A1 (en) * 2005-04-18 2006-10-20 Siemens Vdo Automotive Sas Variable-gain signal e.g. voice signal, amplifier`s automatic gain controlling device, has control units controlling slow variation of gain and rapid variation of gain based on variation of voice signal level
JP2007166588A (en) * 2005-11-16 2007-06-28 Samsung Electronics Co Ltd Automatic gain control apparatus
JP2010124031A (en) * 2008-11-17 2010-06-03 Mitsubishi Electric Corp Signal transmission system
JP2010213128A (en) * 2009-03-12 2010-09-24 Sumitomo Electric Device Innovations Inc Electronic circuit
JP2015046725A (en) * 2013-08-27 2015-03-12 株式会社五洋電子 Tone squelch circuit
JP2016127557A (en) * 2015-01-08 2016-07-11 日本無線株式会社 Power control apparatus

Also Published As

Publication number Publication date
JPH0124444B2 (en) 1989-05-11

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