JPH0364207A - Pulse generating circuit - Google Patents

Pulse generating circuit

Info

Publication number
JPH0364207A
JPH0364207A JP1200637A JP20063789A JPH0364207A JP H0364207 A JPH0364207 A JP H0364207A JP 1200637 A JP1200637 A JP 1200637A JP 20063789 A JP20063789 A JP 20063789A JP H0364207 A JPH0364207 A JP H0364207A
Authority
JP
Japan
Prior art keywords
pulse
capacitor
potential
terminal
input trigger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1200637A
Other languages
Japanese (ja)
Inventor
Atsushi Koyano
小矢野 敦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1200637A priority Critical patent/JPH0364207A/en
Publication of JPH0364207A publication Critical patent/JPH0364207A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control only the position of a pulse having the stable width with use of a single pin by externally controlling the charging start potential of an internal capacitor which decides the pulse position. CONSTITUTION:When an input trigger pulse 1 is supplied, a transistor switch 10 is turned on and the charging terminal potential of a capacitor C is equal to the output DC potential VB of a buffer 9. When the pulse 1 is turned off, a constant current set by a constant current source 2 flows to the capacitor C. Then the capacitor terminal potential VC increases linearly. The reference potentials of comparators 3 and 4 are set at Vref and Vref+IR respectively. A logic processing circuit 6 outputs the output pulses only for a time when the potential charged to the capacitor C crosses the IR. In such a case, the position of the output pulse can be linearly controlled to an input trigger by controlling the charging start potential of the capacitor C via an external terminal 8. As a result, a terminal of just a single pin suffices and at the same time the position of the terminal is variable to the input trigger only. Then the pulse width is constant regardless of the pulse position and has the stable accuracy.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はパルス発生回路に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a pulse generating circuit.

〔従来の技術〕[Conventional technology]

第3図は従来のパルス発生回路の回路図で、入力パルス
をトリガとし外付けCRal)の時定数で減衰を始める
MMV (モノステーブルマルチバイブレータ)+12
11個から成る。第5図は第3図の回路のパルス発生動
作を示すタイミングチャートである。MMV(2)の内
部には波形図すで示す様なスレ・ノショルドl (V+
)とスレッショルド2(Vz)が設けられ、入力aの立
ち上がりをトリガに時定数減衰をはじめた電位が、この
V + 、 V を間を通る間だけ波形図Cに示す様な
パルスを出力する。出力パルスの幅tユは電位vl と
■2のレベル設定にて行い、入力トリガパルスからの位
置1.はτを可変することによって調整する。
Figure 3 is a circuit diagram of a conventional pulse generation circuit, in which an MMV (monostable multivibrator) which is triggered by an input pulse and begins to decay with the time constant of an external CRal) +12
It consists of 11 pieces. FIG. 5 is a timing chart showing the pulse generation operation of the circuit of FIG. 3. Inside MMV (2), there is a thread voltage (V+) as shown in the waveform diagram.
) and a threshold 2 (Vz) are provided, and the potential that begins to decay with a time constant triggered by the rise of the input a outputs a pulse as shown in waveform diagram C only while passing between these V + and V . The width t of the output pulse is determined by setting the potential vl and level 2, and the width t from the input trigger pulse is determined by setting the level 1. is adjusted by varying τ.

第4図は従来の他のパルス発生回路の回路図で、MMV
l、MMV20mと各々独自にcRQoの時定数回路を
持つ、第6図は第4図のパルス発生回路のパルス発生動
作を示すタイミングチャー1.である、波形図aで示す
入力トリガが入ると、その立ち上がりエツジをきっかけ
にて1 なる時定数でMMVI(Li5の端子電圧は減
衰を始める。波形図すに示す内部スレッショルドV、の
位置よりτ、なる時定数を持つMMV2(2)にトリガ
がかかり波形図Cに示す電位v2なるスレフショルドま
での間のパルスを出力する。出力パルスの入力トリガか
らの位置t4はτ、にて、出力パルス幅t。はτ2にて
調整を行う為、パルスの位置と幅は各々独自に調整可能
である。
Figure 4 is a circuit diagram of another conventional pulse generation circuit,
FIG. 6 is a timing chart showing the pulse generation operation of the pulse generation circuit of FIG. When the input trigger shown in the waveform diagram a is input, the terminal voltage of MMVI (Li5 starts to attenuate with a time constant of 1 from the rising edge of the input trigger.From the position of the internal threshold V shown in the waveform diagram), τ A trigger is applied to MMV2 (2) with a time constant of , and it outputs a pulse up to the threshold voltage of potential v2 shown in waveform diagram C.The position t4 from the input trigger of the output pulse is τ, and the output pulse width is Since t. is adjusted by τ2, the position and width of each pulse can be adjusted independently.

第1図は従来のもう1つの他のパルス発生回路の回路図
である。外部端子より可変のバイアス電流により、内部
コンデンサCに定電流充電を行い、2つの比較器(31
14)のスレッショルド電位差を定電流充電直線の傾き
に比例し増加させる様な可変電位差とし、出力パルスの
幅が入力トリガからの位置に影響されることなく常に一
定である様なパルス発生回路である。
FIG. 1 is a circuit diagram of another conventional pulse generating circuit. The internal capacitor C is charged with a constant current using a variable bias current from the external terminal, and the two comparators (31
This is a pulse generation circuit in which the threshold potential difference of 14) is made variable so as to increase in proportion to the slope of the constant current charging straight line, and the width of the output pulse is always constant without being affected by the position from the input trigger. .

トリガパルスaからの時間をtd+ 出力パルス幅をt
。とすると、 1、   = (1) ■ ■■ =CR−−−−−−−−−−−−−−−−−(2)で表
わされ、パルス幅は外部より可変の電流Iには無関係に
一定値を取る。
Time from trigger pulse a is td+ Output pulse width is t
. Then, 1, = (1) ■ ■■ = CR−−−−−−−−−−−−−−−−−(2), the pulse width is determined by the externally variable current I. Takes a constant value regardless.

この様に、比較器[31,(4)の基準電圧の差を抵抗
Rとバイアス電流■による電位差を利用している為、パ
ルス位置のみ可変という動作をする。
In this way, since the difference between the reference voltages of the comparator [31, (4)] is used as the potential difference between the resistor R and the bias current (2), only the pulse position is variable.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のパルス発生回路は以上の様に構成されていたので
、第3図の従来のものでは回路形式は容易で調整ピンも
lカ所にてパルス位置を可変出来るが、内部スレッショ
ルドV、、V、が固定の為、時定数を変えるとともに出
力パルス幅も同時に変わってしまうという欠点があり、
また、第4図の場合は出力パルスの位置と幅の調整用に
各々MMVを設けている為独自に調整が可能であり、第
3図の様な不具合は生しないが回路構成が大きくなるこ
と、端子が2ビン必要であることという大きな欠点があ
った。また、第7図の場合は端子lピンでかつ回路構成
も簡単であり、出力パルス位置が変化しても基本的にパ
ルス幅は不変であるが、実際には、入力トリガからの位
置が遠くなるにつれ、コンデンサへの定電流充電開始電
位の傾きは小さく、同時に内部スレッショルド電位差は
狭くなる傾向にある為、パルス幅の精度、安定度がトリ
ガからの位置により変動を受けるという欠点があった。
The conventional pulse generating circuit was constructed as described above, so in the conventional circuit shown in Fig. 3, the circuit format is easy and the pulse position can be varied using l adjustment pins, but the internal thresholds V, , V, Since it is fixed, there is a drawback that when changing the time constant, the output pulse width also changes at the same time.
In addition, in the case of Figure 4, each MMV is provided for adjusting the position and width of the output pulse, so it is possible to make independent adjustments, and although the problem shown in Figure 3 does not occur, the circuit configuration becomes larger. However, there was a major drawback in that two terminals were required. In addition, in the case of Figure 7, the terminal L pin is used and the circuit configuration is simple, and the pulse width basically remains unchanged even if the output pulse position changes, but in reality, the position from the input trigger is far away. As the voltage rises, the slope of the starting potential for constant current charging to the capacitor becomes smaller, and at the same time the internal threshold potential difference tends to narrow, which has the disadvantage that the accuracy and stability of the pulse width fluctuate depending on the position from the trigger.

この発明は上記の様な欠点を解決する為になされたもの
で、回路構成が簡単で端子も1ピンで良く、かつ入力ト
リガからの位置のみ可変であり、パルス幅は位置に関係
なく一定でかつ安定な精度を持つパルス発生回路を得る
ことを目的とする。
This invention was made to solve the above-mentioned drawbacks; the circuit configuration is simple, only one pin is required, and only the position from the input trigger is variable, and the pulse width is constant regardless of the position. The purpose of this invention is to obtain a pulse generation circuit with stable accuracy.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るパルス発生回路は、内部の一定スレンジ
aルド電位に対し、内部コンデンサへの定電流充電開始
電位を外部端子より制御することの出来る電位可変回路
を設けたものである。
The pulse generating circuit according to the present invention is provided with a potential variable circuit that can control the constant current charging start potential to the internal capacitor from an external terminal with respect to an internal fixed range aldo potential.

〔作用〕[Effect]

この発明における充電開始電位可変回路は出力パルスの
位置に関係なく常に安定な一定の幅のパルスを出力する
The charging start potential variable circuit according to the present invention always outputs a stable pulse with a constant width regardless of the position of the output pulse.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例であるパルス発生回路の回路図
で、図において、(11は入力トリガパルス、(2)は
内部で定めた定電流源、(3)、(4)は比較器で、そ
れぞれ基準電位vr*r+51及びVF*f+I Rf
5)をスレフショルドとする内部電源に接続される。(
6)は出力端子(7)に出力パルスを生じさせる論理処
理回路である。(8)はコンデンサの充電開始電位を決
める外付は端子、(9)はバッファAmPである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a pulse generation circuit that is an embodiment of the present invention. In the figure, (11 is an input trigger pulse, (2) is an internally determined constant current source, (3) and (4) are comparators. and the reference potential vr*r+51 and VF*f+I Rf, respectively.
5) is connected to the internal power supply with threshold. (
6) is a logic processing circuit that generates an output pulse at the output terminal (7). (8) is an external terminal that determines the charging start potential of the capacitor, and (9) is a buffer AmP.

次に動作について説明する。Next, the operation will be explained.

入力トリガが入ると、トランジスタSWはONし、コン
デンサCの充電端子電位はバッファ出力DC電位V、と
なる。トリガパルスfl+がOFF後トランジスタSW
はOFFとなり、内部コンデンサCに内部固定の定電流
源(2)で定められた定電流が流れ、電荷が蓄積され始
める為、コンデンサ端子電位vcは時間と共に、第2図
波形すに示す様に、直線的に増加していく、比較器(3
)、比較器(4)の基準電位をそれぞれ(5)の基$電
位vref 、  V、□+IHに設定して置き、コン
デンサCへの充電電位がこのIRを横切る時間のみ出力
する様な論理処理回路(6)を設置して置けば、第2図
波形Cに示す様な出力パルスか出力端子(7)より得ら
れる。
When an input trigger is applied, the transistor SW is turned on, and the charging terminal potential of the capacitor C becomes the buffer output DC potential V. After trigger pulse fl+ turns off, transistor SW
is turned OFF, a constant current determined by an internally fixed constant current source (2) flows through the internal capacitor C, and charge begins to accumulate.As a result, the capacitor terminal potential vc changes over time as shown in the waveform in Figure 2. , linearly increasing comparator (3
), the reference potential of the comparator (4) is set to the base potential of (5) vref, V, □+IH, respectively, and logic processing is performed such that it outputs only the time when the charging potential to the capacitor C crosses this IR. If the circuit (6) is installed, an output pulse as shown in waveform C in FIG. 2 can be obtained from the output terminal (7).

2つの基準電位V1.1及びvrot + I Rは内
部で決められる一定値である為、出力パルスの入力トリ
ガからの位置は、外付は端子(8)によるコンデンサC
の充電開始電位の調整によりリニアにI!11m可能と
なる。また、スレソショルド間電圧IRは一定であり、
コンデンサCへの充電も常に一定である為、パルス幅の
精度は位置によらず一定となる。
Since the two reference potentials V1.1 and vrot + I R are fixed values determined internally, the position of the output pulse from the input trigger is determined by the capacitor C connected to the external terminal (8).
By adjusting the charging start potential of I! 11m is possible. In addition, the threshold voltage IR is constant,
Since the charge to the capacitor C is always constant, the accuracy of the pulse width is constant regardless of the position.

トリガパルスからの位置を14、パルス幅をt。The position from the trigger pulse is 14, and the pulse width is t.

とすると、 1、  = (3) ■ 1             1 で表される、従って、出力パルス幅は内部で決まるCR
で一定値となり、また入力トリガからの位置は外部より
制御されるV、によって調整可能となる。
Then, 1, = (3) ■ 1 1 Therefore, the output pulse width is determined internally by CR
is a constant value, and the position from the input trigger can be adjusted by externally controlled V.

なお、上記実施例では入力トリガパルスよりパルス幅が
一定で位置のみ可変であるパルス発生回路の場合につい
て説明したが、このパルス発生回路はパーストゲートパ
ルスの他、パルス幅が位置に無関係である必要のある総
てのサンプリングパルス回路に対しても適用が可能であ
る。
In addition, in the above embodiment, the case of a pulse generation circuit in which the pulse width is constant compared to the input trigger pulse and only the position is variable was explained, but this pulse generation circuit requires that the pulse width is independent of the position in addition to the burst gate pulse. It is also applicable to all sampling pulse circuits.

〔発明の効果〕〔Effect of the invention〕

以上の様にこの発明によれば、パルス位置を決める内部
コンデンサ充電開始電位を外部より制御可能としたので
、1ピンで安定な幅を持ったパルスの、位置のみを調整
可能なパルス発生回路が得られるという効果がある。
As described above, according to the present invention, since the charging start potential of the internal capacitor that determines the pulse position can be controlled from the outside, a pulse generation circuit that can only adjust the position of a pulse with a stable width using one pin can be created. There is an effect that can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すパルス発生回路の回
路図、第2図は第1図の回路の各波形図、第3図、第4
図、第7図はそれぞれ従来のパルス発生回路の回路図、
第5図、第6図、第8図はそれぞれ第3図、第4図、第
7図の回路の波形図である。 (1)−・−入力トリガパルス、(2)・−・・電流源
、+31. (4)・−・比較器、(5)−・−基準電
位、16+−・論理処理回路、(7)−・・・−出力端
子、(8)−・−外部制御電圧端子、(91−バソファ
AmP、Oトートランジスタスイッチ。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a circuit diagram of a pulse generation circuit showing an embodiment of the present invention, FIG. 2 is a waveform diagram of the circuit of FIG. 1, and FIGS.
Figure 7 is a circuit diagram of a conventional pulse generation circuit, respectively.
5, 6, and 8 are waveform diagrams of the circuits of FIGS. 3, 4, and 7, respectively. (1) --- input trigger pulse, (2) --- current source, +31. (4)--Comparator, (5)--Reference potential, 16+--Logic processing circuit, (7)--Output terminal, (8)--External control voltage terminal, (91- Bath sofa AmP, O-to transistor switch. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 第1の基準電圧とこの基準電圧に出力パルス幅を決める
バイアス電源を加えた第2の基準電圧をそれぞれスレッ
ショルド電圧とする第1と第2の比較器に、定電流充電
を行うコンデンサ電圧を入力し、前記コンデンサの充電
開始電圧を外部可変電源により制御可能とし、入力トリ
ガパルス後、前記2つのスレッショルド電圧間にのみパ
ルスを発生させるパルス発生回路において、前記外部可
変電源により幅一定のまま入力トリガからの位置のみを
変化させる様にしたことを特徴とするパルス発生回路。
The capacitor voltage that performs constant current charging is input to the first and second comparators whose threshold voltages are the first reference voltage and the second reference voltage obtained by adding a bias power supply that determines the output pulse width to this reference voltage. In the pulse generation circuit, the charging start voltage of the capacitor can be controlled by an external variable power supply, and after an input trigger pulse, a pulse is generated only between the two threshold voltages. A pulse generation circuit characterized by changing only the position from .
JP1200637A 1989-08-02 1989-08-02 Pulse generating circuit Pending JPH0364207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1200637A JPH0364207A (en) 1989-08-02 1989-08-02 Pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1200637A JPH0364207A (en) 1989-08-02 1989-08-02 Pulse generating circuit

Publications (1)

Publication Number Publication Date
JPH0364207A true JPH0364207A (en) 1991-03-19

Family

ID=16427702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1200637A Pending JPH0364207A (en) 1989-08-02 1989-08-02 Pulse generating circuit

Country Status (1)

Country Link
JP (1) JPH0364207A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010525747A (en) * 2007-04-23 2010-07-22 クゥアルコム・インコーポレイテッド Apparatus and method for generating fine timing from a coarse timing source

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010525747A (en) * 2007-04-23 2010-07-22 クゥアルコム・インコーポレイテッド Apparatus and method for generating fine timing from a coarse timing source

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