JP3093361B2 - Time constant automatic adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic time constant adjusting circuit for controlling a bias current or the like of a filter circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional time constant adjusting circuit. The reference voltage generation circuit 1 outputs a reference voltage Vref and a certain difference voltage ΔVi from the generated voltage. Clock signal C from a reference signal generation circuit (not shown)
K1 is input and the other output terminal of the current path switch 5 for switching the current path of the current source 6 is subjected to voltage-current conversion (G
m) Connect to amplifier 2. In the Gm amplifier 2, the difference voltage △ V
Input i and perform voltage-current conversion. Converted current output I
01 and I02 are input to the single-ended circuit 10 to make the current single-ended and flow to the integrating capacitor 7. The other output terminal of the current path switch 5 is connected to the capacitor 7. The peak hold circuit 3 detects the peak of the voltage waveform of the capacitor 7 and uses the hold capacitor 8 to hold the peak voltage Vp until the next peak. Peak voltage Vp
And the reference voltage Vref are input to the comparison circuit 4. The comparison result is stabilized by the smoothing capacitor 9 and the current source 6 is controlled by the comparison output.

The operation of FIG. 4 will be described in more detail with reference to the waveform diagram of FIG. The clock signal CK1 is shown in FIG.
Assume that the signal is as shown in (a), and when the voltage of the capacitor 7 decreases, a clamp circuit (not shown) operates. Since the difference voltage △ Vi voltage is applied, G
The output current of the m amplifier 2 has a different value. In FIG. 4, the relationship between the current outputs I01 and I02 of the Gm amplifier 2 and the bias current IB of the current source 6 is expressed as I01> I02 (I01 + I02 = I
B). When a current flows through the Gm amplifier 2 when the pulse of the clock signal CK1 is Hi, the output current of the Gm amplifier 2 appears only in a half cycle of the clock signal CK1.
When this current is passed through the single-ended circuit 10, the difference component (I01-I02) is output. Therefore, during this period, the capacitor 7 is charged and rises as shown in FIG. When the pulse of the clock signal CK1 is Lo, the output of the current path switch 5 is on the capacitor side. At this time, there is no current output from the single-ended circuit 10, and the entire bias current IB flows to the capacitor 7 and discharges. At this time, the voltage waveform of the capacitor 7 sharply falls as shown in FIG. 5B, and when the voltage waveform becomes sufficiently low, the clamp circuit operates and becomes constant at a predetermined voltage.

The peak hold circuit 3 holds the peak voltage Vp of the waveform (b). The comparison circuit 4 compares the peak voltage Vp with the reference voltage Vref, applies negative feedback to the current source 6, and controls the peak voltage Vp and the reference voltage Vref to be equal.

Japanese Patent Application No. 2-33 filed earlier by the same applicant.
As described in Japanese Patent No. 5635 and the like, by controlling the current source in such a manner, the time constant represented by the product of the resistor and the capacitor built in the IC or the ratio of the current to the capacitor can be kept constant. .

FIG. 6 shows a specific example of the Gm amplifier 2.
The one using a differential amplifier as shown in FIG.
This differential amplifier takes several nS to several tens of nS until an output current appears even when the bias current source 6 is turned on. Also, at the time of the rise of the current-on, since Gm increases from a minute level, it is not constant. Therefore,
The rising waveform in FIG. 5B is slightly reduced at the moment of turning on, as indicated by the dotted line. This is the clock signal CK
This indicates that the voltage to be originally reached is not reached during one half cycle period, and the automatically adjusted time constant is shifted. Also, since this period varies with temperature, the adjusted current will drift with temperature.

[0007]

In the conventional time constant automatic adjustment circuit described above, it takes time for the output current to rise when the power of the Gm amplifier is turned on, and the automatically adjusted time constant deviates. Current drifts with temperature.

An object of the present invention is to provide a time constant automatic adjustment circuit which is less likely to cause time constant adjustment deviation and temperature drift.

[0009]

According to the present invention, the current source switching means is applied to the output current of the Gm amplifier, and the discharging operation of the capacitor is performed by a single-ended circuit.

[0010]

In this manner, the Gm amplifier does not operate by switching, and the output current becomes DC. Further, since a current always flows through a part of the single-ended circuit, the transient response at the time of the switching operation is smooth and fast, so that the deviation of the adjustment current and the temperature drift which have conventionally occurred can be greatly improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG.

The reference voltage generating circuit 1 generates a reference voltage V
ref and a certain difference voltage ΔVi are output. The Gm amplifier 21 receives the difference voltage ΔVi and receives 2 based on the bias current IB.
To produce two output currents I01 and I02 (I01> I0)
2). These current outputs I01 and I02 are connected to the current path switch 1
1 and switches the path at the timing of the clock signal CK <b> 1 and outputs it to the single-ended circuit 101. The output current of the single-ended circuit 101 is supplied to the capacitor 7 and charged. Capacitor voltage peak hold circuit 3
, And holds the peak voltage Vp of the charging waveform. The peak voltage Vp and the reference voltage Vref are input to the comparison circuit 4, and the comparison result is smoothed by the smoothing capacitor 9 to control the control current source 6.

Since the current path switch 11 is arranged for the output current of the Gm amplifier 21, the Gm amplifier 21
Operates at DC. Therefore, the ON which occurred conventionally
There is no delay time due to / OFF, and no error current occurs here.

FIG. 2 shows a specific example of the current path switch 11 and the single end circuit 10. The current output I01 of the Gm amplifier 21 is supplied to the common emitter of the transistors Q5 and Q6, and the collector of the transistor Q5 is connected to the transistors Q7 and Q8 and the first current mirror circuit CM1 of the resistors R1 and R2. The collector of the transistor Q6 is connected to the transistors Q9 and Q10 together with the current output I02.
And a second current mirror circuit CM including resistors R3 and R4.
Connect to 2. The output current of the second current mirror circuit CM2 is input to a third current mirror circuit CM3 comprising transistors Q11 and Q12 and resistors R5 and R6, and the collector of the transistor Q12 and the collector of Q8 are connected to form a single-ended current. Create

The current path switch 11 includes a transistor Q5
, Q6, and the switching operation is performed by the clock signal CK2.
And the clock signal CK3 having the opposite polarity. The transistors Q5 and Q6 receive the clock signal CK input to the base.
2. Since the differential amplifier is operated by CK3, the switching time is the same when the transistor Q5 is turned on and when the transistor Q6 is turned on, and the delay time is constant.

First, in the case of the charging operation, the clock signal CK
2 turns on transistor Q5. The current output I01 passes through the transistor Q5 and the first current mirror circuit CM1, and is led to an output terminal Iout. The output current I02 passes through the second and third current mirror circuits CM2 and CM3 and is output to the output terminal Iout, and the charging current (I01> I02) of the result I01-I02 is output.

In the case of a discharging operation, the transistor Q6 turns on. Since the current output I01 flows through the transistor Q6 to the second and third current mirror circuits CM2 and CM3, all of the bias current IB is supplied to the output terminal Iout.
Output to At this time, the discharge current becomes the bias current IB as in the related art.

As described above, since a predetermined current always flows through the second and third current mirror circuits CM2 and CM3, the current mirror circuit CM2 and CM3 follow quickly even when the current level changes by switching. Since the time for responding to the current change is shorter than in the conventional case where the cutoff is performed, the time for generating the error is short, so that the transient response factors that cause the adjustment deviation and the temperature drift can be drastically reduced.

The above description has been made on the case of operating at the timing of FIG. 5. However, the automatic adjustment circuit which operates at the timing as shown in FIG. 3 of Japanese Patent Application No. 2-335635 filed by the applicant has been described. By adding a current path switch 11 for the current output I02 and means for bypassing the current to the power supply for the current outputs I01 and I02, the same effect as the present invention can be realized.

[0020]

As described above, according to the automatic time-constant adjustment circuit of the present invention, the time-constant adjustment deviation and the temperature drift can be reduced.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a main part of FIG. 1;

FIG. 3 is another charge / discharge waveform diagram handled in FIG.

FIG. 4 is a system diagram showing a conventional time constant automatic adjustment circuit.

FIG. 5 is a charge / discharge waveform diagram of FIG.

FIG. 6 is a circuit diagram showing an example of the Gm amplifier of FIGS. 1 and 5;

[Explanation of symbols]

 1 Reference voltage generation circuit 3 Peak hold circuit 4 Comparison circuit 6 Current source 7 Capacitor 21 Gm amplifier 11 Current path switch 101 Single End circuit

Claims (1)

(57) [Claims] 1. A voltage-current conversion amplifier and a current path provided on its output side using a timing pulse serving as a time reference.
A charging / discharging waveform generating circuit for generating a charging / discharging waveform by a switch means for switching the charge / discharge waveform; a capacitor for performing charging / discharging based on the charging / discharging waveform of the charging / discharging waveform generating circuit; and an amplitude of the charging / discharging waveform of the charging / discharging waveform generating circuit. To detect
Constant automatic adjusting circuit, characterized in that a control circuit for controlling the amplitude of the comparison to said charging discharging waveform and a detected amplitude and the reference voltage.